Wafer surface dielectric layer modification and graph control method suitable for hybrid bonding

Abstract

The invention relates to a wafer surface dielectric layer modification and pattern control method for hybrid bonding, and the method comprises the following steps: carrying out the first CMP technology processing of a wafer surface dielectric layer, and enabling a metal layer to be in a protruding shape relative to the surface dielectric layer; pECVD (Plasma Enhanced Chemical Vapor Deposition) process treatment is carried out on the surface dielectric layer subjected to the first CMP process treatment, and a modified dielectric layer is deposited; performing second CMP process treatment on the modified dielectric layer to enable the upper surface of the metal layer to be flush with the upper surface of the modified dielectric layer and expose the upper surface of the metal layer; and performing third CMP process treatment on the exposed upper surface of the metal layer, so that the metal layer is in a concave shape relative to the upper surface of the modified dielectric layer. According to the method disclosed by the invention, the treatment flow of the process is simplified, and meanwhile, the bonding strength of mixed bonding can be improved and can be improved to 2.2-2.5 J / m < 2 > from the previous 1.5-1.8 J / m < 2 >.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor packaging, and in particular to a wafer surface dielectric layer modification and pattern control method suitable for hybrid bonding. Background Art

[0002] Hybrid bonding technology is the core technology for achieving high-performance three-dimensional heterogeneous integration. Hybrid bonding is a bump-free bonding method that achieves permanent bonding through metal bonding and surface dielectric layer bonding. In order to obtain high-quality bonding, the planarization of the pad and the surface dielectric layer must be met. The pad needs to have a certain concave morphology relative to the surface dielectric layer, and the bulk properties and surface roughness of the surface dielectric layer play a decisive role in the bonding strength of hybrid bonding.

[0003] In the modification method of the surface dielectric layer in the prior art, generally, the newly added modified dielectric layer needs to be etched at the metal pad position to expose the metal pad below, and this process increases the mask preparation and etching process; after etching, the metal pad position is exposed, and seed deposition and metal electroplating are required, and this process increases the deposition seed layer and metal electroplating process; after electroplating the metal layer, it needs to be CMP coarse and fine grinding to form a concave morphology of the metal layer, and this process increases the CMP coarse and fine grinding process of the metal layer. The method of the prior art has the problems of complex process and low bonding strength of the original surface dielectric layer hybrid bonding. Summary of the invention

[0004] In view of the above analysis, the present invention provides a method for modifying and patterning a wafer surface dielectric layer suitable for hybrid bonding, which is used to solve the problems of the prior art methods, such as complex processes, increased processing difficulty and cost, and low bonding strength of the original surface dielectric layer hybrid bonding.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] A method for modifying a wafer surface dielectric layer and controlling a pattern suitable for hybrid bonding comprises the following steps:

[0007] (1) performing a first CMP process on the dielectric layer on the surface of the wafer so that the metal layer has a convex morphology relative to the dielectric layer on the surface;

[0008] (2) performing a PECVD process on the surface dielectric layer treated by the first CMP process to deposit a modified dielectric layer;

[0009] (3) performing a second CMP process on the modified dielectric layer to make the upper surface of the metal layer flush with the upper surface of the modified dielectric layer, exposing the upper surface of the metal layer;

[0010] (4) The exposed upper surface of the metal layer is subjected to a third CMP process, so that the metal layer has a concave morphology relative to the upper surface of the modified dielectric layer.

[0011] Furthermore, the metal layer includes a Cu, Ag or Au pad.

[0012] Furthermore, the surface dielectric layer is SiN or SiO 2 .

[0013] Furthermore, in step (1), the protrusion size of the metal layer relative to the surface dielectric layer is 50-200 nm.

[0014] Furthermore, in step (2), the thickness of the modified dielectric layer is greater than the protruding size of the metal layer relative to the surface dielectric layer.

[0015] Furthermore, the modified dielectric layer is SiCN or SiON.

[0016] Furthermore, the thickness of the modified dielectric layer is 100-300 nm.

[0017] Furthermore, in step (2), the temperature during the PECVD process is 300-450°C.

[0018] Furthermore, in step (3), the roughness Rq of the modified dielectric layer treated by the second CMP process is less than 0.5 nm.

[0019] Furthermore, in step (4), the depression size of the metal layer relative to the upper surface of the modified dielectric layer is 5-50 nm.

[0020] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0021] The method of the present invention sequentially processes through the first CMP process, the PECVD process, the second CMP process and the third CMP process, and does not require etching and electroplating of the metal layer position, thereby reducing the rough grinding and fine grinding process of the metal layer and the corresponding equipment requirements. The method of the present invention is simpler and more convenient, simplifies the process flow and reduces the manufacturing cost. At the same time, compared with the prior art, the method of the present invention can improve the bonding strength of the surface dielectric layer hybrid bonding, and the bonding strength can be increased from the previous 1.5-1.8 J / m 2 Increase to 2.2-2.5J / m 2 .

[0022] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0024] Figure 1 It is a schematic flow chart of a method for modifying a dielectric layer on a hybrid-bonded wafer surface in the prior art;

[0025] Figure 2 The present invention is a schematic flow chart of a hybrid-bonded wafer surface dielectric layer modification and pattern control method.

[0026] Reference numerals:

[0027] 1-wafer substrate layer, 2-device layer, 3-surface dielectric layer, 4-metal layer, 5-modified dielectric layer, 6-electroplated metal layer. DETAILED DESCRIPTION

[0028] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present invention and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0029] A specific embodiment of the present invention, as Figure 2 As shown, a method for modifying a wafer surface dielectric layer and controlling a pattern suitable for hybrid bonding is disclosed, comprising the following steps:

[0030] (1) performing a first CMP process on the surface dielectric layer 3 of the wafer so that the metal layer 4 is convex relative to the surface dielectric layer 3;

[0031] (2) performing a PECVD process on the surface dielectric layer 3 treated by the first CMP process to deposit a modified dielectric layer 5;

[0032] (3) performing a second CMP process on the modified dielectric layer 5 to make the upper surface of the metal layer 4 flush with the upper surface of the modified dielectric layer 5, exposing the upper surface of the metal layer 4;

[0033] (4) The exposed upper surface of the metal layer 4 is subjected to a third CMP process, so that the metal layer 4 has a concave morphology relative to the upper surface of the modified dielectric layer 5.

[0034] It should be noted that the modification method of the dielectric layer on the surface of the wafer in the prior art is as follows: Figure 1 First, a modified dielectric layer 5 is deposited on the surface dielectric layer 3 by using a PECVD process, and the modified dielectric layer 5 is processed by a CMP process, and the metal layer 4 is etched to expose the underlying metal layer 4, and then seed deposition and metal electroplating are performed to form an electroplated metal layer 6. The electroplated metal layer 6 needs to be subjected to CMP rough grinding and fine grinding to form a metal concave morphology, thereby completing the modification of the dielectric layer on the wafer surface.

[0035] Compared with the prior art, the method of the present invention sequentially processes through the first CMP process, the PECVD process, the second CMP process and the third CMP process, and does not require the metal layer 4 to be etched and electroplated, thereby reducing the rough grinding and fine grinding processes of the metal layer 4. The method of the present invention is simpler and more convenient, simplifies the process flow and reduces the manufacturing cost. At the same time, the method of the present invention can improve the bonding strength of the hybrid bonding, and the bonding strength can be increased from the previous 1.5-1.8 J / m 2 Increase to 2.2-2.5J / m 2 .

[0036] It should be noted that the processes before the hybrid bonded wafer surface dielectric layer is modified are all prepared by existing methods. First, a device layer 2 is prepared on a wafer substrate layer 1, and a metal layer 4 and a surface dielectric layer 3 are prepared on the device layer 2. For details, refer to the integrated circuit preparation process, for example, 28 nanometers, 14 nanometers, 7 nanometers, 5 nanometers, etc.

[0037] In a specific embodiment, the metal layer 4 includes Cu, Ag or Au pads.

[0038] In a specific embodiment, the surface dielectric layer 3 is SiN or SiO 2 .

[0039] In a specific embodiment, in step (1), the metal layer 4 protrudes from the surface dielectric layer 3 by a size of 50-200 nm, for example, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm.

[0040] It should be noted that the protrusion size is adjusted according to the size of the pad. If the pad size is small, the protrusion size is required to be small.

[0041] Specifically, the first CMP process uses Slurry parameters: pH 2-4, average particle size 50-200nm, viscosity 0.5-1mPa·s, flow rate 100-500ml / min; CMP process pressure from edge to center is 1-10psi, upper turntable speed is 60-100RPM, and lower turntable speed is 50-90RPM.

[0042] In a specific embodiment, in step (2), the thickness of the modified dielectric layer 5 is greater than the protruding dimension of the metal layer 4 relative to the surface dielectric layer 3 .

[0043] In a specific embodiment, the modified dielectric layer 5 is SiCN or SiON.

[0044] In a specific embodiment, the modified medium layer 5 has a thickness of 100-300 nm, for example, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm.

[0045] In a specific embodiment, in step (2), the temperature during the PECVD process is 300-450° C. For example, the temperature is 300° C., 320° C., 340° C., 360° C., 380° C., 400° C., 420° C., 440° C., 450° C.

[0046] It should be noted that the above temperature is the decomposition temperature range of the organic raw materials in the modified medium layer 5 .

[0047] In a specific embodiment, in step (3), the roughness Rq of the modified dielectric layer treated by the second CMP process is less than 0.5 nm.

[0048] Specifically, the second CMP process uses Slurry parameters: pH 2-4, average particle size 50-200nm, viscosity 0.5-1mPa·s, flow rate 100-500ml / min; CMP process pressure from edge to center is 1-10psi, upper turntable speed is 60-100RPM, and lower turntable speed is 50-90RPM.

[0049] In a specific embodiment, in step (4), the concave size of the metal layer 4 relative to the upper surface of the modified dielectric layer 5 is 5-50 nm. For example, the concave size is 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm.

[0050] It should be noted that the recess size is related to the amount of metal expansion during hybrid bonding. If the metal expansion is too small, the bonding interface between the edge of the metal layer and the surface dielectric layer 3 is prone to stratification. If it is too large, the metal expansion is insufficient during heating during bonding, and the metal and metal layers cannot be bonded together. In addition, the selection range is related to the size of the metal layer. The smaller the metal layer, the smaller this value is required to be.

[0051] Specifically, in step (4), the third CMP process uses Slurry parameters as follows: pH 6-8, average particle size 50-200 nm, viscosity 0.5-2 mPa·s, flow rate 100-500 ml / min; CMP process pressure from edge to center 2-12 psi, upper turntable speed 60-120 RPM, and lower turntable speed 50-110 RPM.

[0052] The technical solution of the present invention is explained below in conjunction with specific embodiments.

[0053] Example 1

[0054] The wafer size of this embodiment is 12 inches, the surface dielectric layer 3 is SiN, and the metal layer is a copper pad.

[0055] The present embodiment provides a wafer surface dielectric layer modification and pattern control method suitable for hybrid bonding, comprising the following steps:

[0056] (1) The wafer surface dielectric layer 3 is subjected to a first CMP process, so that the metal layer 4 is convex relative to the surface dielectric layer 3, and the convex size is 50 nm;

[0057] The first CMP process used Slurry parameters: pH 2, average particle size 50 nm, viscosity 0.5 mPa·s, flow rate 100 ml / min; CMP process pressure from edge to center 1 psi, upper turntable speed 60 RPM, lower turntable speed 50 RPM;

[0058] (2) performing a PECVD process on the surface dielectric layer 3 treated by the first CMP process to deposit a modified dielectric layer 5, wherein the modified dielectric layer 5 is SiCN with a thickness of 100 nm, and the temperature during the PECVD process is 300° C.;

[0059] (3) performing a second CMP process on the modified dielectric layer 5 to make the upper surface of the metal layer 4 flush with the upper surface of the modified dielectric layer 5, exposing the upper surface of the metal layer 4, and the roughness Rq of the modified dielectric layer after the second CMP process is less than 0.5 nm;

[0060] The second CMP process used Slurry parameters: pH 2, average particle size 50 nm, viscosity 0.5 mPa·s, flow rate 100 ml / min; CMP process pressure from edge to center 1 psi, upper turntable speed 60 RPM, lower turntable speed 50 RPM;

[0061] (4) performing a third CMP process on the exposed upper surface of the metal layer 4, so that the metal layer 4 has a concave morphology relative to the upper surface of the modified dielectric layer 5, and the concave size of the metal layer relative to the upper surface of the modified dielectric layer 5 is 5 nm;

[0062] The third CMP process uses Slurry parameters as follows: pH 6, average particle size 50 nm, viscosity 0.5 mPa·s, flow rate 100 ml / min; CMP process pressure from edge to center is 2 psi, upper turntable speed is 60 RPM, and lower turntable speed is 50 RPM.

[0063] Example 2

[0064] The wafer size of this embodiment is 12 inches, the surface dielectric layer 3 is SiN, and the metal layer is an Ag pad.

[0065] The present embodiment provides a wafer surface dielectric layer modification and pattern control method suitable for hybrid bonding, comprising the following steps:

[0066] (1) The wafer surface dielectric layer 3 is subjected to a first CMP process, so that the metal layer 4 is convex relative to the surface dielectric layer 3, and the convex size is 125 nm;

[0067] The first CMP process used Slurry parameters: pH 3, average particle size 130 nm, viscosity 0.75 mPa·s, flow rate 300 ml / min; CMP process pressure from edge to center 6 psi, upper turntable speed 80 RPM, lower turntable speed 70 RPM;

[0068] (2) performing a PECVD process on the surface dielectric layer 3 treated by the first CMP process to deposit a modified dielectric layer 5, wherein the modified dielectric layer 5 is SiON with a thickness of 200 nm, and the temperature during the PECVD process is 375° C.;

[0069] (3) performing a second CMP process on the modified dielectric layer 5 to make the upper surface of the metal layer 4 flush with the upper surface of the modified dielectric layer 5, exposing the upper surface of the metal layer 4, and the roughness Rq of the modified dielectric layer after the second CMP process is less than 0.5 nm;

[0070] The second CMP process used Slurry parameters: pH 3, average particle size 160 nm, viscosity 0.75 mPa·s, flow rate 300 ml / min; CMP process pressure from edge to center 5.5 psi, upper turntable speed 80 RPM, lower turntable speed 70 RPM;

[0071] (4) performing a third CMP process on the exposed upper surface of the metal layer 4, so that the metal layer 4 has a concave morphology relative to the upper surface of the modified dielectric layer 5, and the concave size of the metal layer relative to the upper surface of the modified dielectric layer 5 is 15 nm;

[0072] The third CMP process uses Slurry parameters as follows: pH 7, average particle size 125 nm, viscosity 1.25 mPa·s, flow rate 300 ml / min; CMP process pressure from edge to center is 7 psi, upper turntable speed is 90 RPM, and lower turntable speed is 30 RPM.

[0073] Example 3

[0074] The wafer size of this embodiment is 12 inches, and the surface dielectric layer 3 is SiO 2 , the metal layer is an Au pad.

[0075] The present embodiment provides a wafer surface dielectric layer modification and pattern control method suitable for hybrid bonding, comprising the following steps:

[0076] (1) The dielectric layer 3 on the surface of the wafer is subjected to a first CMP process, so that the metal layer 4 is convex relative to the dielectric layer 3 on the surface, and the convex size is 200 nm;

[0077] The first CMP process used Slurry parameters: pH 4, average particle size 200 nm, viscosity 1 mPa·s, flow rate 500 ml / min; CMP process pressure from edge to center 10 psi, upper turntable speed 100 RPM, lower turntable speed 90 RPM;

[0078] (2) performing a PECVD process on the surface dielectric layer 3 treated by the first CMP process to deposit a modified dielectric layer 5, wherein the modified dielectric layer 5 is SiON with a thickness of 300 nm, and the temperature during the PECVD process is 450° C.;

[0079] (3) performing a second CMP process on the modified dielectric layer 5 to make the upper surface of the metal layer 4 flush with the upper surface of the modified dielectric layer 5, exposing the upper surface of the metal layer 4, and the roughness Rq of the modified dielectric layer after the second CMP process is less than 0.5 nm;

[0080] The second CMP process used Slurry parameters: pH 4, average particle size 200 nm, viscosity 1 mPa·s, flow rate 500 ml / min; CMP process pressure from edge to center 10 psi, upper turntable speed 100 RPM, lower turntable speed 90 RPM;

[0081] (4) performing a third CMP process on the exposed upper surface of the metal layer 4, so that the metal layer 4 is concave relative to the upper surface of the modified dielectric layer 5, and the concave size of the metal layer relative to the upper surface of the modified dielectric layer 5 is 50 nm;

[0082] The third CMP process uses Slurry parameters as follows: pH 8, average particle size 200 nm, viscosity 2 mPa·s, flow rate 500 ml / min; CMP process pressure from edge to center is 12 psi, upper turntable speed is 120 RPM, and lower turntable speed is 110 RPM.

[0083] Example 4

[0084] The wafer size of this embodiment is 12 inches, and the surface dielectric layer 3 is SiO 2 , the metal layer is a copper pad.

[0085] The present embodiment provides a wafer surface dielectric layer modification and pattern control method suitable for hybrid bonding, comprising the following steps:

[0086] (1) The wafer surface dielectric layer 3 is subjected to a first CMP process, so that the metal layer 4 is convex relative to the surface dielectric layer 3, and the convex size is 80 nm;

[0087] The first CMP process used Slurry parameters: pH 2.5, average particle size 100 nm, viscosity 0.6 mPa·s, flow rate 200 ml / min; CMP process pressure from edge to center 8 psi, upper turntable speed 70 RPM, lower turntable speed 80 RPM;

[0088] (2) performing a PECVD process on the surface dielectric layer 3 treated by the first CMP process to deposit a modified dielectric layer 5, wherein the modified dielectric layer 5 is SiCN with a thickness of 250 nm, and the temperature during the PECVD process is 400° C.;

[0089] (3) performing a second CMP process on the modified dielectric layer 5 to make the upper surface of the metal layer 4 flush with the upper surface of the modified dielectric layer 5, exposing the upper surface of the metal layer 4, and the roughness Rq of the modified dielectric layer after the second CMP process is less than 0.5 nm;

[0090] The second CMP process used Slurry parameters: pH 3.5, average particle size 180 nm, viscosity 0.9 mPa·s, flow rate 200 ml / min; CMP process pressure from edge to center 3 psi, upper turntable speed 90 RPM, lower turntable speed 60 RPM;

[0091] (4) performing a third CMP process on the exposed upper surface of the metal layer 4, so that the metal layer 4 has a concave morphology relative to the upper surface of the modified dielectric layer 5, and the concave size of the metal layer relative to the upper surface of the modified dielectric layer 5 is 20 nm;

[0092] The third CMP process used Slurry parameters as follows: pH 6.5, average particle size 100 nm, viscosity 1.2 mPa·s, flow rate 200 ml / min; CMP process pressure from edge to center was 10 psi, upper turntable speed was 100 RPM, and lower turntable speed was 70 RPM.

[0093] Comparative Example 1

[0094] like Figure 1 The dielectric layer on the surface of the wafer is modified according to the method of the prior art.

[0095] The wafer size of this comparative example is 12 inches, the surface dielectric layer 3 is SiN, the metal layer is a copper pad, and the method is as follows:

[0096] (1) performing a PECVD process on the surface dielectric layer 3 to deposit a modified dielectric layer 5, wherein the modified dielectric layer 5 is SiCN with a thickness of 250 nm, and the temperature during the PECVD process is 400° C.;

[0097] (2) performing a first CMP process on the modified dielectric layer 5, wherein the roughness Rq of the modified dielectric layer after the first CMP process is less than 0.5 nm;

[0098] The first CMP process used Slurry parameters: pH 3.5, average particle size 180 nm, viscosity 0.9 mPa·s, flow rate 200 ml / min; the first CMP process pressure was 3 psi from edge to center, the upper turntable speed was 90 RPM, and the lower turntable speed was 60 RPM;

[0099] (3) etching the modified dielectric layer 5 after the CMP process, and exposing the metal layer 4 through processes such as coating, exposure, development, hardening, and wet etching;

[0100] The photoresist coating thickness is 2 μm and the exposure dose is 300 mJ / cm 2, hardening temperature is 300℃, wet etching solution is DHF;

[0101] (4) depositing a seed layer and electroplating copper on the modified dielectric layer 5 and the metal layer 4 after the etching process;

[0102] The seed layer is Ti metal with a thickness of 20nm, and the electroplated Cu has a thickness of 300nm;

[0103] (5) performing a second CMP process on the upper surface of the electroplated metal layer 6, so that the electroplated metal layer 6 has a concave morphology relative to the upper surface of the modified dielectric layer 5, and the concave size of the metal layer relative to the upper surface of the modified dielectric layer 5 is 50 nm;

[0104] The second CMP process used Slurry parameters: pH 6.5, average particle size 100 nm, viscosity 1.2 mPa·s, flow rate 200 ml / min; CMP process pressure from edge to center was 10 psi, upper turntable speed was 100 RPM, and lower turntable speed was 70 RPM.

[0105] Test Example 1

[0106] The bonding strength of the mixed bonds modified by the methods of Examples 1-4 and Comparative Example 1 was tested, and the results are shown in Table 1.

[0107] Table 1

[0108] Group Example 1 Example 2 Example 3 Example 4 Comparative Example 1 <![CDATA[Bonding strength (J / m 2 )]]> 2.5 2.3 2.1 2.4 1.8

[0109] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for modifying and patterning a wafer surface dielectric layer suitable for hybrid bonding, characterized in that: The steps include: (1) performing a first CMP process on the dielectric layer on the surface of the wafer so that the metal layer has a convex morphology relative to the dielectric layer on the surface; (2) performing a PECVD process on the surface dielectric layer treated by the first CMP process to deposit a modified dielectric layer; (3) performing a second CMP process on the modified dielectric layer to make the upper surface of the metal layer flush with the upper surface of the modified dielectric layer, exposing the upper surface of the metal layer; (4) The exposed upper surface of the metal layer is subjected to a third CMP process, so that the metal layer has a concave morphology relative to the upper surface of the modified dielectric layer.

2. The method for modifying the dielectric layer on the surface of a wafer and controlling the pattern of the wafer suitable for hybrid bonding according to claim 1, characterized in that: The metal layer includes Cu, Ag or Au pads.

3. The method for modifying the wafer surface dielectric layer and controlling the pattern suitable for hybrid bonding according to claim 1, characterized in that: The surface dielectric layer is SiN or SiO2.

4. A method for modifying a wafer surface dielectric layer and controlling a pattern suitable for hybrid bonding according to any one of claims 1 to 3, characterized in that: In step (1), the protrusion size of the metal layer relative to the surface dielectric layer is 50-200 nm.

5. A method for modifying a wafer surface dielectric layer and controlling a pattern suitable for hybrid bonding according to any one of claims 1 to 3, characterized in that: In step (2), the thickness of the modified dielectric layer is greater than the protruding size of the metal layer relative to the surface dielectric layer.

6. The method for modifying the wafer surface dielectric layer and controlling the pattern suitable for hybrid bonding according to claim 5, characterized in that: The modified dielectric layer is SiCN or SiON.

7. The method for modifying the dielectric layer on the surface of a wafer and controlling the pattern suitable for hybrid bonding according to claim 5, characterized in that: The thickness of the modified medium layer is 100-300nm.

8. The method for modifying the wafer surface dielectric layer and controlling the pattern suitable for hybrid bonding according to claim 5, characterized in that: In step (2), the temperature during the PECVD process is 300-450°C.

9. The method for modifying the wafer surface dielectric layer and controlling the pattern suitable for hybrid bonding according to claim 1, characterized in that: In step (3), the roughness Rq of the modified dielectric layer treated by the second CMP process is less than 0.5 nm.

10. The method for modifying the wafer surface dielectric layer and controlling the pattern suitable for hybrid bonding according to claim 1, characterized in that: In step (4), the depression size of the metal layer relative to the upper surface of the modified dielectric layer is 5-50 nm.

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