Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a first unit FET provided on the substrate and including a first source electrode, a first drain electrode, and a first gate electrode; a second unit FET provided on the substrate in the first direction with respect to the first unit FET, the second unit FET including a second source electrode, a second drain electrode, and a second gate electrode; a first source wiring extending in the first direction and provided on the first source electrode, the first source wiring being in electrical contact with the first source electrode; a gate bus bar which is provided so that the first gate electrode is disposed between the gate bus bar and the second gate electrode in the first direction, and which is electrically connected to the first gate electrode; and a gate wiring provided above the first source electrode so as not to be in contact with the first source electrode, the first source wiring being disposed between the gate wiring and the first drain electrode in the second direction, the gate wiring extending in the first direction and electrically connecting the gate bus bar and the second gate electrode.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] It is known that in a field effect transistor (FET) having finger-shaped source electrodes, gate electrodes, and drain electrodes, a plurality of unit FETs having source electrodes, gate electrodes, and drain electrodes are arranged in the extending direction of the electrodes (for example, Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351

[0006] Patent Document 2: U.S. Patent No. 9786660

[0007] In Patent Documents 1 and 2, by configuring a plurality of unit FETs in the extension direction of the electrode, the width of the gate electrode in the unit FET can be shortened. Therefore, the gate resistance can be suppressed. However, the gate wiring that electrically connects the gate pad to the gate electrode far from the gate pad is provided above the unit FET. As a result, the parasitic capacitance between the gate wiring and the drain electrode increases, and characteristics such as gain deteriorate. On the other hand, if the gate wiring is configured so as not to overlap with the unit FET, the semiconductor device will be large-scale. Summary of the invention

[0008] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of characteristics and achieve miniaturization.

[0009] One embodiment of the present disclosure is a semiconductor device, which includes: a substrate; a first unit FET, which is provided on the substrate and includes a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction; a second unit FET, which is provided on the substrate in the first direction relative to the first unit FET and includes a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction; a first source wiring extending in the first direction and provided on the first source electrode, The first source electrode is electrically in contact; a gate bus is arranged in a manner that the first gate electrode is configured between the gate bus and the second gate electrode in the first direction, and the gate bus is electrically connected to the first gate electrode; and a gate wiring is arranged above the first source electrode in a non-contact manner with the first source electrode, and the first source wiring is configured between the gate wiring and the first drain electrode in the second direction, the gate wiring extends in the first direction, electrically connects the gate bus to the second gate electrode, and the maximum width in the first direction of the area where the first source wiring contacts the first source electrode is greater than or equal to 1 / 2 times the maximum width in the first direction of the area where the first source wiring overlaps with the first source electrode when observed from the thickness direction of the substrate.

[0010] One embodiment of the present disclosure is a method for manufacturing a semiconductor device, the method comprising the following steps: forming a first unit FET and a second unit FET on a substrate, wherein the first unit FET comprises a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and disposed between the first source electrode and the first drain electrode in a second direction intersecting the first direction, and the second unit FET is located in the first direction relative to the first unit FET, comprises a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and disposed between the second source electrode and the second drain electrode in the second direction; and A first source wiring, a second source wiring and a first drain wiring are formed, wherein the first source wiring extends in the first direction and is arranged on the first source electrode and is electrically in contact with the first source electrode, the second source wiring extends in the first direction and is arranged on the second source electrode and is electrically in contact with the second source electrode, and the first drain wiring extends in the first direction and is arranged on the first drain electrode and is electrically in contact with the first drain electrode; and a gate wiring is formed, wherein the gate wiring is arranged above the first source electrode in a non-contact manner with the first source electrode, and the first source wiring is configured between the gate wiring and the first drain electrode in the second direction, and the gate wiring extends in the first direction to electrically connect a gate bus to the second gate electrode.

[0011] Effects of the Invention

[0012] According to the present disclosure, it is possible to achieve miniaturization while suppressing degradation of characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a top view of the semiconductor device in Example 1.

[0014] Figure 2 yes Figure 1 A-A section view in.

[0015] Figure 3 yes Figure 1 B-B section view in.

[0016] Figure 4 yes Figure 1 C-C section view in.

[0017] Figure 5 yes Figure 1 D-D section view in.

[0018] Figure 6 yes Figure 1 E-E section view in.

[0019] Fig. 7A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0020] Figure 7B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Fig. 8A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Figure 8B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Fig.9A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Fig. 9B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0025] Fig. 10A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0026] Fig. 10B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0027] Fig.11A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0028] Fig. 11B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0029] Fig. 12A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0030] Fig. 12B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0031] Fig.13A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0032] Fig. 13B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0033] Fig.14A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0034] Fig. 14B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0035] Fig.15 3 is a cross-sectional view of a semiconductor device in Comparative Example 1.

[0036] Fig.16 is a cross-sectional view of a semiconductor device in Comparative Example 2.

[0037] Fig.17 This is a cross-sectional view of a semiconductor device in Modification 1 of Embodiment 1.

[0038] Fig.18 This is a cross-sectional view of a semiconductor device in Modification 1 of Embodiment 1.

[0039] Fig.19 It is a top view of a semiconductor device in a second variation of the first embodiment.

[0040] Fig. 20 yes Fig.19 A-A section view in.

[0041] Fig.21 yes Fig.19 B-B section view in.

[0042] Fig. 22 It is a top view of a semiconductor device in a third variation of the first embodiment.

[0043] Fig.23 yes Fig. 22 A-A section view in.

[0044] Fig.24 This is a cross-sectional view of a semiconductor device in Modification 4 of Embodiment 1.

[0045] Fig.25 This is a cross-sectional view of a semiconductor device in Modification 4 of Embodiment 1.

[0046] Fig.26 It is a cross-sectional view of a semiconductor device in a fifth variation of the first embodiment.

[0047] Fig. 27 It is a top view of a semiconductor device according to a sixth variation of the first embodiment.

[0048] Fig.28 yes Fig. 27 A-A section view.

[0049] Fig.29 This is a top view of the semiconductor device in Example 2.

[0050] Fig.30 yes Fig.29 A-A section view.

[0051] Fig.31It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0052] Fig.32 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0053] Fig.33 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0054] Fig.34 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0055] Fig.35 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0056] Fig.36 It is a top view of the semiconductor device in the first variation of the second embodiment.

[0057] Fig.37 yes Fig.36 A-A section view.

[0058] Fig.38 yes Fig.36 B-B section view.

[0059] Fig.39 This is a top view of the semiconductor device in Example 3.

[0060] Fig.40 yes Fig.39 A-A section view.

[0061] Fig.41 It is a top view of the semiconductor device in the first variation of the third embodiment.

[0062] Fig.42 It is a top view of the semiconductor device in the second variation of the third embodiment.

[0063] Fig.43 This is a top view of a semiconductor device in a third variation of the third embodiment.

[0064] Fig.44 This is a top view of the semiconductor device in Example 4.

[0065] Description of reference numerals:

[0066] 10, 10a: substrate

[0067] 10b: Semiconductor layer

[0068] 10c: Channel layer

[0069] 10d: Barrier layer

[0070] 11a, 11b, 11c: Active area

[0071] 12, 12a, 12b, 12c: source electrodes

[0072] 13: Passive zone

[0073] 14a, 14b, 14c, 14d, 14e: gate electrodes

[0074] 15: Field board

[0075] 16, 16a, 16b, 16a1, 16a2, 16b1, 16b2: drain electrode

[0076] 17: Connection wiring

[0077] 22, 22a, 22b, 22c: Source wiring

[0078] 23a, 23b, 44: Protective metal layer

[0079] 25, 25a: Opening

[0080] 26, 26a, 26b: Drain wiring

[0081] 28: Gate wiring

[0082] 29a, 29b, 29c: Connection wiring

[0083] 30: Via

[0084] 31: Space

[0085] 32, 32a: Metal layer

[0086] 34: Gate bus

[0087] 34a: Gate metal layer

[0088] 34b: Pad metal layer

[0089] 35a, 35b, 38a, 38b: Insulating film

[0090] 36: Drain bus

[0091] 38: Organic insulating film

[0092] 40, 45: Seed layer

[0093] 41, 42: coating layer

[0094] 43a, 43b: Location

[0095] 44: Protect the metal layer

[0096] 44a: Part of the protective metal layer

[0097] 47: Gap

[0098] 50, 52, 54, 56: Mask layer

[0099] 51, 53, 55, 57: Opening

[0100] 60, 60a, 60b, 60c, 60d, 60e: Unit FET

[0101] 62a, 62b, 62c: FET group

[0102] 64: Power Line

[0103] 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 120, 122: semiconductor devices. DETAILED DESCRIPTION

[0104] [Description of Embodiments of the Present Disclosure]

[0105] First, the contents of the embodiments of the present disclosure will be listed and described.

[0106] (1) One embodiment of the present disclosure is a semiconductor device, which includes: a substrate; a first unit FET provided on the substrate, including a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction; a second unit FET provided on the substrate in the first direction relative to the first unit FET, including a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction; a first source wiring extending in the first direction and provided on the first source electrode , electrically contacting the first source electrode; a gate busbar, arranged in such a way that the first gate electrode is arranged between the gate busbar and the second gate electrode in the first direction, and the gate busbar is electrically connected to the first gate electrode; and a gate wiring, arranged above the first source electrode in a non-contacting manner with the first source electrode, so that the first source wiring is arranged between the gate wiring and the first drain electrode in the second direction, the gate wiring extends in the first direction, electrically connecting the gate busbar to the second gate electrode, and the maximum width in the first direction of the area where the first source wiring contacts the first source electrode is greater than or equal to 1 / 2 times the maximum width in the first direction of the area where the first source wiring overlaps with the first source electrode when viewed from the thickness direction of the substrate. Thus, the gate-drain capacitance can be suppressed, and the degradation of the characteristics can be suppressed. In addition, the miniaturization of the semiconductor device can be achieved.

[0107] (2) In the above (1), the height of the upper surface of the gate wiring from the upper surface of the substrate may be smaller than the height of the upper surface of the first source wiring from the upper surface of the substrate. This can further suppress the gate-drain capacitance.

[0108] (3) Alternatively, in the above (1) or (2), the semiconductor device may include a first drain wiring extending in the first direction and provided on the first drain electrode, and electrically contacting the first drain electrode, and the thickness of the first source wiring is less than or equal to the thickness of the first drain wiring. Thus, the manufacturing process can be reduced.

[0109] (4) In any one of the above (1) to (3), the semiconductor device may include a second source wiring extending in the first direction and provided on the second source electrode, and electrically contacting the second source electrode, and the thickness of the first source wiring is equal to the thickness of the second source wiring. Thus, the manufacturing process can be reduced.

[0110] (5) In any one of the above (1) to (4), the semiconductor device may include: an inorganic insulating film provided on the first source electrode; and an organic insulating film or a gap provided between the inorganic insulating film and the gate wiring. This can reduce gate-source capacitance and suppress degradation of characteristics.

[0111] (6) In the above (5), the gate wiring may be in contact with the inorganic insulating film without the organic insulating film or the gap at a first portion of a portion in the first direction of the region where the gate wiring overlaps the first source electrode when viewed from the thickness direction of the substrate, and the organic insulating film or the gap is disposed between the gate wiring and the inorganic insulating film at a second portion of the region separated from the first portion in the first direction. Thus, the shape of the gate wiring can be stabilized.

[0112] (7) In any one of the above (1) to (6), the semiconductor device may include: a second source wiring extending in the first direction and provided on the second source electrode, and electrically contacting the second source electrode; and a first connecting wiring extending in the second direction, arranged between the first source electrode and the second source electrode in the first direction, and electrically connecting the gate wiring to the second gate electrode, and the first source wiring and the first connecting wiring intersecting with each other in a non-contact manner and connected to the second source wiring. Thus, the gate-drain capacitance can be further suppressed.

[0113] (8) It may also be that in any one of the above (1) to (7), the semiconductor device comprises: a third unit FET, provided on the substrate, comprising the first source electrode, a third drain electrode and a third gate electrode, wherein the third drain electrode extends in the first direction and the first source electrode is arranged between the third drain electrode and the first drain electrode in the second direction, and the third gate electrode extends in the first direction and is provided between the first source electrode and the third drain electrode in the second direction; a fourth unit FET, provided on the substrate in the first direction relative to the third unit FET, comprising the second source electrode, a fourth drain electrode and a fourth gate electrode, wherein the fourth drain electrode extends in the first direction and is provided between the first source electrode and the third drain electrode in the second direction. The second source electrode is arranged between the fourth drain electrode and the second drain electrode in the second direction, the fourth gate electrode extends in the first direction and is arranged between the second source electrode and the fourth drain electrode in the second direction; and a third source wiring extends in the first direction and is arranged on the first source electrode, the gate wiring is arranged between the third source wiring and the first source wiring in the second direction, and the third source wiring is in electrical contact with the first source electrode, and the maximum width in the first direction of the region where the third source wiring contacts the first source electrode is greater than or equal to 1 / 2 times the maximum width in the first direction of the region where the third source wiring overlaps with the first source electrode when viewed from the thickness direction of the substrate. Thus, miniaturization of the semiconductor device can be achieved.

[0114] (9) In the above (8), the semiconductor device may include a first connection wiring, which is arranged between the first source electrode and the second source electrode in the first direction, and electrically connects the second gate electrode and the fourth gate electrode, and the end of the gate wiring is connected to the center of the first connection wiring in the second direction. Thus, a gate potential can be supplied to the second gate electrode and the fourth gate electrode.

[0115] (10) In the above (8) or (9), the semiconductor device may include a protective metal layer, which is provided above the gate wiring in a non-contact manner with the gate wiring, and connects the first source wiring and the third source wiring. This can further suppress the gate-drain capacitance.

[0116] (11) In any one of the above (1) to (10), the semiconductor device may include: a fifth unit FET provided on the substrate, including a third source electrode, the first drain electrode, and a fifth gate electrode, wherein the third source electrode extends in the first direction and the first drain electrode is arranged between the third source electrode and the first source electrode in the second direction, and the fifth gate electrode extends in the first direction and is provided between the third source electrode and the first drain electrode in the second direction; a fourth source wiring extending in the first direction and provided on the third source electrode and electrically contacting the third source electrode; and a second connecting wiring provided between the first drain electrode and the gate bus in the first direction and electrically connecting the first source wiring and the fourth source wiring. Thus, the gate-drain capacitance can be further suppressed.

[0117] (12) One embodiment of the present disclosure is a method for manufacturing a semiconductor device, the method comprising the following steps: forming a first unit FET and a second unit FET on a substrate, wherein the first unit FET comprises a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction, and the second unit FET is located in the first direction relative to the first unit FET, comprises a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction; A first source wiring, a second source wiring, and a first drain wiring are formed simultaneously, wherein the first source wiring extends in the first direction and is disposed on the first source electrode, and is in electrical contact with the first source electrode, the second source wiring extends in the first direction and is disposed on the second source electrode, and is in electrical contact with the second source electrode, and the first drain wiring extends in the first direction and is disposed on the first drain electrode, and is in electrical contact with the first drain electrode; and a gate wiring is formed, wherein the gate wiring is disposed above the first source electrode in a non-contact manner with the first source electrode, and the first source wiring is arranged between the gate wiring and the first drain electrode in the second direction, and the gate wiring extends in the first direction to electrically connect the gate busbar to the second gate electrode. Thus, degradation of characteristics can be suppressed. In addition, miniaturization of semiconductor devices can be achieved. Moreover, manufacturing processes can be reduced.

[0118] [Details of the embodiments of the present disclosure]

[0119] Hereinafter, specific examples of semiconductor devices and methods of manufacturing the same according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0120] [Example 1]

[0121] A semiconductor device used as an amplifier for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a mobile communication base station will be described as an example. Figure 1 This is a top view of the semiconductor device in Example 1. Figures 2 to 6 They are Figure 1 The thickness direction of the substrate 10 is set to the Z direction, the extension direction of each finger-shaped electrode is set to the Y direction (first direction), and the arrangement direction of each electrode is set to the X direction (second direction intersecting the first direction).

[0122] In each figure, the source electrode 12, the gate electrode 14, the drain electrode 16, the source wiring 22, the drain wiring 26, and the unit FET 60 represent general elements, and the source electrode 12a, the source electrode 12b, the gate electrodes 14a to 14d, the drain electrode 16a, the drain electrode 16b, the source wiring 22a to 22c, the drain wiring 26a, the drain wiring 26b, and the unit FET 60a to 60d represent specific elements included in the general elements. In the following, the unit FET 60a to 60d is mainly described using the source electrode 12a, the source electrode 12b, the gate electrodes 14a to 14d, the drain electrode 16a, the drain electrode 16b, the source wiring 22a to 22c, the drain wiring 26a, and the drain wiring 26b.

[0123] like Figures 1 to 6 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The semiconductor layer 10b includes, for example, a channel layer 10c and a barrier layer 10d. On the XY plane parallel to the X direction and the Y direction, the region deactivated by ion implantation of the semiconductor layer 10b is the inactive region 13, and the region not deactivated is the active region 11a and the active region 11b.

[0124] The active region 11a and the active region 11b are arranged in the Y direction and extend in the X direction. The active region 11a is provided with a FET group 62a including a plurality of unit FETs 60 arranged in the X direction. The active region 11b is provided with a FET group 62b including a plurality of unit FETs 60 arranged in the X direction.

[0125] In the FET group 62a, the source electrode 12a (first source electrode), the gate electrode 14a (first gate electrode), the gate electrode 14c (third gate electrode), the drain electrode 16a (first drain electrode), and the drain electrode 16b (third drain electrode) extend in the Y direction. In the X direction, the source electrode 12a is arranged between the gate electrode 14a and the gate electrode 14c. In the X direction, the gate electrode 14a is arranged between the source electrode 12a and the drain electrode 16a, and the gate electrode 14c is arranged between the source electrode 12a and the drain electrode 16b. The unit FET 60a (first unit FET) includes the source electrode 12a, the gate electrode 14a, and the drain electrode 16a. The unit FET 60c (third unit FET) includes the source electrode 12a, the gate electrode 14c, and the drain electrode 16b. The source wiring 22a (first source wiring) and the source wiring 22c (third source wiring) are arranged on the source electrode 12a and are in electrical contact with the source electrode 12a. The source wiring 22 a and the source wiring 22 c extend in the Y direction and are arranged in the X direction.

[0126] In the FET group 62b, the source electrode 12b (second source electrode), the gate electrode 14b (second gate electrode), the gate electrode 14d (fourth gate electrode), the drain electrode 16a (second drain electrode), and the drain electrode 16b (fourth drain electrode) extend in the Y direction, respectively. In the X direction, the source electrode 12b is arranged between the gate electrode 14b and the gate electrode 14d. In the X direction, the gate electrode 14b is arranged between the source electrode 12b and the drain electrode 16a, and the gate electrode 14d is arranged between the source electrode 12b and the drain electrode 16b. The unit FET 60b (second unit FET) includes the source electrode 12b, the gate electrode 14b, and the drain electrode 16a. The unit FET 60d (fourth unit FET) includes the source electrode 12b, the gate electrode 14d, and the drain electrode 16b. The source wiring 22b (second source wiring) is arranged on the source electrode 12b and is in electrical contact with the source electrode 12b. The source wiring 22b extends in the Y direction.

[0127] The drain electrode 16a of the FET group 62a is provided integrally and continuously with the drain electrode 16a of the FET group 62b, and the drain electrode 16b of the FET group 62a is provided integrally and continuously with the drain electrode 16b of the FET group 62b. The drain wiring 26a (first drain wiring) and the drain wiring 26b (second drain wiring) are provided on the drain electrode 16a and the drain electrode 16b, respectively, and are in electrical contact with the drain electrode 16a and the drain electrode 16b, respectively. The drain wiring 26a and the drain wiring 26b extend in the Y direction. The drain bus 36 is provided in such a manner that the FET group 62b is arranged between the drain bus 36 and the FET group 62a in the Y direction. One end of the drain electrode 16a and the drain electrode 16b in the Y direction is connected to the drain bus 36.

[0128] The gate bus 34 is provided so that the FET group 62a is arranged between the gate bus 34 and the FET group 62b in the Y direction. The gate bus 34 includes a gate metal layer 34a and a pad metal layer 34b provided on the gate metal layer 34a. A connection wiring 29a is provided between the gate bus 34 and the FET group 62a in the Y direction. The connection wiring 29a extends in the X direction and connects the positive end of the gate electrode 14a in the Y direction to the positive end of the gate electrode 14c in the Y direction. The gate bus 34 is electrically connected to the gate electrode 14a and the gate electrode 14c via the connection wiring 29a to form a short circuit.

[0129] A connection wiring 29b is provided between the FET group 62a and the FET group 62b in the Y direction. The connection wiring 29b (first connection wiring) extends in the X direction, and connects the + end of the gate electrode 14b in the Y direction to the + end of the gate electrode 14d in the Y direction. The gate wiring 28 is provided above the source electrode 12a in a manner that is not in electrical contact with the source electrode 12a, and extends in the Y direction. The connection wiring 29a and the connection wiring 29b are electrically connected through the gate wiring 28. The gate bus 34 is electrically connected to the gate electrode 14b and the gate electrode 14d via the connection wiring 29a, the gate wiring 28, and the connection wiring 29b to form a short circuit.

[0130] On the substrate 10, an insulating film 35a is provided in a manner covering the source electrode 12a, the source electrode 12b, the gate electrodes 14a to 14d, the drain electrode 16a, the drain electrode 16b, and the connection wiring 29a and the connection wiring 29b. The insulating film 35a has an opening 25 that exposes the upper surface of the source electrode 12a, the source electrode 12b, the drain electrode 16a, the drain electrode 16b, and the connection wiring 29a and the connection wiring 29b. The source wiring 22a and the source wiring 22c provided on the source electrode 12a are in electrical contact with the source electrode 12a via the opening 25. The source wiring 22b, the drain wiring 26a and the drain wiring 26b provided on the source electrode 12b, the drain electrode 16a and the drain electrode 16b are in electrical contact with the source electrode 12b, the drain electrode 16a and the drain electrode 16b, respectively, via the opening 25. The gate wiring 28 is in electrical contact with the connection wiring 29a and the connection wiring 29b via the opening 25.

[0131] An insulating film 35b is provided on the source wiring 22a to the source wiring 22c, the drain wiring 26a, the drain wiring 26b, and the gate wiring 28. The insulating film 35b is provided above the source electrode 12a so as to surround the upper surface, the lower surface, and the side surface of the gate wiring 28. The insulating film 35a, the space 31, and the insulating film 35b are provided between the gate wiring 28 above the source electrode 12a and the source electrode 12a. The space 31 is, for example, a void (gas such as air).

[0132] The via hole 30 passes through the substrate 10 and is connected to the source electrode 12a and the source electrode 12b. A metal layer 32 is provided on the lower surface of the substrate 10. A metal layer 32a is provided on the inner surface of the via hole 30. Thus, the metal layer 32 is electrically connected to the source electrode 12a and the source electrode 12b through the via hole 30 to form a short circuit.

[0133] The source potential (for example, a reference potential such as a ground potential) is supplied from the metal layer 32 to the source electrode 12a and the source electrode 12b via the metal layer 32a of the via 30. The gate potential (for example, a high-frequency signal and a gate bias voltage) is supplied from the gate bus 34 to the gate electrode 14a and the gate electrode 14c via the connection wiring 29a. In addition, the gate potential is supplied from the gate bus 34 to the gate electrode 14b and the gate electrode 14d via the connection wiring 29a, the gate wiring 28, and the connection wiring 29b. The drain bias voltage is supplied from the drain bus 36 to the drain electrode 16a and the drain electrode 16b. The high-frequency signal amplified in each unit FET 60a to the unit FET 60d is output from the drain electrode 16a or the drain electrode 16b to the drain bus 36.

[0134] In the unit FET 60a and the unit FET 60c, a high-frequency signal is input from the + end in the Y direction of the gate electrode 14a and the gate electrode 14c. In the unit FET 60b and the unit FET 60d, a high-frequency signal is input from the + end in the Y direction of the gate electrode 14b and the gate electrode 14d. If a high-frequency signal is input to the gate electrode 14a and the gate electrode 14c from both ends of the + end and the - end in the Y direction of the gate electrode 14a and the gate electrode 14c, the high-frequency characteristics of the unit FET 60a and the unit FET 60c will deteriorate due to a phase difference or the like. In the first embodiment, the - end in the Y direction of the gate electrode 14a and the gate electrode 14c and the + end in the Y direction of the gate electrode 14b and the gate electrode 14d are not connected, so that the degradation of the high-frequency characteristics in the unit FET 60a and the unit FET 60c can be suppressed.

[0135] In the case where the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and / or an InGaN layer. In the case where the unit FET 60a to the unit FET 60d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the channel layer 10c is a GaN layer, and the barrier layer 10d is an AlGaN layer. In the case where the semiconductor device 100 is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and / or an InGaAs layer. The semiconductor device 100 may also be a silicon semiconductor device such as an LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0136] The source electrode 12a, the source electrode 12b, the drain electrode 16a, and the drain electrode 16b are metal films, such as titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d, the connection wiring 29a, the connection wiring 29b, and the gate metal layer 34a are metal films, such as nickel films and gold films from the substrate 10 side. The source wiring 22a to 22c, the drain wiring 26a, the drain wiring 26b, and the pad metal layer 34b are, for example, a gold layer, a copper layer, or an aluminum layer. The gate wiring 28 and the metal layer 32 are, for example, a gold layer, a copper layer, or an aluminum layer. The insulating film 35a and the insulating film 35b are, for example, inorganic insulating films such as silicon nitride films.

[0137] The length of the source electrode 12a and the source electrode 12b in the X direction is, for example, 10 μm to 100 μm. The length of the drain electrode 16a and the drain electrode 16b in the X direction is, for example, 1 μm to 50 μm. The length of the source wiring 22a and the source wiring 22c in the X direction is, for example, 1 μm to 50 μm. The length of the source wiring 22b in the X direction is, for example, 5 μm to 100 μm. The length of the gate wiring 28 in the X direction is, for example, 1 μm to 50 μm. The distance between the source electrode 12 and the drain electrode 16 in the X direction is, for example, 1 μm to 20 μm. The thickness of the source wiring 22a to the source wiring 22c, the drain wiring 26a, and the drain wiring 26b is, for example, 1 μm to 10 μm. The thickness of the gate wiring 28 is, for example, 0.5 μm to 5 μm.

[0138] [Manufacturing method of Example 1]

[0139] 7A to 14BIt is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. 7A to 14A Equivalent to Figure 1 A part of the A-A section, 7B to 14B Equivalent to Figure 1 Part of the E-E section.

[0140] like Fig. 7A and Figure 7B As shown, source electrodes 12a to 12c, gate electrodes 14a to 14d, drain electrodes 16a, 16b, connection wiring 29a, and connection wiring 29b are formed on substrate 10. An insulating film 35a is formed on substrate 10 in a manner covering source electrodes 12a to 12c, gate electrodes 14a to 14d, drain electrodes 16a, 16b, connection wiring 29a, and connection wiring 29b. An opening 25 is formed in insulating film 35a. A mask layer 50 is formed on insulating film 35a. Mask layer 50 has an opening 51 that exposes opening 25. Mask layer 50 is, for example, a photoresist.

[0141] like Fig. 8A and Figure 8B As shown, the seed layer 40 is formed in a manner covering the opening 51 and the mask layer 50. The seed layer 40 is formed on the entire surface of the substrate 10 using, for example, a sputtering method. The seed layer 40 includes, for example, a bonding layer and a low-resistance layer on the bonding layer. The low-resistance layer is, for example, a metal layer formed of the same material as the plating layer 41 and the plating layer 42 described later.

[0142] like Fig.9A and Fig. 9B As shown, a mask layer 52 is formed on the seed layer 40. The mask layer 52 has an opening 53 for exposing the seed layer 40 on the mask layer 50 on the source electrode 12a. The opening 53 is provided to connect the opening 25 on the connection wiring 29a and the connection wiring 29b. The mask layer 52 is, for example, a photoresist.

[0143] like Fig. 10A and Fig. 10B As shown, the plated layer 41 is formed in the opening 53. The plated layer 41 is formed by, for example, an electroplating method in which a current is supplied through the seed layer 40.

[0144] like Fig.11A and Fig. 11B As shown, the mask layer 52 is peeled off. A mask layer 54 is formed on the seed layer 40 and the plating layer 41. The mask layer 54 has an opening 55 for exposing the seed layer 40 on the opening 25. The mask layer 54 is, for example, a photoresist.

[0145] like Fig. 12A and Fig. 12BAs shown, the plated layer 42 is formed in the opening 55. The plated layer 42 is formed by, for example, an electroplating method in which a current is supplied through the seed layer 40.

[0146] Alternatively, the plating layer 42 may be formed before the plating layer 41. When the plating layer 42 is formed before the plating layer 41, the mask layer 50 is provided so as to cover the plating layer 42. When the plating layer 42 is thicker than the plating layer 41, it is difficult to provide the mask layer 50 so as to cover the thick plating layer 42. Therefore, when the plating layer 41 is thinner than the plating layer 42, the plating layer 41 may be formed before the plating layer 42.

[0147] like Fig.13A and Fig. 13B As shown, the mask layer 54 is peeled off. The seed layer 40 is removed using the plating layer 41 and the plating layer 42 as a mask. Thus, the gate wiring 28 is formed by the seed layer 40 and the plating layer 41. The source wiring 22a to the source wiring 22c, the drain wiring 26a and the drain wiring 26b are formed by the seed layer 40 and the plating layer 42. Hereinafter, the illustration of the seed layer 40 is omitted.

[0148] like Fig.14A and Fig. 14B As shown, the mask layer 50 is peeled off. The insulating film 35b is formed to cover the source wiring 22a to the source wiring 22c, the drain wiring 26a, the drain wiring 26b, and the gate wiring 28. Thus, a space 31 is formed between the gate wiring 28 and the source electrode 12a. Through the above process, the semiconductor device of Example 1 is manufactured.

[0149] (Comparative Example 1)

[0150] Fig.15 is a top view of the semiconductor device in Comparative Example 1. Fig.15 As shown, in the semiconductor device 120 of Comparative Example 1, the unit FET 60a and the unit FET 60b are arranged in the Y direction. The gate electrode 14a of the unit FET 60a is directly connected to the gate bus 34. The gate electrode 14b of the unit FET 60b is connected to the gate bus 34 via the connection wiring 29b and the gate wiring 28. The gate wiring 28 is provided in such a manner that the source electrode 12a is arranged between the gate wiring 28 and the drain electrode 16a, and the connection wiring 29b is provided between the unit FET 60a and the unit FET 60b.

[0151] If the width of the gate electrode of the unit FET in the Y direction increases, the gate resistance of the unit FET will increase. If the gate resistance increases, the frequency at which the maximum stable gain is switched to the maximum available power gain becomes lower, and the gain at high frequency decreases. In Comparative Example 1, the gate width of the unit FET 60a and the unit FET 60b in the Y direction is shortened. The gate electrode 14b is electrically connected to the gate bus 34 via the connecting wiring 29b and the gate wiring 28. Thus, the gate resistance can be suppressed. Therefore, the gain at high frequency can be improved. In addition, if the gate-drain capacitance increases, the reverse power gain S12 will increase. In Comparative Example 1, the source wiring 22a is provided between the gate wiring 28 and the drain wiring 26a. Thus, the source wiring 22a shields the electric line 64 between the gate wiring 28 and the drain wiring 26a. Thus, since the gate-drain capacitance is suppressed, the reverse power gain S12 is reduced, thereby improving the gain characteristics of the FET.

[0152] However, in order to provide the gate wiring 28, the chip size becomes larger.

[0153] (Comparative Example 2)

[0154] Fig.16 is a cross-sectional view of a semiconductor device in Comparative Example 2. Fig.16 As shown, in the semiconductor device 122 of Comparative Example 2, a source wiring 22a, a drain wiring 26a, and a drain wiring 26b are provided on the source electrode 12a, the drain electrode 16a, and the drain electrode 16b, respectively. An insulating film 38a is provided in a manner covering the source wiring 22a, the drain wiring 26a, and the drain wiring 26b. A protective metal layer 23a, a protective metal layer 23b, and a gate wiring 28 are provided on the insulating film 38a. The gate wiring 28 is arranged between the protective metal layer 23a and the protective metal layer 23b. The protective metal layer 23a, the protective metal layer 23b, and the gate wiring 28 are arranged to overlap with the source wiring 22a when viewed from the Z direction. An insulating film 38b is provided in a manner covering the protective metal layer 23a, the protective metal layer 23b, and the gate wiring 28. The other configurations are the same as those of Example 1.

[0155] In Comparative Example 2, the gate wiring 28 is provided in a manner overlapping with the source wiring 22a, so that the chip size can be reduced compared with Comparative Example 1. The protective metal layer 23a and the protective metal layer 23b supplied with the source potential are provided in a manner such that the gate wiring 28 is arranged between the protective metal layer 23a and the protective metal layer 23b supplied with the source potential. Thus, the protective metal layer 23a and the protective metal layer 23b shield the electric force line 64 between the gate wiring 28 and the drain wiring 26a and the drain wiring 26b. Therefore, the gate-drain capacitance is suppressed, thereby reducing the reverse power gain S12 and improving the gain characteristics of the FET.

[0156] However, in order to provide the gate wiring 28, the protective metal layer 23a, and the protective metal layer 23b on the insulating film 38a, the insulating film 38a is formed by an organic insulating film, and the insulating film 38a is flattened. In this way, the manufacturing process increases in order to perform the multi-layer wiring process. In addition, the insulating film 38a and the insulating film 38b, which are organic insulating films, become thicker, so the stress increases and the warping of the wafer increases. As a result, the degree of freedom of selecting the process in the manufacturing process is reduced.

[0157] (Description of Embodiment 1)

[0158] According to the first embodiment, the source wiring 22a is arranged between the gate wiring 28 and the drain electrode 16a in the X direction, and the source wiring 22c is arranged between the gate wiring 28 and the drain electrode 16b in the X direction. The gate wiring 28 electrically connects the gate bus 34 to the gate electrode 14b, and the gate bus 34 to the gate electrode 14d. In this way, the electric force lines 64 (see FIG. 1 ) between the gate wiring 28 and the drain electrode 16a and the drain electrode 16b are controlled by the source wiring 22a and the source wiring 22c. Figure 2 ) for shielding. Thus, even if multilayer wiring is not used as in Comparative Example 2, gate-drain capacitance can be suppressed, thereby suppressing degradation of characteristics. In this way, multilayer wiring is not used, so the manufacturing process can be simplified. In addition, the warping of the wafer can be suppressed. In addition, the gate wiring 28 is provided above the source electrode 12a. Thus, compared with Comparative Example 1, miniaturization of the semiconductor device can be achieved.

[0159] The gate electrode 14c, the gate electrode 14d, the drain electrode 16b, and the source wiring 22c may not be provided. By not providing the gate electrode 14c, the gate electrode 14d, the drain electrode 16b, and the source wiring 22c, the semiconductor device 100 can be miniaturized.

[0160] The - end (first end) of the gate wiring 28 in the Y direction is connected to the central part of the connection wiring 29b in the X direction. Thus, the gate potential can be supplied to the gate electrode 14b and the gate electrode 14d via the gate wiring 28 and the connection wiring 29b. In Example 1, the + end (second end) of the gate wiring 28 in the Y direction is connected to the central part of the connection wiring 29a in the X direction. Alternatively, the gate electrode 14a and the gate electrode 14b are directly connected to the gate bus 34, and the + end (second end) of the gate wiring 28 in the Y direction is directly connected to the gate bus 34.

[0161] The source wiring 22a and the source wiring 22c are wirings for reducing the current density flowing in the Y direction of the source electrode 12a. Therefore, the source wiring 22a and the source wiring 22c are in contact with the source electrode 12a via one opening 25 respectively. If the area where the source wiring 22a contacts the source electrode 12a is small, the effect of suppressing the current density flowing in the Y direction of the source electrode 12a becomes small. From this point of view, if Figure 6 In this way, when viewed from the Z direction, the maximum width in the Y direction of the region where the source wiring 22a and the source wiring 22c overlap with the source electrode 12a is set to D1, and the maximum width in the Y direction of the region where the source wiring 22a and the source wiring 22c contact with the source electrode 12a is set to D2. In this case, the maximum width D2 is 1 / 2 times or more, 3 / 4 times or more, or 4 / 5 times or more of the maximum width D1. D2 is 1 times or less of D1. In addition, the area of ​​the region where the source wiring 22a and the source wiring 22c contact with the source electrode 12a is 1 / 4 times or more, 1 / 2 times or more, or 3 / 4 times or more of the area of ​​the region where the source wiring 22a and the source wiring 22c overlap with the source electrode 12a when viewed from the Z direction.

[0162] like Figure 2 and Figure 4 Thus, with reference to the upper surface of the substrate 10, the height of the upper surface of the source wiring 22a and the source wiring 22c is set to H1, the height of the upper surface of the source wiring 22b is set to H2, and the height of the upper surface of the drain wiring 26a and the drain wiring 26b is set to H3. With reference to the upper surface of the substrate 10, the height of the upper surface of the gate wiring 28 is set to H4. The thickness of the source wiring 22a and the source wiring 22c is set to T1, the thickness of the source wiring 22b is set to T2, and the thickness of the drain wiring 26a and the drain wiring 26b is set to T3.

[0163] At this time, the height H4 is smaller than the height H1. Thus, the electric lines of force between the gate wiring 28 and the drain electrode 16a and the drain wiring 26a are shielded by the source wiring 22a, and the electric lines of force between the gate wiring 28 and the drain electrode 16b and the drain wiring 26b are shielded by the source wiring 22c. Therefore, the gate-drain capacitance can be further suppressed. The height H4 is, for example, less than 0.9 times or less than 0.8 times the height H1. From the perspective of reducing the resistance of the gate wiring 28, for example, the height H4 is more than 0.2 times the height H1. It should be noted that even if the height H4 is higher than the height H1, it has the effect of suppressing the gate-drain capacitance.

[0164] The source wiring 22b is a wiring for reducing the current density flowing in the Y direction of the source electrode 12b. The drain wiring 26a and the drain wiring 26b are wirings for reducing the current density flowing in the Y direction of the drain electrode 16a and the drain electrode 16b, respectively. Fig. 12A and Fig.13A In this way, source wiring 22a to source wiring 22c and drain wiring 26a and drain wiring 26b are formed at the same time. As a result, the manufacturing process can be reduced compared to the case where the protective metal layer 23a and the protective metal layer 23b are formed separately from the source wiring and the drain wiring as in Comparative Example 2. If manufacturing is performed in this way, the thickness T2 and the thickness T3 are equal to the thickness T1. The height H2 is equal to the height H1, and the height H3 is equal to the height H1. It should be noted that the thickness T2 and the thickness T3 are equal to the thickness T1 (approximately equal) means that the allowable manufacturing error, for example, |T2-T1| / T1 and |T3-T1| / T1 can be less than 0.1 times.

[0165] exist Figure 5 In the embodiment, the insulating film 35a (inorganic insulating film) is provided on the source electrode 12a. The gate wiring 28 does not need to be in contact with the source electrode 12a, and may be in contact with the insulating film 35a on the source electrode 12a, for example. However, if the gate wiring 28 is in contact with the insulating film 35a, the gate-source capacitance between the gate wiring 28 and the source electrode 12a will increase. Therefore, a space 31 as a gap is provided between the insulating film 35a and the gate wiring 28. Thus, the gate-source capacitance can be reduced, and the degradation of the characteristics can be suppressed.

[0166] (Variation 1 of Example 1)

[0167] Fig.17 and Fig.18 This is a cross-sectional view of a semiconductor device in Modification 1 of Embodiment 1. Fig.17 is equivalent to Figure 1 The A-A section diagram, Fig.18 is equivalent to Figure 1 Diagram of the D-D section.

[0168] like Fig.17 and Fig.18 As shown, in the semiconductor device 101 of the first modification of the first embodiment, an organic insulating film 38 is provided in a manner covering the insulating film 35b. The organic insulating film 38 is also provided between the gate wiring 28 and the insulating film 35a. The organic insulating film 38 is, for example, a polyimide resin or BCB (Benzocyclobutene). The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0169] The organic insulating film 38 is provided between the insulating film 35a and the gate wiring 28. In this case, the distance between the gate wiring 28 and the source electrode 12a can also be increased, thereby reducing the gate-source capacitance. The organic insulating film 38 can also be a molding resin (e.g., epoxy resin) for sealing. In order to reduce the gate-source capacitance, the relative dielectric constant of the organic insulating film 38 can also be lower than the relative dielectric constants of the insulating film 35a and the insulating film 35b.

[0170] (Variation 2 of Example 1)

[0171] Fig.19 It is a top view of a semiconductor device in a second variation of the first embodiment. Fig. 20 and Fig.21 They are Fig.19 The A-A section view and the B-B section view in the figure. Figures 19 to 21 As shown, in the semiconductor device 102 of the second variation of the first embodiment, the source wiring 22a and the source wiring 22c extend in the - direction of the Y direction and are connected to the source wiring 22b. An insulating film 35a is provided between the source wiring 22a and the source wiring 22c and the connection wiring 29b, and the source wiring 22a and the source wiring 22c are not in contact with the connection wiring 29b. The source wiring 22a and the source wiring 22c are provided between the gate wiring 28 and the drain wiring 26a and between the gate wiring 28 and the drain wiring 26b on the connection wiring 29b, respectively. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0172] In the semiconductor device 100 of the first embodiment, the source wiring 22a and the source wiring 22b are not provided between the gate wiring 28 and the drain wiring 26a and the drain wiring 26b, respectively, between the FET group 62a and the FET group 62b. Therefore, the gate-drain capacitance increases. In the semiconductor device 102 of the second variation of the first embodiment, the source wiring 22a and the source wiring 22c cross the connection wiring 29b without contact and are connected to the source wiring 22b. As a result, between the FET group 62a and the FET group 62b, the source wiring 22a and the source wiring 22c respectively connect the electric force lines 64 (refer to Fig. 20 ) for shielding. Therefore, the gate-drain capacitance can be further suppressed.

[0173] Alternatively, the source wiring 22a and the source wiring 22c may be provided on the insulating film 35a with a space therebetween, like the gate wiring 28 on the source electrode 12a. If a space is provided between the source wiring 22a and the source wiring 22c and the insulating film 35a, the effect of shielding the electric lines of force between the gate wiring 28 and the drain wiring 26a and the drain wiring 26b will be reduced. Therefore, the source wiring 22a and the source wiring 22c may also be in contact with the insulating film 35a.

[0174] (Variation 3 of Example 1)

[0175] Fig. 22 It is a top view of a semiconductor device in a third variation of the first embodiment. Fig.23 yes Fig. 22 The A-A section view in the figure. Fig. 22 and Fig.23 As shown, in the semiconductor device 103 of the third modification of the first embodiment, the unit FET 60e (fifth unit FET) includes a source electrode 12c (third source electrode), a gate electrode 14e (fifth gate electrode) and a drain electrode 16a. A source wiring 22d (fourth source wiring) is provided on the source electrode 12c, and the source wiring 22d is electrically in contact with the source electrode 12c. The connection wiring 17 (second connection wiring) electrically connects the source wiring 22a and the source wiring 22d separated by the drain wiring 26a, and is provided between the gate bus 34 and the drain wiring 26a in the Y direction. The connection wiring 17 is provided on the insulating film 35a in a manner of contacting with the insulating film 35a. The other configurations are the same as those of the second modification of the first embodiment, and the description thereof is omitted.

[0176] In the semiconductor devices 100 and 102 of the first embodiment and the second variation thereof, a gate-drain capacitance is generated between the drain wiring 26a and the gate bus 34. In the semiconductor device 103 of the third variation of the first embodiment, a connection wiring 17 is provided between the gate bus 34 and the drain wiring 26a, and the connection wiring 17 is electrically connected to the source wiring 22a and the source wiring 22d to form a short circuit. As a result, the connection wiring 17 has a negative impact on the electric field 64 (see FIG. 1 ) between the gate bus 34 and the drain wiring 26a. Fig.23 ) are shielded. Therefore, the gate-drain capacitance can be suppressed. In addition, the potential of the source wiring 22a and the source wiring 22d can be stabilized.

[0177] In the second and third variants of the first embodiment, even if the source electrode 12a is not provided with the via hole 30, the source potential can be supplied from the source electrode 12b through the source wiring 22a and the source wiring 22c. In addition, instead of providing the via hole 30 in the source electrode 12b, a source pad can be provided outside the active region 11b.

[0178] (Variation 4 of Example 1)

[0179] Fig.24 and Fig.25 This is a cross-sectional view of a semiconductor device in Modification 4 of Embodiment 1. Fig.24 and Fig.25 This corresponds to the cross section of the gate wiring 28 in the X direction. Fig.24 and Fig.25As shown, in the semiconductor device 104 and the semiconductor device 105 of the fourth modification of the first embodiment, the gate wiring 28 is in contact with the insulating film 35a at the center portion 43a of the source electrode 12a in the Y direction. Fig.24 There is a portion 43a in Fig.25 In the embodiment, two portions 43a are provided. A portion 43b separated by the portion 43a in the Y direction is provided with a space 31 between the gate wiring 28 and the insulating film 35a. The other configurations are the same as those of the first embodiment and its modified examples 1 to 3, and the description thereof is omitted.

[0180] When the portion of the gate wiring 28 provided on the insulating film 35a with the space 31 therebetween is long, the shape of the gate wiring 28 becomes unstable. In such a case, in a portion 43a (first portion) in the Y direction of the region where the gate wiring 28 overlaps with the source electrode 12a when viewed from the Z direction, the gate wiring 28 contacts the insulating film 35a without interposing the space 31 (for example, an organic insulating film and a gap). In a portion 43b (second portion) separated by the portion 43a in the Y direction of the region where the gate wiring 28 overlaps with the source electrode 12a, the space 31 (organic insulating film or a gap) is arranged between the gate wiring 28 and the insulating film 35a. Thus, the shape of the gate wiring 28 can be stabilized. The total width of the portion 43a in the Y direction is, for example, 1 / 20 times or more and 1 / 2 times or less of the width of the source electrode 12a in the Y direction.

[0181] (Variation 5 of Example 1)

[0182] Fig.26 It is a cross-sectional view of a semiconductor device in a fifth variation of the first embodiment. Fig.26 Equivalent to Figure 1 A-A section diagram of. Fig.26 As shown, in the semiconductor device 106 of the fifth variation of the first embodiment, the drain wiring 26a and the drain wiring 26b include a plating layer 41 and a plating layer 42 provided on the plating layer 41. The plating layer 41 and the plating layer 42 of the gate wiring 28 (see Fig. 10A and Fig. 10B ) is formed simultaneously, and the plating layer 42 and the plating layer 42 of the source wiring 22a to the source wiring 22c (refer to Fig. 12A and Fig. 12B ) are formed simultaneously. Thus, the thickness of the drain wiring 26a and the drain wiring 26b is substantially the same as the total thickness of the source wiring 22a and the gate wiring 28.

[0183] In addition to the source wiring 22a to the source wiring 22c, the current can also be supplied to the source electrode 12a and the source electrode 12b through the metal layer 32 and the metal layer 32a through the via 30. On the other hand, the current only from the drain wiring 26a and the drain wiring 26b is supplied to the drain electrode 16a and the drain electrode 16b. Therefore, by making the drain wiring 26a and the drain wiring 26b thicker than the source wiring 22a to the source wiring 22c, a larger drain current can flow, and high-power operation can be performed. In addition, the drain resistance can be reduced. In this way, the height H3 of the upper surface of the drain wiring 26a and the drain wiring 26b based on the upper surface of the substrate 10 is greater than or equal to the height H1 of the upper surface of the source wiring 22a to the source wiring 22c based on the upper surface of the substrate 10. From the viewpoint of reducing gate-drain capacitance, all straight lines from the gate wiring 28 to the drain wiring 26a and the drain wiring 26b may be hidden in the source wiring 22a and the source wiring 22c. The other configurations are the same as those in the first embodiment, and the description thereof is omitted.

[0184] (Variation 6 of Example 1)

[0185] Fig. 27 It is a top view of a semiconductor device according to a sixth variation of the first embodiment. Fig.28 yes Fig. 27 A-A section view. Fig. 27 and Fig.28 As shown, in the semiconductor device 113 of the sixth variation of the first embodiment, the drain electrode 16a and the drain electrode 16b are not provided between the active region 11a and the active region 11b. The drain electrode 16a1 and the drain electrode 16b1 are provided in the active region 11a, and the drain electrode 16a2 and the drain electrode 16b2 are provided in the active region 11b. The drain electrode 16a1 and the drain electrode 16a2 are electrically connected through the drain wiring 26a, and the drain electrode 16b1 and the drain electrode 16b2 are electrically connected through the drain wiring 26b. Between the active region 11a and the active region 11b, the drain wiring 26a and the drain wiring 26b are provided on the insulating film 35a. The other structures are the same as those of the first embodiment, and the description is omitted. In the embodiments other than the first embodiment and the variation thereof, the drain electrode may not be provided between the active region 11a and the active region 11b.

[0186] (Example 2)

[0187] Fig.29 This is a top view of the semiconductor device in Example 2. Fig.30 yes Fig.29 A-A section view. Fig.29 In the figure, a part of the opening 25 is omitted. Fig.29 and Fig.30As shown, in the semiconductor device 107 of the second embodiment, a protective metal layer 44 is provided so as to cover the top of the gate wiring 28. The first end of the protective metal layer 44 is connected to the upper surface of the source wiring 22a, and the second end of the protective metal layer 44 is connected to the upper surface of the source wiring 22c. The protective metal layer 44 is, for example, a gold layer, a copper layer, or an aluminum layer. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0188] (Manufacturing method of Example 2)

[0189] Figure 31 to Figure 35 FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2. Figure 31 to Figure 35 In the figure, the via hole 30, the metal layer 32 and the metal layer 32a are omitted.

[0190] like Fig.31 As shown, Fig.14A Similarly, source wiring 22a and source wiring 22c are provided on source electrode 12a so as to be in contact with source electrode 12a. Gate wiring 28 is provided between source wiring 22a and source wiring 22c on source electrode 12a. Insulating film 35b is provided so as to surround source wiring 22a, source wiring 22c and gate wiring 28.

[0191] like Fig.32 As shown, a mask layer 56 is formed on the substrate 10. The mask layer 56 has an opening 57 that exposes the insulating film 35b on the upper surface of the source wiring 22a and the source wiring 22c. The mask layer 56 is, for example, a photoresist.

[0192] like Fig.33 As shown, an opening 25a is formed in the insulating film 35b using a mask layer 56 as a mask. A seed layer 45 is formed on the opening 25a and the mask layer 56. The seed layer 45 is formed on the entire surface of the substrate 10 using, for example, a sputtering method. The seed layer 45 includes, for example, a bonding layer and a low-resistance layer on the bonding layer. The low-resistance layer is, for example, a metal layer formed of the same material as the plating layer 46 described later.

[0193] like Fig.34 As shown, a mask layer 58 is formed on the seed layer 45. The mask layer 58 has an opening 59 between the source wiring 22a and the source wiring 22c. The mask layer 58 is, for example, a photoresist. The plating layer 46 is formed in the opening 59 by electroplating.

[0194] like Fig.35 As shown, the mask layer 58 is peeled off. The seed layer 45 is removed using the plating layer 46 as a mask. The mask layer 56 is removed. Thus, the protective metal layer 44 is formed by the seed layer 45 and the plating layer 46.

[0195] In the semiconductor device 100 of the first embodiment, as Figure 2In this way, the upper part of the gate wiring 28 between the source wiring 22a and the source wiring 22c is open. Therefore, the electric lines extend from the gate wiring 28 to the drain wiring 26a and the drain wiring 26b, bypassing the source wiring 22a and the source wiring 22c. As a result, a gate-drain capacitance is generated. In the semiconductor device 107 of the second embodiment, the protective metal layer 44 is provided above the gate wiring 28 in a non-contact manner with the gate wiring 28, and the source wiring 22a and the source wiring 22c are electrically connected. As a result, the protective metal layer 44 blocks the electric lines 64 (see FIG. 1 ) between the gate wiring 28 and the drain wiring 26a and the drain wiring 26b. Fig.30 ) for shielding. Therefore, the gate-drain capacitance can be further suppressed.

[0196] (Variation 1 of Example 2)

[0197] Fig.36 It is a top view of the semiconductor device in the first variation of the second embodiment. Fig.37 and Fig.38 They are Fig.36 The A-A section view and the B-B section view. Figure 36 to Figure 38 As shown, in the semiconductor device 108 of the first variation of the second embodiment, a plurality of protective metal layers 44 are provided above a gate wiring 28. Each of the plurality of protective metal layers 44 connects the source wiring 22a to the source wiring 22c. A portion 44a of the protective metal layer 44 is provided between the plurality of protective metal layers 44, and a gap 47 is provided above the gate wiring 28. The other configurations are the same as those of the second embodiment, and the description thereof is omitted.

[0198] In the semiconductor device 107 of the second embodiment, Fig.34 and Fig.35 In the embodiment, when the mask layer 56 under the protective metal layer 44 is stripped, the stripping liquid or the oxygen plasma used for ashing sometimes cannot reach below the central part of the protective metal layer 44 in the Y direction. In this case, the mask layer 56 will remain. In the semiconductor device 108 of the modification 1 of the embodiment 2, a gap 47 is provided between the plurality of protective metal layers 44. Thus, the stripping liquid can reach the mask layer 56 under the protective metal layer 44, thereby suppressing the residue of the mask layer 56. From the viewpoint of shielding the electric line, when viewed from the Z direction, the area where the protective metal layer 44 overlaps in the region between the source wiring 22a and the source wiring 22c can be 1 / 2 times or more of the area between the source wiring 22a and the source wiring 22c, or can be 3 / 4 times or more of the area between the source wiring 22a and the source wiring 22c. The protective metal layer 44 as in the embodiment 2 and its modification can also be provided in the modification of the embodiment 1.

[0199] (Example 3)

[0200] Fig.39 This is a top view of the semiconductor device in Example 3. Fig.40 yes Fig.39 A-A section view. Fig.39 and Fig.40 In the figure, the via hole 30, the metal layer 32 and the metal layer 32a are omitted.

[0201] like Fig.39 and Fig.40 As shown, in the semiconductor device 109 of the third embodiment, the width of the gate electrode 14a to the gate electrode 14d in the X direction at the portion far from the semiconductor layer 10b is greater than the width of the portion close to the semiconductor layer 10b in the X direction. That is, the gate electrode 14a to the gate electrode 14d are T-type or Γ-type gates. A field plate 15 is provided above the substrate 10 via an insulating film 35a between the gate electrode 14a and the drain electrode 16a, between the gate electrode 14b and the drain electrode 16a, between the gate electrode 14c and the drain electrode 16b, and between the gate electrode 14d and the drain electrode 16b. The field plate 15 is also provided on both sides of the connection wiring 29a and the connection wiring 29b in the X direction. As a result, the capacitance between the connection wiring 29a and the connection wiring 29b and the drain wiring 26a and the drain wiring 26b can be suppressed.

[0202] The field plate 15 is connected to the source wiring 22a and the source wiring 22c at the - end in the Y direction of the source wiring 22a and the source wiring 22c. Thus, the field plate 15 is electrically connected to the source electrode 12a, the source electrode 12b, and the source electrode 12c, and a reference potential is supplied. Alternatively, the field plate 15 is connected to the source wiring 22a and the source wiring 22c at the + end in the Y direction of the source wiring 22a and the source wiring 22c, or at both the - end and the + end.

[0203] The electric field concentration in the semiconductor layer 10b between the gate electrode 14a and the drain electrode 16a, between the gate electrode 14b and the drain electrode 16a, between the gate electrode 14c and the drain electrode 16b, and between the gate electrode 14d and the drain electrode 16b can be alleviated by the field plate 15. Thus, the current drift phenomenon can be suppressed. Alternatively, a part of the field plate 15 is provided above the gate electrode 14a to the gate electrode 14d. Thus, the gate-drain capacitance can be suppressed. The other structures are the same as those in Example 1, and the description is omitted.

[0204] (Variation 1 of Example 3)

[0205] Fig.41 FIG. 1 is a top view of a semiconductor device in a variation 1 of the third embodiment. Fig.41As shown, in the semiconductor device 110 of the first modification of the third embodiment, the field plate 15 is provided on the + side of the connection wiring 29a and the connection wiring 29b in the Y direction. As a result, the gate-drain capacitance between the connection wiring 29a and the drain wiring 26a and the drain wiring 26b, and between the connection wiring 29b and the drain wiring 26a and the drain wiring 26b can be suppressed. The other configurations are the same as those of the third embodiment, and the description thereof is omitted.

[0206] (Variation 2 of Example 3)

[0207] Fig.42 FIG. 1 is a top view of a semiconductor device in a second variation of the third embodiment. Fig.42 As shown, in the semiconductor device 114 of the second modification of the third embodiment, the field plate 15 crosses the connection wiring 29a and the connection wiring 29b without contact, and is connected to the source wiring 22a and the source wiring 22c at the + end in the Y direction of the source wiring 22a and the source wiring 22c. The other structures are the same as the first modification of the third embodiment, and the description is omitted. As in the second modification of the third embodiment, the field plate 15 can also be connected to the source wiring 22a and the source wiring 22c at both the + end and the - end in the Y direction of the source wiring 22a and the source wiring 22c. Thus, the reference potential can be stably supplied to the field plate 15 as a whole. The field plate 15 can also be connected to the source wiring 22a and the source wiring 22c at the + end in the Y direction of the source wiring 22a and the source wiring 22c.

[0208] (Variation 3 of Example 3)

[0209] Fig.43 FIG. 1 is a top view of a semiconductor device in a third variation of the third embodiment. Fig.43 As shown, in the semiconductor device 111 of the modification 3 of the embodiment 3, the field plate 15 of the unit FET 60a and the field plate 15 of the unit FET 60b are continuously provided. The field plate 15 of the unit FET 60c and the field plate 15 of the unit FET 60d are continuously provided. As a result, the gate-drain capacitance between the connection wiring 29a and the drain wiring 26a and the drain wiring 26b, and between the connection wiring 29b and the drain wiring 26a and the drain wiring 26b can be suppressed. The other configurations are the same as those of the embodiment 3, and the description thereof is omitted.

[0210] The field plate 15 may be provided in the first embodiment, the second embodiment and their modified examples.

[0211] (Example 4)

[0212] Fig.44 FIG. 4 is a top view of the semiconductor device in Example 4. Fig.44As shown, in the semiconductor device 112 of the fourth embodiment, an active region 11c is provided between the active region 11a and the active region 11b. A FET group 62c is provided in the active region 11c. A connection wiring 29c is provided between the FET group 62a and the FET group 62c. A connection wiring 29b is provided between the FET group 62c and the FET group 62b. The - end in the Y direction of the gate wiring 28 of the FET group 62a and the + end in the Y direction of the gate wiring 28 of the FET group 62c are connected to the connection wiring 29c. The - end in the Y direction of the gate wiring 28 of the FET group 62c is connected to the connection wiring 29b. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0213] It is also possible to set three FET groups 62a to 62c in the Y direction as in Example 4. This can further reduce the gate resistance. It is also possible to set four or more FET groups in the Y direction. It is also possible to set three or more FET groups in Examples 1 to 3 and their variations.

[0214] In the first to fourth embodiments and their modified examples, an example in which four unit FETs are arranged in the X direction is described, but the number of unit FETs in the X direction can be arbitrarily designed.

[0215] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: substrate; a first unit FET provided on the substrate, comprising a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction; a second unit FET provided on the substrate in the first direction relative to the first unit FET, comprising a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction; a first source wiring extending in the first direction and disposed on the first source electrode and electrically contacting the first source electrode; a gate bus bar, arranged in such a way that the first gate electrode is arranged between the gate bus bar and the second gate electrode in the first direction, and the gate bus bar is electrically connected to the first gate electrode; as well as a gate wiring, which is disposed above the first source electrode in a non-contact manner with the first source electrode, and the first source wiring is arranged between the gate wiring and the first drain electrode in the second direction, and the gate wiring extends in the first direction to electrically connect the gate bus bar to the second gate electrode, The maximum width in the first direction of a region where the first source wiring contacts the first source electrode is greater than or equal to 1 / 2 times the maximum width in the first direction of a region where the first source wiring overlaps the first source electrode when viewed in the thickness direction of the substrate.

2. The semiconductor device according to claim 1, wherein A height of an upper surface of the gate wiring from an upper surface of the substrate is smaller than a height of an upper surface of the first source wiring from an upper surface of the substrate.

3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device includes a first drain wiring extending in the first direction and provided on the first drain electrode and electrically contacting the first drain electrode. The thickness of the first source wiring is less than or equal to the thickness of the first drain wiring.

4. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device includes a second source wiring extending in the first direction and provided on the second source electrode and electrically contacting the second source electrode. The thickness of the first source wiring is equal to the thickness of the second source wiring.

5. The semiconductor device according to claim 1 or 2, comprising: an inorganic insulating film, disposed on the first source electrode; and An organic insulating film or a gap is provided between the inorganic insulating film and the gate wiring.

6. The semiconductor device according to claim 5, wherein: At a first portion of a part in the first direction of the region where the gate wiring overlaps with the first source electrode when viewed from the thickness direction of the substrate, the gate wiring is in contact with the inorganic insulating film without the organic insulating film or the gap in between, and at a second portion of the region separated by the first portion in the first direction, the organic insulating film or the gap is arranged between the gate wiring and the inorganic insulating film.

7. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device comprises: a second source wiring extending in the first direction and disposed on the second source electrode and electrically contacting the second source electrode; as well as a first connecting wiring extending in the second direction, arranged between the first source electrode and the second source electrode in the first direction, and electrically connecting the gate wiring and the second gate electrode; The first source wiring crosses the first connection wiring in a non-contact manner and is connected to the second source wiring.

8. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device comprises: a third unit FET provided on the substrate, comprising the first source electrode, a third drain electrode, and a third gate electrode, wherein the third drain electrode extends in the first direction and the first source electrode is arranged between the third drain electrode and the first drain electrode in the second direction, and the third gate electrode extends in the first direction and is arranged between the first source electrode and the third drain electrode in the second direction; a fourth unit FET provided on the substrate in the first direction relative to the third unit FET, comprising the second source electrode, a fourth drain electrode, and a fourth gate electrode, wherein the fourth drain electrode extends in the first direction and the second source electrode is arranged between the fourth drain electrode and the second drain electrode in the second direction, and the fourth gate electrode extends in the first direction and is provided between the second source electrode and the fourth drain electrode in the second direction; and a third source wiring extending in the first direction and provided on the first source electrode, wherein the gate wiring is arranged between the third source wiring and the first source wiring in the second direction, and the third source wiring is in electrical contact with the first source electrode, The maximum width in the first direction of a region where the third source wiring contacts the first source electrode is greater than or equal to 1 / 2 times the maximum width in the first direction of a region where the third source wiring overlaps the first source electrode when viewed in the thickness direction of the substrate.

9. The semiconductor device according to claim 8, wherein: The semiconductor device includes a first connection wiring, the first connection wiring being arranged between the first source electrode and the second source electrode in the first direction and electrically connecting the second gate electrode and the fourth gate electrode. An end portion of the gate wiring is connected to a center portion of the first connection wiring in the second direction.

10. The semiconductor device according to claim 8, comprising: A protective metal layer is provided above the gate wiring in a non-contact manner with the gate wiring, and connects the first source wiring and the third source wiring.

11. The semiconductor device according to claim 1 or 2, comprising: The fifth unit FET is provided on the substrate and includes a third source electrode, the first drain electrode and a fifth gate electrode, wherein: The third source electrode extends in the first direction and the first drain electrode is arranged between the third source electrode and the first source electrode in the second direction, and the fifth gate electrode extends in the first direction and is arranged between the third source electrode and the first drain electrode in the second direction; a fourth source wiring extending in the first direction and disposed on the third source electrode and electrically contacting the third source electrode; as well as The second connection wiring is provided between the first drain electrode and the gate bus bar in the first direction, and electrically connects the first source wiring and the fourth source wiring.

12. A method for manufacturing a semiconductor device, comprising the following steps: A first unit FET and a second unit FET are formed on a substrate, wherein: The first unit FET includes a first source electrode extending in a first direction, a first drain electrode extending in the first direction, and a first gate electrode extending in the first direction and provided between the first source electrode and the first drain electrode in a second direction intersecting the first direction, and the second unit FET is located in the first direction relative to the first unit FET, includes a second source electrode extending in the first direction, a second drain electrode extending in the first direction, and a second gate electrode extending in the first direction and provided between the second source electrode and the second drain electrode in the second direction; Simultaneously forming a first source wiring, a second source wiring, and a first drain wiring, wherein the first source wiring extends in the first direction and is disposed on the first source electrode and is in electrical contact with the first source electrode, the second source wiring extends in the first direction and is disposed on the second source electrode and is in electrical contact with the second source electrode, and the first drain wiring extends in the first direction and is disposed on the first drain electrode and is in electrical contact with the first drain electrode; and A gate wiring is formed, wherein the gate wiring is arranged above the first source electrode in a non-contact manner with the first source electrode, and the first source wiring is configured between the gate wiring and the first drain electrode in the second direction, and the gate wiring extends in the first direction to electrically connect the gate bus and the second gate electrode.

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