Semiconductor device

Abstract

The invention discloses a semiconductor device, relates to the technical field of semiconductors, and aims to reduce stray capacitance between gate stack structures and improve alternating current characteristics of the semiconductor device. The semiconductor device comprises a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulating layer, a first dielectric isolation layer and a second dielectric isolation layer. The insulating layer is disposed between the source / drain region included in the first gate-all-around transistor and the source / drain region included in the second gate-all-around transistor. And the first dielectric isolation layer and the second dielectric isolation layer are alternately stacked between a channel region included in the first gate-all-around transistor and a channel region included in the second gate-all-around transistor. A gate stack structure included in the first gate-all-around transistor and / or a gate stack structure included in the second gate-all-around transistor are located on the periphery of the first dielectric isolation layers and the second dielectric isolation layers which are alternately stacked, and film layers, located on the bottom layer and the top layer, in the first dielectric isolation layers and the second dielectric isolation layers which are alternately stacked are the first dielectric isolation layers.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminating the lateral spacing between the N-type transistors and the P-type transistors, which allows the effective channel width to be further increased, thereby facilitating the improvement of the operating performance and integration of the semiconductor device.

[0003] However, in the existing three-dimensional stacked complementary transistor, the parasitic capacitance between the gate stack structures included in the upper ring gate transistor and the lower ring gate transistor is relatively large, resulting in poor AC characteristics of the three-dimensional stacked complementary transistor. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device for reducing the parasitic capacitance between the gate stack structures and improving the AC characteristics of the semiconductor device by positioning the gate stack structure included in the first ring-gate transistor and / or the gate stack structure included in the second ring-gate transistor at the periphery of the alternately stacked first dielectric isolation layer and the second dielectric isolation layer.

[0005] In order to achieve the above-mentioned object, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a first ring-gate transistor, a second ring-gate transistor, an insulating layer, and a first dielectric isolation layer and a second dielectric isolation layer. The first ring-gate transistor is arranged on the semiconductor substrate. The second ring-gate transistor is arranged above the first ring-gate transistor. The conductivity type of the second ring-gate transistor is opposite to that of the first ring-gate transistor. The insulating layer is arranged between the source / drain region included in the first ring-gate transistor and the source / drain region included in the second ring-gate transistor. Along the thickness direction of the semiconductor substrate, the first dielectric isolation layer and the second dielectric isolation layer are alternately stacked and arranged between the channel region included in the first ring-gate transistor and the channel region included in the second ring-gate transistor. The gate stack structure included in the first ring-gate transistor and / or the gate stack structure included in the second ring-gate transistor are located at the periphery of the alternately stacked first dielectric isolation layer and the second dielectric isolation layer, and the film layers located at the bottom and top layers of the alternately stacked first dielectric isolation layer and the second dielectric isolation layer are both first dielectric isolation layers.

[0006] When the above technical solution is adopted, in the semiconductor device provided by the present invention, the insulating layer can electrically isolate the two source / drain regions with opposite conductivity types that are spaced apart along the thickness direction of the semiconductor substrate, thereby improving the electrical reliability of the semiconductor device. In addition, between the channel region included in the first ring-gate transistor and the channel region included in the second ring-gate transistor, not only is a first dielectric isolation layer for reducing leakage and interference provided, but also a second dielectric isolation layer that is alternately stacked with the first dielectric isolation layer is provided. At this time, although the spacing between the first ring-gate transistor and the second ring-gate transistor is relatively large in order to ensure that the insulating layer has sufficient insulating properties, and there are multiple first dielectric isolation layers spaced apart and distributed along the thickness direction of the semiconductor substrate between the channel regions, the presence of the second dielectric isolation layer can fill the gaps between adjacent first dielectric isolation layers. At this time, when forming a gate stack structure, the presence of the second dielectric isolation layer can prevent the gate stack structure from filling the gap between the adjacent first dielectric isolation layers, so that the gate stack structure included in the first ring-gate transistor and / or the gate stack structure included in the second ring-gate transistor is only located at the periphery of the alternately stacked first dielectric isolation layer and the second dielectric isolation layer, thereby increasing the thickness of the middle dielectric, which is beneficial to reducing the parasitic capacitance between the gate stack structures and improving the AC characteristics of the semiconductor device.

[0007] In one example, the first dielectric isolation layer and the second dielectric isolation layer are not formed in one piece.

[0008] In one example, the material of the second dielectric isolation layer is the same as the material of the first dielectric isolation layer.

[0009] In one example, the dielectric constant of the material of the second dielectric isolation layer is smaller than the dielectric constant of the material of the first dielectric isolation layer.

[0010] In one example, the material of the first dielectric isolation layer includes at least one of SiN, SiCO and SiCON.

[0011] In one example, the material of the second dielectric isolation layer includes at least one of SiO2, SiN, SiCO, SiCON and SiO2-SiF4.

[0012] In one example, the thickness of the first dielectric isolation layer and / or the second dielectric isolation layer is greater than or equal to 10 nm and less than or equal to 30 nm.

[0013] In one example, the semiconductor device further includes a gate sidewall, which is disposed at least on two sides of the gate stack structure along its length direction, and the gate sidewall and the first dielectric isolation layer are integrally formed.

[0014] Or, the semiconductor device further includes a gate sidewall. The gate sidewall is at least arranged on both sides of the gate stack structure along its own length direction. The gate sidewall includes a first sidewall and a second sidewall stacked along the length direction of the gate stack structure. The second sidewall is arranged on the side of the first sidewall away from the gate stack structure. The first sidewall and the first dielectric isolation layer are integrally formed, and the second sidewall and the second dielectric isolation layer are integrally formed.

[0015] In one example, the first all-around gate transistor and / or the second all-around gate transistor further includes an inner sidewall disposed between the gate stack structure and the source / drain region.

[0016] In one example, the inner sidewalls of the first gate-all-around transistor and the second gate-all-around transistor are integrally formed.

[0017] In one example, a material of a gate stack structure included in the first gate-all-around transistor is different from a material of a gate stack structure included in the second gate-all-around transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0019] Figure 1 A schematic longitudinal cross-sectional view of the structure of a three-dimensional stacked complementary transistor in the related art;

[0020] Figure 2 A schematic longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present invention Figure 1 ;

[0021] Figure 3 A schematic longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present invention Figure 2 ;

[0022] Figure 4 A schematic longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present invention Figure 3 ;

[0023] Figure 5 A schematic longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present invention Figure 4 .

[0024] Figure numerals: 11 is a semiconductor substrate, 12 is a first ring-gate transistor, 13 is a second ring-gate transistor, 14 is an insulating layer, 15 is a first dielectric isolation layer, 16 is a second dielectric isolation layer, 17 is a source / drain region, 18 is a channel region, 19 is a gate stack structure, 20 is a gate sidewall, 21 is a first sidewall, 22 is a second sidewall, 23 is an inner sidewall, 24 is a shallow trench isolation structure, and 25 is an interlayer dielectric layer. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0026] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0027] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] The three-dimensional stacked complementary transistor includes a vertically stacked N-type transistor and a P-type transistor, eliminating the lateral spacing between the N-type transistor and the P-type transistor, which allows the effective channel width to be further increased, thereby improving the performance and integration of the semiconductor device. However, in the existing three-dimensional stacked complementary transistor, the parasitic capacitance between the gate stack structure included in the upper ring-gate transistor and the lower ring-gate transistor is large, resulting in a deterioration in the AC characteristics of the three-dimensional stacked complementary transistor.

[0031] Specifically, the existing three-dimensional stacked complementary transistor usually includes a middle dielectric isolation layer arranged between the channel region included in the upper ring gate transistor and the channel region included in the lower ring gate transistor to reduce leakage or interference between the upper ring gate transistor and the lower ring gate transistor. In addition, when the upper ring gate transistor and the lower ring gate transistor use different metal gate materials, it is necessary to fill the gate formation area with protective materials such as spin-coated carbon and perform back etching to expose only the nanostructure of the upper ring gate transistor. At this time, if the middle dielectric isolation layer does not exist, when the above-mentioned protective material is back-etched, the part of the protective material located below the nanostructure included in the upper ring gate transistor is difficult to clean, thereby affecting the subsequent formation of the first layer of metal gate; in other words, the existence of the middle dielectric isolation layer is also conducive to improving the yield of semiconductor devices.

[0032] In the actual manufacturing process, it is necessary to first form a fin structure on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes an alternately stacked first sacrificial layer and a channel layer, and an alternately stacked second sacrificial layer and a third sacrificial layer. Among them, the remaining channel layer (the remaining channel layer is used to form a channel region) will be released by selectively removing the portion of the first sacrificial layer corresponding to the gate formation area, so as to form a gate stack structure surrounding the remaining channel layer. Subsequently, a middle dielectric isolation layer is formed by selectively etching the second sacrificial layer to isolate the gate stack structure of the upper ring-gate transistor included in the three-dimensional stacked complementary transistor from the gate stack structure of the lower ring-gate transistor. As for the above-mentioned third sacrificial layer. In the existing manufacturing method, the material of the third sacrificial layer is the same as that of the first sacrificial layer, so as to alleviate the need to consider problems such as stress distribution and stress matching between thin films due to the large difference in materials of the above-mentioned different sacrificial layers. At this time, when the first sacrificial layer is operated accordingly, the third sacrificial layer will also be affected accordingly. In this case, if Figure 1 As shown, in the three-dimensional stacked complementary transistor formed by the existing manufacturing method, a gate stack structure will be subsequently formed at the position where the portion of the third sacrificial layer corresponding to the gate formation area is located. The gate stack structure not only surrounds the periphery of the channel area, but also surrounds the periphery of the middle dielectric isolation layer, so that the parasitic capacitance between the gate stack structure included in the upper ring gate transistor and the lower ring gate transistor is large, resulting in the deterioration of the AC characteristics of the three-dimensional stacked complementary transistor.

[0033] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device. Among them, in the semiconductor device provided by the embodiment of the present invention, in the alternately stacked first dielectric isolation layer and the second dielectric isolation layer, the first dielectric isolation layer can reduce the leakage or interference between the first ring gate transistor and the second ring gate transistor. The presence of the second dielectric isolation layer can prevent the gate stack structure from filling the gap between the adjacent layers of the first dielectric isolation layer, so that the gate stack structure included in the first ring gate transistor and / or the gate stack structure included in the second ring gate transistor is only located at the periphery of the alternately stacked first dielectric isolation layer and the second dielectric isolation layer, reducing the parasitic capacitance between the gate stack structures and improving the AC characteristics of the semiconductor device.

[0034] Specifically, if Figure 2 As shown, the semiconductor device provided by the embodiment of the present invention includes: a semiconductor substrate 11, a first all-round gate transistor 12, a second all-round gate transistor 13, an insulating layer 14, and a first dielectric isolation layer 15 and a second dielectric isolation layer 16. The first all-round gate transistor 12 is arranged on the semiconductor substrate 11. The second all-round gate transistor 13 is arranged above the first all-round gate transistor 12. The conductivity type of the second all-round gate transistor 13 is opposite to that of the first all-round gate transistor 12. The insulating layer 14 is arranged between the source / drain region 17 included in the first all-round gate transistor 12 and the source / drain region 17 included in the second all-round gate transistor 13. Along the thickness direction of the semiconductor substrate 11, the first dielectric isolation layer 15 and the second dielectric isolation layer 16 are alternately stacked and arranged between the channel region 18 included in the first all-round gate transistor 12 and the channel region 18 included in the second all-round gate transistor 13. The gate stack structure 19 included in the first ring-gate transistor 12 and / or the gate stack structure 19 included in the second ring-gate transistor 13 are located at the periphery of the alternately stacked first dielectric isolation layers 15 and the second dielectric isolation layers 16, and the film layers located at the bottom and top layers of the alternately stacked first dielectric isolation layers 15 and the second dielectric isolation layers 16 are both the first dielectric isolation layers 15.

[0035] In actual application, the embodiment of the present invention does not specifically limit the material and structure of the semiconductor substrate, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention.

[0036] Exemplarily, the semiconductor substrate may be a semiconductor substrate on which no structure is formed, such as a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate or a germanium substrate.

[0037] Alternatively, the semiconductor substrate may also be a semiconductor substrate with some structures formed thereon. For example, when the semiconductor device in the embodiment of the present invention is a second-layer or higher-layer semiconductor device in an integrated circuit, the semiconductor substrate includes a semiconductor structure and an interlayer dielectric layer located below the first ring-gate transistor.

[0038] For the above-mentioned first ring-gate transistor and the second ring-gate transistor, from the aspect of the conductivity type, the embodiment of the present invention does not specifically limit the conductivity type of the first ring-gate transistor and the second ring-gate transistor, as long as the conductivity type of the second ring-gate transistor and the first ring-gate transistor are opposite. For example: the first ring-gate transistor can be an N-type ring-gate transistor, in which case the second ring-gate transistor is a P-type ring-gate transistor, and the P-type ring-gate transistor is arranged above the N-type ring-gate transistor. For another example: the first ring-gate transistor can also be a P-type ring-gate transistor, in which case the second ring-gate transistor is an N-type ring-gate transistor, and the N-type ring-gate transistor is arranged above the P-type ring-gate transistor.

[0039] From a structural perspective, the first gate-all-around transistor and the second gate-all-around transistor may both include a channel region, a source / drain region, and a gate stack structure. Figure 2 As shown, in the same first all-around gate transistor 12 or the same second all-around gate transistor 13, the channel region 18 is located between the source / drain regions 17, and both ends of the channel region 18 along the length direction are respectively in contact with the source / drain regions 17. The gate stack structure 19 surrounds the periphery of the channel region 18. The channel region 18 may include only one layer of nanostructure, or may include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate 11. In addition, the number of layers of the nanostructures included in the first all-around gate transistor 12 may be the same or different.

[0040] The materials of the above-mentioned source / drain regions and channel regions may include any semiconductor material such as silicon, silicon germanium or germanium. Among them, the material of the source / drain region and / or channel region included in the first ring-gate transistor may be the same as or different from the material of the source / drain region and / or channel region included in the second ring-gate transistor. Secondly, the material of the channel region included in the first ring-gate transistor may be the same as or different from the material of the source / drain region. The material of the channel region included in the second ring-gate transistor may be the same as or different from the material of the source / drain region.

[0041] As for the gate stack structure included in the first ring-gate transistor and the gate stack structure included in the second ring-gate transistor, the material of the gate dielectric layer included in the gate stack structure may include any insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the above-mentioned gate may include any conductive material such as TiN, TaN or TiSiN. Among them, the materials of the gate stack structure included in the first ring-gate transistor and the gate stack structure included in the second ring-gate transistor may be the same or different.

[0042] It is worth noting that when the material of the gate stack structure included in the first ring-gate transistor is different from the material of the gate stack structure included in the second ring-gate transistor, the presence of the first dielectric isolation layer and the second dielectric isolation layer alternately stacked can also provide a larger process window for manufacturing gate stack structures of different materials, which is beneficial to improving the yield of semiconductor devices. Among them, the difference in the materials of the gate stack structure included in the first ring-gate transistor and the gate stack structure included in the second ring-gate transistor can refer to: the materials of the gate dielectric layer included in the first ring-gate transistor and the gate dielectric layer included in the second ring-gate transistor are different (the materials may be partially different or completely different), but the gate included in the first ring-gate transistor and the gate included in the second ring-gate transistor are the same. It can also refer to that the materials of the gate dielectric layer included in the first ring-gate transistor and the gate dielectric layer included in the second ring-gate transistor are the same, but the materials of the gate included in the first ring-gate transistor and the gate included in the second ring-gate transistor are different (the materials may be partially different or completely different). It is also possible that the materials of the gate dielectric layer included in the first ring-gate transistor and the gate dielectric layer included in the second ring-gate transistor are different (the materials may be partially different or completely different), and the materials of the gate included in the first ring-gate transistor and the gate included in the second ring-gate transistor are also different (the materials may be partially different or completely different).

[0043] In some cases, such as Figure 3 As shown, the semiconductor device may further include a shallow trench isolation structure 24. The shallow trench isolation structure 24 is disposed on the semiconductor substrate 11 to isolate different active regions on the semiconductor substrate 11 to prevent leakage.

[0044] In some cases, such as Figure 4 As shown, the semiconductor device may further include a gate spacer 20, which is disposed at least on both sides of the gate stack structure 19 along its length direction to isolate the gate stack structure 19 from other adjacent conductive structures to prevent leakage or interference. Figure 4 As shown, the gate spacer 20 may be a single-layer structure. Alternatively, the gate stack structure 19 may also be a stacked structure. Figure 5 As shown, the gate sidewall 20 includes a first sidewall 21 and a second sidewall 22 stacked along the length direction of the gate stack structure 19, and the second sidewall 22 is arranged on the side of the first sidewall 21 away from the gate stack structure 19. Specifically, the materials of the first sidewall 21 and the second sidewall 22 can be the same or different. The specific materials of the first sidewall 21 and the second sidewall 22 can be set according to the actual manufacturing process and actual needs, and are not specifically limited here.

[0045] In some cases, such as Figure 2As shown, the first ring-gate transistor 12 and / or the second ring-gate transistor 13 may further include an inner sidewall 23. The inner sidewall 23 is disposed between the gate stack structure 19 and the source / drain region 17 to limit the length of the gate stack structure 19 and improve the yield of the semiconductor device. Among them, only the first ring-gate transistor may include the inner sidewall, while the second ring-gate transistor may not include the inner sidewall. Alternatively, the second ring-gate transistor may include the inner sidewall, while the first ring-gate transistor may not include the inner sidewall. Alternatively, as Figure 2 As shown, the first all-round gate transistor 12 and the second all-round gate transistor 13 both include the inner sidewall 23. In this case, in the actual manufacturing process, the inner sidewall 23 included in the first all-round gate transistor 12 and the second all-round gate transistor 13 can be integrally formed to improve the manufacturing efficiency of the semiconductor device and help reduce the manufacturing cost of the semiconductor device. Alternatively, the inner sidewall 23 included in the first all-round gate transistor 12 and the second all-round gate transistor 13 can also be formed separately in different operation steps.

[0046] In some cases, such as Figure 2 As shown, the semiconductor device may further include an interlayer dielectric layer 25 disposed on the semiconductor substrate 11. The top of the interlayer dielectric layer 25 is flush with the top of the gate stack structure 19 included in the second all-around gate transistor 13 to protect the source / drain region 17 from being affected by operations such as etching or cleaning, thereby improving the yield of the semiconductor device.

[0047] In terms of materials, the materials of the shallow trench isolation structure, gate sidewalls and inner sidewalls can be set according to the actual manufacturing process and actual needs, and are not specifically limited here. Exemplarily, the materials of the shallow trench isolation structure, gate sidewalls or inner sidewalls can include any insulating material such as silicon oxide or silicon nitride.

[0048] For the above-mentioned insulating layer, the insulating layer is arranged between the source / drain region included in the first ring-gate transistor and the source / drain region included in the second ring-gate transistor, and is used to electrically isolate the two source / drain regions of opposite conductivity types. Based on this, the thickness of the above-mentioned insulating layer can be determined according to the leakage protection requirements between the two source / drain regions of opposite conductivity types in the actual application scenario, and is not specifically limited here. The material of the insulating layer may include any insulating material such as silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbide.

[0049] For the first dielectric isolation layer and the second dielectric isolation layer, the number of layers of the first dielectric isolation layer and the second dielectric isolation layer can be determined according to the thickness of a single layer of the first dielectric isolation layer and a single layer of the second dielectric isolation layer, and the thickness of the insulating layer, as long as the total thickness of the alternatingly stacked first dielectric isolation layer and the second dielectric isolation layer is roughly the same as the total thickness of the insulating layer.

[0050] The thickness of the single-layer first dielectric isolation layer and the single-layer second dielectric isolation layer can be set according to the actual manufacturing process and actual needs, and is not specifically limited here.

[0051] For example, Figure 4 As shown, when the semiconductor device also includes a gate spacer 20, and the gate spacer 20 and the first dielectric isolation layer 15 are integrally formed, the material of the first dielectric isolation layer 15 is the same as that of the gate spacer 20, and the thickness of the single-layer first dielectric isolation layer 15 is less than or equal to the thickness of the gate spacer 20.

[0052] It should be noted that, when the semiconductor device further includes a gate spacer, the gate spacer and the first dielectric isolation layer may be manufactured and formed separately in different operation steps. In this case, the material of the first dielectric isolation layer may be the same as or different from that of the gate spacer. The thickness of the first dielectric isolation layer may be greater than, equal to, or less than the thickness of the gate spacer.

[0053] For example, Figure 5 As shown, in the case where the semiconductor device further includes a gate spacer 20, and the gate spacer 20 includes a first spacer 21 and a first dielectric isolation layer 15 that are integrally formed, and a second spacer 22 and a second dielectric isolation layer 16 that are integrally formed, the material of the first dielectric isolation layer 15 is the same as that of the first spacer 21, and the thickness of a single layer of the first dielectric isolation layer 15 can be less than or equal to the thickness of the first spacer 21. The material of the second dielectric isolation layer 16 is the same as that of the second spacer 22, and the thickness of a single layer of the second dielectric isolation layer 16 can be less than or equal to the thickness of the second spacer 22.

[0054] It should be noted that, in the case where the semiconductor device further includes a first side wall and a second side wall, the first side wall may be manufactured and formed separately from the first dielectric isolation layer in different operation steps, and the second side wall may be manufactured and formed separately from the second dielectric isolation layer in different operation steps. Based on this, the material of the first dielectric isolation layer may be the same as or different from the material of the first side wall. The thickness of the first dielectric isolation layer may be greater than, equal to, or less than the thickness of the first side wall. The material of the second dielectric isolation layer may be the same as or different from the material of the second side wall. The thickness of the second dielectric isolation layer may be greater than, equal to, or less than the thickness of the second side wall.

[0055] As for the specific thickness of the first dielectric isolation layer, illustratively, the thickness of the first dielectric isolation layer and / or the second dielectric isolation layer may be greater than or equal to 10nm and less than or equal to 30nm. For example, the thickness of the first dielectric isolation layer and / or the second dielectric isolation layer may be 10nm, 12nm, 15nm, 18nm, 20nm, 22nm, 25nm, 28nm or 30nm, etc. In this case, it can be understood that when manufacturing the first ring-gate transistor, the second ring-gate transistor, the insulating layer and the first dielectric isolation layer and the second dielectric isolation layer alternately stacked on the semiconductor substrate, a fin structure will first be formed on the semiconductor substrate, and the portion of the fin structure corresponding to the first dielectric isolation layer and the second dielectric isolation layer alternately stacked will be pre-formed with a corresponding sacrificial layer. The materials of the two sacrificial layers corresponding to the first dielectric isolation layer and the second dielectric isolation layer may be different, so as to manufacture the first dielectric isolation layer and the second dielectric isolation layer respectively (that is, the first dielectric isolation layer and the second dielectric isolation layer are not integrally formed), so as to prevent the difficulty of simultaneously filling and forming the first dielectric isolation layer and the second dielectric isolation layer in a larger space. Based on this, when the thickness of the first dielectric isolation layer and / or the second dielectric isolation layer is within the above range, it means that the thickness of the corresponding sacrificial layer is also roughly within the above range. At this time, the thickness of the sacrificial layer is relatively large, and the materials of different sacrificial layers are similar. Therefore, the limitation of the critical thickness of the epitaxial growth can be reduced. There is no need to form more layers of different sacrificial layers with smaller layer thicknesses as in the existing manufacturing method, or there is no need to form a fixed number of different sacrificial layers due to the critical thickness limitation, resulting in the thickness of the insulating layer used to isolate the source / drain regions with opposite conductivity types is also smaller to prevent leakage.

[0056] As for the material of the second dielectric isolation layer and the material of the first dielectric isolation layer, the material of the second dielectric isolation layer and the material of the first dielectric isolation layer can be the same. In this case, after the second dielectric isolation layer and the first dielectric isolation layer are formed, when the source and drain etching of the fin structure is performed, the etchant can remove the sacrificial layer and the channel layer located above the second dielectric isolation layer and the first dielectric isolation layer and whose material is semiconductor material. Then, the second dielectric isolation layer and the first dielectric isolation layer can be etched based on the same etchant, without changing the etchant, thereby improving the etching efficiency and reducing the difficulty of manufacturing semiconductor devices.

[0057] Alternatively, the material of the second dielectric isolation layer and the material of the first dielectric isolation layer may also be different. In this case, the material of the second dielectric isolation layer and the material of the first dielectric isolation layer may be set separately according to different actual requirements.

[0058] Exemplarily, the dielectric constant of the material of the second dielectric isolation layer may be smaller than the dielectric constant of the material of the first dielectric isolation layer. In this case, since the dielectric constant of the material of the second dielectric isolation layer is proportional to the magnitude of the parasitic capacitance between the gate stack structure included in the first all-around gate transistor and the second all-around gate transistor, when the dielectric constant of the material of the second dielectric isolation layer is smaller than the dielectric constant of the material of the first dielectric isolation layer, it is beneficial to further reduce the parasitic capacitance between the two gate stack structures, and further improve the AC characteristics of the semiconductor device.

[0059] As for the specific materials of the first dielectric isolation layer and the second dielectric isolation layer, illustratively, the material of the first dielectric isolation layer may include at least one of SiN, SiCO and SiCON.

[0060] Exemplarily, the material of the second dielectric isolation layer may include at least one of SiO2, SiN, SiCO, SiCON and SiO2-SiF4.

[0061] When the above technical solution is adopted, Figure 2 As shown, in the semiconductor device provided by the embodiment of the present invention, the insulating layer 14 can electrically isolate the two source / drain regions 17 of opposite conductivity types which are arranged at intervals along the thickness direction of the semiconductor substrate 11, thereby improving the electrical reliability of the semiconductor device. In addition, between the channel region 18 included in the first all-round gate transistor 12 and the channel region 18 included in the second all-round gate transistor 13, not only a first dielectric isolation layer 15 for reducing leakage and interference is arranged, but also a second dielectric isolation layer 16 which is alternately stacked with the first dielectric isolation layer 15 is arranged. At this time, although the spacing between the first all-round gate transistor 12 and the second all-round gate transistor 13 is relatively large in order to ensure that the insulating layer 14 has sufficient insulation properties, and there are multiple first dielectric isolation layers 15 spaced apart and distributed along the thickness direction of the semiconductor substrate 11 between the channel regions 18, the presence of the second dielectric isolation layer 16 can fill the gaps between adjacent first dielectric isolation layers 15. At this time, when forming the gate stack structure 19, the presence of the second dielectric isolation layer 16 can prevent the gate stack structure 19 from filling the gap between the adjacent first dielectric isolation layers 15, so that the gate stack structure 19 included in the first ring-gate transistor 12 and / or the gate stack structure 19 included in the second ring-gate transistor 13 is only located at the periphery of the alternatingly stacked first dielectric isolation layers 15 and second dielectric isolation layers 16, thereby increasing the thickness of the middle dielectric, which is beneficial to reducing the parasitic capacitance between the gate stack structures 19 and improving the AC characteristics of the semiconductor device.

[0062] An embodiment of the present invention provides a method for manufacturing the semiconductor device described above, and the method for manufacturing the semiconductor device comprises the following steps:

[0063] First, epitaxy and selective etching processes can be used to form a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes an alternately stacked first sacrificial layer and a channel layer, and an alternately stacked second sacrificial layer and a third sacrificial layer. The alternately stacked first sacrificial layer and the channel layer are located on both sides of the alternately stacked second sacrificial layer and the third sacrificial layer in the thickness direction. The film layers located at the bottom and top layers of the alternately stacked first sacrificial layer and the channel layer are both first sacrificial layers. The film layers located at the bottom and top layers of the alternately stacked second sacrificial layer and the third sacrificial layer are both second sacrificial layers.

[0064] Specifically, the first sacrificial layer, the second sacrificial layer and the third sacrificial layer have different functions respectively. Specifically, the remaining channel layer (the remaining channel layer is used to form the channel region) will be released by selectively removing the portion of the first sacrificial layer corresponding to the gate formation area, so as to form a gate stack structure surrounding the periphery of the remaining channel layer. Subsequently, the second sacrificial layer will be selectively etched to form a first dielectric isolation layer for isolating the gate stack structure of the upper device included in the three-dimensional stacked complementary transistor from the gate stack structure of the lower device. As for the above-mentioned third sacrificial layer, the position where the portion of the third sacrificial layer corresponding to the gate formation area is located will also form a second dielectric isolation layer for isolation and blocking. Based on this, a certain etching selectivity ratio is required between the first sacrificial layer, the second sacrificial layer and the third sacrificial layer to achieve separate release.

[0065] Specifically, the materials of the second sacrificial layer and the third sacrificial layer can be different from the material of the first sacrificial layer. The materials of the second sacrificial layer and the third sacrificial layer can be different; or, the materials of the two can be the same, and the second sacrificial layer is doped with an etching auxiliary agent to accelerate the etching effect.

[0066] Exemplarily, the material of one of the second sacrificial layer and the third sacrificial layer may include silicon or silicon germanium, and the material of the other may include silicon germanium or germanium. The difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%, and the second sacrificial layer is doped with an etching aid. Among them, the etching aid may be an N-type dopant (such as phosphorus or arsenic, etc.). The doping concentration of the etching aid in the second sacrificial layer can be determined according to the etching requirements of the second sacrificial layer in the actual application scenario, and is not specifically limited here. Exemplarily, the doping concentration of the etching aid in the above-mentioned second sacrificial layer may be greater than or equal to 1E18cm -3 , and less than or equal to 1E19cm -3 .

[0067] Next, a deposition and etching process may be used to form a mask structure that spans the fin structure. The mask structure may include a sacrificial gate (or a sacrificial gate and a gate oxide layer).

[0068] Next, the second sacrificial layer is selectively removed to form a first dielectric filling region. The first sacrificial layer and the third sacrificial layer are retained. At this time, the second sacrificial layer can be selectively etched only based on the difference in material between the second sacrificial layer and the first sacrificial layer and the third sacrificial layer, and / or, the second sacrificial layer can be selectively etched at least under the accelerated etching effect of the etching auxiliary agent.

[0069] The selective etching process and the type of etchant can be determined according to the material of the second sacrificial layer and the type of etching auxiliary agent, and are not specifically limited here.

[0070] For example, when a wet etching process is used to selectively remove the second sacrificial layer, the wet etching solution may include a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0071] Exemplarily, when a dry etching process is used to selectively remove the second sacrificial layer, the etching gas includes a mixed gas of CF 4 , O 2 and He.

[0072] Next, a first dielectric isolation layer may be formed in the first dielectric filling region by using processes such as deposition and etching.

[0073] Next, the first sacrificial layer, the channel layer, the first dielectric isolation layer and the third sacrificial layer that are not covered by the mask structure are removed.

[0074] In an actual manufacturing process, after forming the first dielectric isolation layer, the first sacrificial layer, the channel layer, the first dielectric isolation layer and the third sacrificial layer not covered by the mask structure may be removed together to facilitate the subsequent formation of source / drain regions.

[0075] Alternatively, when the material of the first sacrificial layer is different from the material of the third sacrificial layer, a process such as wet etching or dry etching may be used to selectively remove the third sacrificial layer first to form a third dielectric filling area; then, a deposition and etching process is used to form a second dielectric isolation layer in the third dielectric filling area. Next, the first sacrificial layer, the channel layer, the first dielectric isolation layer, and the second dielectric isolation layer that are not covered by the mask structure are removed. A process such as wet etching or dry etching is used. At this time, when the gate stack structure is subsequently formed, the gate stack structure will not be filled in the gap between two adjacent first dielectric isolation layers, thereby reducing parasitic capacitance and further improving the operating performance of the manufactured semiconductor device.

[0076] Next, epitaxial growth or other processes may be used to form source / drain regions of the first all-around gate transistor on both sides of the remaining first sacrificial layer and the channel layer below the remaining first dielectric isolation layer.

[0077] Next, an insulating layer may be formed on the source / drain regions of the first all-around gate transistor by using processes such as deposition and etching.

[0078] Next, epitaxy or other processes may be used to form source / drain regions included in the second all-around gate transistor on the insulating layer and on both sides of the remaining first sacrificial layer and the channel layer located above the remaining first dielectric isolation layer. The conductivity type of the source / drain region included in the second all-around gate transistor is opposite to the conductivity type of the source / drain region included in the first all-around gate transistor.

[0079] Next, deposition and planarization processes may be used to form an interlayer dielectric layer covering the semiconductor substrate. The top of the interlayer dielectric layer is flush with the top of the mask structure.

[0080] Next, the mask structure is removed by using a process such as wet etching or dry etching.

[0081] It should be noted that if the second dielectric isolation layer is not formed in the foregoing, after the interlayer dielectric layer is formed and the mask structure is removed, a process such as wet etching or dry etching can be used to remove the remaining third sacrificial layer to obtain a second dielectric filling area. Then, a second dielectric isolation layer is formed in the second dielectric filling area by using processes such as deposition and etching.

[0082] If the second dielectric isolation layer has been formed before forming the source / drain regions included in the first all-around gate transistor, subsequent operations can be performed directly.

[0083] Next, a process such as wet etching or dry etching is used to remove the remaining first sacrificial layer.

[0084] Next, a gate stack structure surrounding the remaining channel layer is formed by using processes such as atomic layer deposition.

[0085] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0086] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor substrate; A first gate-all-around transistor is disposed on a semiconductor substrate; a second all-round gate transistor, disposed above the first all-round gate transistor; the second all-round gate transistor and the first all-round gate transistor have opposite conductivity types; An insulating layer, disposed between a source / drain region included in the first all-around gate transistor and a source / drain region included in the second all-around gate transistor; and a first dielectric isolation layer and a second dielectric isolation layer; along the thickness direction of the semiconductor substrate, the first dielectric isolation layer and the second dielectric isolation layer are alternately stacked between the channel region included in the first ring-gate transistor and the channel region included in the second ring-gate transistor; the gate stack structure included in the first ring-gate transistor and / or the gate stack structure included in the second ring-gate transistor are located at the periphery of the alternately stacked first dielectric isolation layer and the second dielectric isolation layer, and the film layers located at the bottom and top layers of the alternately stacked first dielectric isolation layer and the second dielectric isolation layer are both the first dielectric isolation layer.

2. The semiconductor device according to claim 1, wherein: The first dielectric isolation layer and the second dielectric isolation layer are not formed in one piece.

3. The semiconductor device according to claim 1, wherein: The material of the second dielectric isolation layer is the same as that of the first dielectric isolation layer.

4. The semiconductor device according to claim 1, wherein: The dielectric constant of the material of the second dielectric isolation layer is smaller than the dielectric constant of the material of the first dielectric isolation layer.

5. The semiconductor device according to claim 1, wherein: The material of the first dielectric isolation layer includes: at least one of SiN, SiCO and SiCON; And / or, the material of the second dielectric isolation layer includes: at least one of SiO2, SiN, SiCO, SiCON and SiO2-SiF4.

6. The semiconductor device according to claim 1, wherein: The thickness of the first dielectric isolation layer and / or the second dielectric isolation layer is greater than or equal to 10 nm and less than or equal to 30 nm.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a gate sidewall; the gate sidewall is at least arranged on both sides of the gate stack structure along its own length direction; the gate sidewall and the first dielectric isolation layer are integrally formed; Alternatively, the semiconductor device further includes a gate sidewall; the gate sidewall is at least arranged on both sides of the gate stack structure along its own length direction; the gate sidewall includes a first sidewall and a second sidewall stacked along the length direction of the gate stack structure; the second sidewall is arranged on the side of the first sidewall away from the gate stack structure; the first sidewall and the first dielectric isolation layer are integrally formed, and the second sidewall and the second dielectric isolation layer are integrally formed.

8. The semiconductor device according to claim 1, wherein: The first all-around gate transistor and / or the second all-around gate transistor further includes an inner sidewall; the inner sidewall is arranged between the gate stack structure and the source / drain region.

9. The semiconductor device according to claim 8, characterized in that The inner sidewalls of the first gate-all-around transistor and the second gate-all-around transistor are integrally formed.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The material of the gate stack structure included in the first all-around gate transistor is different from the material of the gate stack structure included in the second all-around gate transistor.

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