Quasi-vertical P-FET device, integrated inverter and preparation method of quasi-vertical P-FET device

Abstract

The invention discloses a quasi-vertical P-FET device, an integrated inverter and a preparation method of the quasi-vertical P-FET device. The quasi-vertical P-FET device comprises a first substrate, a first semiconductor base structure layer and a semiconductor drift structure layer, wherein the first semiconductor base structure layer and the semiconductor drift structure layer are sequentially arranged on the first substrate; two-dimensional hole gas is formed in the first semiconductor base structure layer; the semiconductor drift structure layer comprises a P-GaN drift layer, an N-GaN base layer and a P < + >-GaN drift layer which are sequentially arranged on the first semiconductor base structure layer; a drain electrode growth region of the semiconductor drift structure layer is provided with a drain electrode step, and the drain electrode step penetrates through the whole semiconductor drift structure layer; a gate groove is formed in a first gate position region of the semiconductor drift structure layer and extends to the P-GaN drift layer; the first drain electrode is arranged at the bottom of the drain electrode step; the gate oxide layer and the first gate electrode are sequentially arranged in the gate groove; and the first source electrode is arranged on the P < + >-GaN drift layer. The quasi-vertical P-FET device provided by the invention is low in production cost and high in conduction current density.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a quasi-vertical P-FET device, an integrated inverter and a preparation method thereof. Background Art

[0002] At present, GaN monolithic integration has gradually become the main development trend of power module design based on GaN devices. However, due to the lack of mature GaN P-FET devices, in the circuit drive design of GaN power devices, it is more common to use N-type E / D-mod cascaded depletion load inverters to form direct coupled FET logic (DCFL). However, N-type devices will generate higher static leakage current when the circuit is working, resulting in higher static power consumption of the inverter. Therefore, how to achieve high-performance P-FET that can be monolithically integrated with the current mainstream commercial P-GaN gate GaN N-HEMTS, and then simplify GaN IC design, improve GaN IC performance, and give full play to the high-speed and efficient working performance of GaN power devices has become an urgent problem to be solved.

[0003] At present, a lot of work has been done on GaN P-FET devices, but it is difficult to completely solve the problem: for example, considering that it is precisely because of the large effective mass and strong low-energy phonon scattering in GaN P-FET devices that the hole mobility in GaN materials is difficult to improve, the current density of GaN P-FET devices is 1-1.5 orders of magnitude lower than that of N-HEMTS. Therefore, in order to make the P-FET current adapt to N-HEMTS, the method of increasing the P-FET chip area is adopted, but this will cause the P-FET parasitic capacitance to become larger and the switching speed to be slower, which will lead to circuit current transport mismatch; for example, in order to obtain high saturation current, a research team used ALN / GaN heterojunctions with a larger difference in heterogeneous lattice constants to produce 2DHG with a larger piezoelectric polarization effect, higher surface density and hole mobility, so that the on-current density reaches 100mA / mm, but during this period there is a problem with the inability to integrate with mainstream commercial AlGaN / GaN. There are problems. FinFET devices with superlattice structures have also been proposed, but the 2DHG depletion of the multi-layer structure is difficult, and it is difficult to prepare an enhancement-mode device even if the device threshold voltage is positive. For example, in order to prevent the device from being accidentally turned on in actual applications and to increase the threshold voltage of the device, lateral structures such as recessed gate structures, H ion (O ion) implantation structures, and N-GaN / AlGaN that can be integrated with mainstream commercial HEMTS are used. These lateral structures adjust the threshold voltage by adjusting the etching depth or injection depth of the P-GaN under the gate, but the process conditions limit the etching accuracy and depth, making it difficult to accurately control them, and these lateral structures have low on-current density and low threshold voltage. Summary of the invention

[0004] Therefore, in order to solve the problems of the P-FET devices in the above-mentioned prior art, the present invention provides a quasi-vertical P-FET device which has the characteristics of high current conduction density, low leakage current, and high withstand voltage in the vertical direction, and can further increase the current density in the horizontal direction by using the two-dimensional hole gas in the first semiconductor basic structure layer as a carrier channel, and whose preparation process is compatible with the N-FET process.

[0005] To this end, according to a first aspect, the present invention provides a quasi-vertical P-FET device, comprising:

[0006] A first substrate and a first semiconductor basic structure layer and a semiconductor drift structure layer sequentially arranged on the first substrate; a two-dimensional hole gas is formed in the first semiconductor basic structure layer; the semiconductor drift structure layer includes a P-GaN drift layer, an N-GaN base layer and a P-GaN layer sequentially arranged on the first semiconductor basic structure layer + -GaN drift layer; a drain step is provided in the drain growth region of the semiconductor drift structure layer, and the drain step runs through the entire semiconductor drift structure layer; a gate groove is provided in the first gate position region of the semiconductor drift structure layer, and the gate groove extends to the P-GaN drift layer;

[0007] A first drain electrode is disposed at the bottom of the drain step and is spaced apart from the semiconductor drift structure layer;

[0008] A gate oxide layer and a first gate electrode are sequentially arranged on the bottom and sidewall of the gate groove;

[0009] The first source electrode is arranged at P + -GaN drift layer.

[0010] In an optional embodiment, the first semiconductor base structure layer includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-GaN base layer sequentially arranged on the substrate, and two-dimensional hole gas is formed between the P-GaN base layer and the AlGaN barrier layer.

[0011] In an optional embodiment, the gate oxide layer also covers the epitaxial region, and the epitaxial region includes P + - Other regions on the GaN drift layer except the first source location region, the sidewall of the drain step, and the region on the bottom of the drain step except the first drain location region.

[0012] In an optional embodiment, the quasi-vertical P-FET device further includes:

[0013] The insulating layer is arranged on the epitaxial region; and the gate oxide layer of the epitaxial region is arranged on the insulating layer.

[0014] According to a second aspect, the present invention provides an integrated inverter, comprising:

[0015] An N-FET device and a quasi-vertical P-FET device in any one of the embodiments of the first aspect;

[0016] N-FET devices include:

[0017] A second substrate and a second semiconductor basic structure layer arranged on the second substrate, wherein two-dimensional hole gas is formed in the second semiconductor basic structure layer; the second substrate and the first substrate are the same integrated substrate, the second semiconductor basic structure layer and the first semiconductor basic structure layer are formed in the N-FET region and the P-FET region of the same integrated semiconductor basic structure layer, and an isolation groove for cutting off the two-dimensional hole gas is formed between the N-FET region and the P-FET region;

[0018] A second source electrode, a second drain electrode and a second gate electrode are all disposed on the second semiconductor basic structure layer, and the second gate electrode is located between the second source electrode and the second drain electrode;

[0019] The second drain electrode is electrically connected to the first drain electrode, and the second gate electrode is electrically connected to the first gate electrode.

[0020] In an optional embodiment, the epitaxial region also includes a bottom and sidewalls of the isolation trench, and other regions on the second semiconductor base structure layer except the second source location region, the second drain location region, and the second gate location region.

[0021] In an optional embodiment, when the first semiconductor basic structure layer includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-GaN base layer which are sequentially arranged on a substrate, the second semiconductor basic structure layer and the first semiconductor basic structure layer are formed in the N-FET region and the P-FET region of the same integrated semiconductor basic structure layer, and an isolation groove for cutting off the two-dimensional hole gas is formed between the N-FET region and the P-FET region, and the P-GaN base layer in the N-FET region except the gate position region is removed.

[0022] According to a third aspect, the present invention provides a method for preparing an integrated inverter, comprising the following steps:

[0023] An integrated semiconductor basic structure layer and a semiconductor drift structure layer are sequentially grown on an integrated substrate; a two-dimensional hole gas is formed in the integrated semiconductor basic structure layer; the semiconductor drift structure layer comprises a P-GaN drift layer, an N-GaN base layer and a P-GaN layer sequentially arranged on the first semiconductor basic structure layer. + -GaN drift layer;

[0024] Etching and removing the semiconductor drift structure layer in other areas except the P-FET area;

[0025] Etching the integrated semiconductor basic structure layer to form an isolation groove for cutting off the two-dimensional hole gas between the N-FET region and the P-FET region of the integrated semiconductor basic structure layer; the integrated semiconductor basic structure layers of the N-FET region and the P-FET region are respectively the first semiconductor basic structure layer and the second semiconductor basic structure layer;

[0026] Growing a second source electrode and a second drain electrode at a second source location region and a second drain location region on the second semiconductor base structure layer, respectively;

[0027] Etching the semiconductor drift structure layer to form a gate groove in the first gate position region of the semiconductor drift structure layer; the gate groove extends to the P-GaN drift layer;

[0028] growing a gate oxide layer in the gate trench;

[0029] Growing a first drain electrode at the bottom of the drain step, and growing a first source electrode in a first source position region on the semiconductor drift structure layer;

[0030] Growing a first gate electrode on the gate oxide layer, and growing a second gate electrode in a second gate position region on the second semiconductor base structure layer;

[0031] The second drain electrode is electrically connected to the first drain electrode, and the second gate electrode is electrically connected to the first gate electrode.

[0032] In an optional embodiment, before the step of etching the semiconductor drift structure layer to form a gate groove in the first gate position region of the semiconductor drift structure layer, the method further includes:

[0033] A passivation layer is grown on the first surface of the fabricated device.

[0034] The technical solution provided by the present invention has the following advantages:

[0035] 1. The quasi-vertical P-FET device provided by the present invention adopts a groove gate structure that can be integrated with mainstream commercial HEMTS, and is provided with a P-GaN drift layer with different doping concentrations, an N-GaN base layer and a P + -GaN drift layer is used as semiconductor drift structure layer, so that the threshold voltage of the device can be achieved by changing the doping concentration of the drift layer and adjusting the thickness of the gate oxide layer. The gate groove produced by etching the semiconductor drift structure layer mainly affects the breakdown voltage and on-resistance, thereby greatly reducing the etching depth and etching accuracy requirements for the gate groove, reducing the production process restrictions on the device and reducing the production cost;

[0036] At the same time, the quasi-vertical structure of the device has a higher current carrying area flowing in a two-dimensional plane than the lateral structure, and has a shorter current path and an optimized conductive channel, so it has a lower overall on-resistance, thereby supporting a larger current flow, further improving the on-current density of the quasi-vertical P-FET device.

[0037] 2. The integrated inverter provided by the present invention realizes the effective integration of P-FET devices and N-FET devices on the same substrate, has strong applicability and low production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic structural diagram of a quasi-vertical P-FET device provided in Example 1 of the present invention;

[0040] Figure 2 A schematic diagram of the structure of an integrated inverter provided in Embodiment 2 of the present invention;

[0041] Figure 3 A method flow chart of a method for preparing an integrated inverter provided in Example 3 of the present invention;

[0042] Figure 4-Figure 10 A device structure diagram obtained during the implementation of a method for preparing an integrated inverter provided in Example 3 of the present invention;

[0043] Description of reference numerals:

[0044] 10-Integrated semiconductor infrastructure layer;

[0045] 11-a first semiconductor basic structure layer;

[0046] 12-semiconductor drift structure layer; 121-P-GaN drift layer; 122-N-GaN base layer; 123-P + -GaN drift layer;

[0047] 13-gate oxide layer;

[0048] 14- passivation layer;

[0049] 15-first drain electrode; 15a-drain step;

[0050] 16- a first source electrode;

[0051] 17-first gate electrode; 17a-gate groove;

[0052] 21- a second drain electrode;

[0053] 22- a second source electrode;

[0054] 23- a second gate electrode;

[0055] 24-Metal layer. DETAILED DESCRIPTION

[0056] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] In the description of the present invention, it should be noted that the terms "upper", "lower", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0058] Example 1

[0059] This embodiment provides a quasi-vertical P-FET device, such as Figure 1 As shown, the quasi-vertical P-FET device includes a first substrate, a first semiconductor basic structure layer, a semiconductor drift structure layer, a first source electrode, a first drain electrode, a gate oxide layer and a first gate electrode. The first semiconductor basic structure layer and the semiconductor drift structure layer are sequentially arranged on the first substrate; the semiconductor drift structure layer includes a P-GaN drift layer, an N-GaN base layer and a P-GaN layer sequentially arranged on the first semiconductor basic structure layer. + -GaN drift layer, the drain growth region of the semiconductor drift structure layer is provided with a drain step, the drain step runs through the entire semiconductor drift structure layer, the first gate position region of the semiconductor drift structure layer is provided with a gate groove, the gate groove extends to the P-GaN drift layer; the first drain electrode is provided at the bottom of the drain step, and there is a gap between the drain electrode and the semiconductor drift structure layer. The gate oxide layer and the first gate electrode are sequentially provided on the bottom and sidewall of the gate groove, and the first source electrode is provided at the P + -GaN drift layer.

[0060] In this embodiment, the first substrate may be a Si substrate or a SiC substrate.

[0061] In this embodiment, the first semiconductor basic structure layer can be any existing semiconductor structure layer in which two-dimensional hole gas can be formed; in specific implementation, the first semiconductor basic structure layer can be set to include an AlN nucleation layer, a GaN channel layer and an AlGaN barrier layer (two-dimensional hole gas is formed between the GaN channel layer and the AlGaN barrier layer); the first semiconductor basic structure layer can also be set to include a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer (two-dimensional hole gas is formed between the GaN channel layer and the AlGaN barrier layer); the first semiconductor basic structure layer can also be set as Figure 1 As shown in the figure, it includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-GaN base layer (a two-dimensional hole gas is formed between the P-GaN base layer and the AlGaN barrier layer). At this time, the quasi-vertical P-FET device in this embodiment can be turned on in the horizontal direction through the two-dimensional hole gas and the holes in the P-GaN base layer as carriers, and the conduction current density is relatively high.

[0062] In this embodiment, P + The P-GaN drift layer is achieved by heavily doping GaN with acceptor impurities, and the P-GaN drift layer is achieved by doping GaN with a relatively low concentration (relative to P + -GaN drift layer) is realized by acceptor impurities, and the N-GaN base layer can be obtained by doping GaN with donor impurities; the P-GaN drift layer, N-GaN base layer and P + The specific doping concentration in the GaN drift layer can be set according to the requirements of the threshold voltage and on-current density of the device in actual application scenarios.

[0063] In the specific implementation, in this embodiment, the drain step and the gate groove can be obtained by photolithography; the gate groove extending to the P-GaN drift layer can be a gate groove that only penetrates the P-GaN drift layer. + The gate groove can penetrate the entire P-GaN drift layer and reach the interface of the P-GaN drift layer. + -The whole of GaN drift layer and part of P-GaN drift layer ( Figure 1 This situation is used as an example in the illustration).

[0064] In this embodiment, the gate oxide layer may be a SiO2 layer or an Al2O3 layer. In this embodiment, if the quasi-vertical P-FET device in this embodiment is in Figure 1The upper surface in the state shown is the first surface, and when the oxide is grown, the entire first surface is covered. After that, all oxides except the oxide in the gate groove can be etched away to form a gate oxide layer deposited only on the bottom and sidewalls of the gate groove; or only the gate oxide in the second source position region and the second drain position region can be etched away, so that the formed gate oxide layer is not only deposited on the bottom and sidewalls of the gate groove, but also covers the epitaxial region, and the epitaxial region includes P + -Other regions on the GaN drift layer except the first source position region, the sidewalls of the drain step, and the region at the bottom of the drain step except the first drain position region, enable the gate oxide layer to passivate the leakage path of the exposed pnp junction and reduce the interface state while reducing the gate leakage.

[0065] In this embodiment, in order to further reduce the leakage current of the quasi-vertical P-FET device, as shown in FIG. Figure 1 As shown, the quasi-vertical P-FET device in this embodiment may further include an insulating layer, which is disposed on the epitaxial region, and the gate oxide layer of the epitaxial region is disposed on the insulating layer. In specific implementation, in order to simplify the preparation process of the device in this embodiment and reduce production costs, a hard mask may be used as a mask plate in the gate groove photolithography process, and the hard mask remaining after photolithography may be directly used as an insulating layer.

[0066] The quasi-vertical P-FET device in this embodiment has a vertical structure, and when the gate is not biased and the drain is negatively biased, the structure can withstand high voltage. At this time, the N-GaN base layer and the drift region (i.e., the P-GaN drift layer and the P-GaN drift region) are + -GaN drift layer) forms a reverse biased PN junction, and the voltage is mainly borne by the P-GaN drift layer; when the gate is negatively biased, a drain current is generated, and an inversion layer channel is formed on the surface of the N-GaN base layer along the longitudinal sidewall of the gate groove; when both the gate and the drain are negatively biased, the inversion layer channel provides a transmission path for holes from the source region to the drain region. In the horizontal structure (taking the first semiconductor basic structure layer including GaN buffer layer, GaN channel layer, AlGaN barrier layer and P-GaN base layer as an example), there is not only the flow of holes in the P-GaN base layer in contact with the first drain electrode, but also the 2DHG formed by the P-GaN layer and the AlGaN layer.

[0067] In summary, the quasi-vertical P-FET device in this embodiment adopts a groove gate structure that can be integrated with mainstream commercial HEMTS, and by setting a P-GaN drift layer with different doping concentrations, an N-GaN base layer and a P +-GaN drift layer is used as semiconductor drift structure layer, so that the threshold voltage of the device can be achieved by changing the doping concentration of the drift layer and adjusting the thickness of the gate oxide layer. The gate groove produced by etching the semiconductor drift structure layer mainly affects the breakdown voltage and on-resistance, thereby greatly reducing the etching depth and etching accuracy requirements for the gate groove, reducing the production process restrictions on the device and reducing the production cost;

[0068] At the same time, the quasi-vertical structure of the device has a higher current carrying area flowing in a two-dimensional plane than the lateral structure, and has a shorter current path and an optimized conductive channel, so it has a lower overall on-resistance, thereby supporting a larger current flow, further improving the on-current density of the quasi-vertical P-FET device.

[0069] Example 2

[0070] This embodiment provides an integrated inverter such as Figure 2 As shown, the integrated inverter includes an N-FET device and a quasi-vertical P-FET device in any specific implementation of the above-mentioned embodiment 1; the N-FET device includes a second substrate, a second semiconductor basic structure layer, a second source electrode, a second drain electrode and a second gate electrode; wherein the second substrate and the first substrate in the quasi-vertical P-FET device are the same integrated substrate; a second semiconductor basic structure layer, a two-dimensional hole gas is formed in the second semiconductor basic structure layer, the second semiconductor basic structure layer and the first semiconductor basic structure layer are formed in the N-FET region and the P-FET region of the same integrated semiconductor basic structure layer, and an isolation groove for cutting off the two-dimensional hole gas is formed between the N-FET region and the P-FET region; the second source electrode, the second drain electrode and the second gate electrode are all arranged on the second semiconductor basic structure layer, and the second gate electrode is located between the second source electrode and the second drain electrode. The second drain electrode in the N-FET device is electrically connected to the first drain electrode in the quasi-vertical P-FET device, and the second gate electrode in the N-FET device is electrically connected to the first gate electrode in the quasi-vertical P-FET device.

[0071] In this embodiment, when the first semiconductor basic structure layer (i.e., the integrated semiconductor basic structure layer) includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a P-GaN base layer sequentially arranged on the substrate, the second semiconductor basic structure layer and the first semiconductor basic structure layer are formed in the N-FET region and the P-FET region of the same integrated semiconductor basic structure layer, and an isolation groove for cutting off the two-dimensional hole gas is formed between the N-FET region and the P-FET region, and the P-GaN base layer of the N-FET region except the gate position region is removed, so that the P-GaN base layer in the gate position region becomes a cap layer under the gate, thereby reducing the leakage current of the N-FET device and reducing power consumption. Of course, in the specific implementation, when the integrated semiconductor basic structure layer does not include the P-GaN base layer, the P-GaN cap layer can also be grown in the gate position region on the second semiconductor basic structure layer by another generation method.

[0072] In this embodiment, the epitaxial region in the above-mentioned embodiment 1 may also include the bottom and side walls of the isolation trench, and other regions on the second semiconductor basic structure layer except the second source position region, the second drain position region and the second gate position region. The gate oxide layer covers these epitaxial regions, which can realize surface passivation of the N-FET device and reduce the surface state; similarly, the insulating layer in the above-mentioned embodiment 1 can also be set to cover these epitaxial regions of the N-FET device.

[0073] In specific implementation, the inverter including the P-FET device and the N-FET device can be expanded to obtain other logic unit devices such as NOT gate and NOR gate.

[0074] In summary, the integrated inverter in this embodiment realizes the effective integration of P-FET devices and N-FET devices on the same substrate, has strong applicability and low production cost.

[0075] Example 3

[0076] This embodiment provides a method for preparing an integrated inverter, which is the method for preparing the integrated inverter in the above embodiment 2; and based on the fact that the integrated inverter in the above embodiment 2 is an integrated device of an N-FET device and the quasi-vertical P-FET device in the above embodiment 1, the preparation method in this embodiment covers the preparation method of the quasi-vertical P-FET device in the above embodiment 1; the specific scheme of this embodiment can be understood by referring to the contents of embodiments 1 and 2. Figure 3 As shown, the method comprises the following steps:

[0077] S301: sequentially growing an integrated semiconductor base structure layer and a semiconductor drift structure layer on an integrated substrate.

[0078] In this embodiment, a two-dimensional hole gas is formed in the integrated semiconductor basic structure layer; the semiconductor drift structure layer includes a P-GaN drift layer, an N-GaN base layer and a P-GaN layer sequentially arranged on the first semiconductor basic structure layer. + -GaN drift layer.

[0079] In this embodiment, the integrated semiconductor basic structure layer can be any existing semiconductor structure layer in which two-dimensional hole gas can be formed; in specific implementation, the integrated semiconductor basic structure layer can be set to include an AlN nucleation layer, a GaN channel layer and an AlGaN barrier layer (two-dimensional hole gas is formed between the GaN channel layer and the AlGaN barrier layer); the integrated semiconductor basic structure layer can also be set to include a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer (two-dimensional hole gas is formed between the GaN channel layer and the AlGaN barrier layer); the integrated semiconductor basic structure layer can also be set as Figure 1 As shown in the figure, it includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-GaN base layer (a two-dimensional hole gas is formed between the P-GaN base layer and the AlGaN barrier layer). At this time, the quasi-vertical P-FET device in this embodiment can be turned on in the horizontal direction through the two-dimensional hole gas and the holes in the P-GaN base layer as carriers, and the conduction current density is relatively high.

[0080] In this embodiment, P + The P-GaN drift layer is achieved by heavily doping GaN with acceptor impurities, and the P-GaN drift layer is achieved by doping GaN with a relatively low concentration (relative to P + -GaN drift layer) is realized by acceptor impurities, and the N-GaN base layer can be obtained by doping GaN with donor impurities; the P-GaN drift layer, N-GaN base layer and P + The specific doping concentration in the GaN drift layer can be set according to the requirements of the threshold voltage and on-current density of the device in actual application scenarios.

[0081] Taking the integrated semiconductor basic structure layer including GaN buffer layer, GaN channel layer, AlGaN barrier layer and P-GaN base layer as an example (the device structure diagram corresponding to the following preparation steps is also taken as an example), the device prepared by this step is as follows Figure 4 shown.

[0082] S302: etching and removing the semiconductor drift structure layer in other regions except the P-FET region.

[0083] In specific implementation, the N-FET region and the P-FET region can be defined by using a hard mask or photoresist, and then the semiconductor drift structure layer in other regions outside the P-FET region (i.e., the N-FET region and the region corresponding to the isolation trench described below) can be removed by etching or other processes.

[0084] S303: etching the integrated semiconductor basic structure layer to form an isolation groove for cutting off two-dimensional hole gas between the N-FET region and the P-FET region of the integrated semiconductor basic structure layer.

[0085] In this embodiment, the integrated semiconductor basic structure layer of the N-FET region and the integrated semiconductor basic structure layer of the P-FET region are respectively the first semiconductor basic structure layer in the above embodiment 1 and the second semiconductor basic structure layer in the above embodiment 2.

[0086] In this embodiment, based on the fact that N-type carriers also flow between the GaN channel layer and the AlGaN barrier layer, Figure 5 As shown, the isolation groove in this step should not only penetrate the P-GaN base layer and the AlGaN barrier layer, but also penetrate at least part of the GaN channel layer (the thickness of the penetrated part is based on the ability to block the flow of carriers). In specific implementation, the N-FET region, the P-FET region and the isolation groove region can be defined by a hard mask or photoresist, and then the isolation region can be defined by etching or ion implantation. Figure 5 The isolation trench structure shown.

[0087] S304 : Growing a second source electrode and a second drain electrode in a second source position region and a second drain position region on the second semiconductor base structure layer, respectively.

[0088] In this embodiment, when the integrated semiconductor basic structure layer includes a P-GaN base layer, as Figure 6 As shown, the other P-GaN base layers outside the second gate position region can be removed by photolithography and etching processes to form a gate cap layer, and then the second source electrode and the second drain electrode are grown in the second source position region and the second drain position region on the AlGaN barrier layer respectively.

[0089] S305: etching the semiconductor drift structure layer to form a drain step in the drain growth region of the semiconductor drift structure layer.

[0090] In this embodiment, the drain step runs through the entire semiconductor drift structure layer, that is, the bottom surface of the drain step is the integrated semiconductor base layer. Therefore, in practical applications, this step can be implemented simultaneously with the above step S302.

[0091] S306: etching the semiconductor drift structure layer to form a gate groove in the first gate position region of the semiconductor drift structure layer; the gate groove extends to the P-GaN drift layer.

[0092] In specific implementation, a hard mask or photoresist may be used to define the gate groove region, and then an etching process or the like may be used to penetrate and form the P +-GaN drift layer, N-GaN base layer and gate trench of part of P-GaN drift layer.

[0093] In this embodiment, in order to reduce the surface state of the device finally prepared, before implementing step S306, a step S311 may be implemented:

[0094] S311: growing a passivation layer on the first surface of the fabricated device.

[0095] At this time, when the etching in step S306 is performed, the passivation layer in the gate groove area will also be removed at the same time; at this time, the device structure prepared is as follows Figure 7 shown.

[0096] S307: growing a gate oxide layer in the gate trench.

[0097] In a specific implementation, when the oxide is grown, the entire first surface is covered. After that, all the oxides except the oxide in the gate groove can be etched away to form a gate oxide layer deposited only on the bottom and sidewalls of the gate groove; or only the gate oxides in the second source position region and the second drain position region can be etched away (when the preparation process also includes the above-mentioned step S311, this etching step also removes the passivation layer in the first source position region and the first drain position region at the same time), so that the formed gate oxide layer is not only deposited on the bottom and sidewalls of the gate groove, but also covers the epitaxial region, and the epitaxial region includes P + -Other regions on the GaN drift layer except the first source region, the sidewalls of the drain step and the region at the bottom of the drain step except the first drain region, the bottom and sidewalls of the isolation trench, and the first surface of the N-FET device region; so that the gate oxide layer can passivate the leakage path of the exposed pnp junction and reduce the interface state while reducing the gate leakage (the device structure diagrams before and after etching and removing the first source region and the first drain region are shown in FIG. Figure 8 and Fig. 9 shown).

[0098] S308: growing a first drain electrode at the bottom of the drain step, and growing a first source electrode in a first source position region on the semiconductor drift structure layer.

[0099] S309: growing a first gate electrode on the gate oxide layer, and growing a second gate electrode in a second gate position region on the second semiconductor base structure layer.

[0100] In a specific implementation, when the above-mentioned passivation layer is present and the gate oxide layer also covers the epitaxial region, before growing the second gate electrode, it is necessary to etch and remove the passivation layer and the gate oxide layer in the corresponding position region; at the same time, in order to facilitate electrical connection of the finally prepared device, it is also necessary to etch and remove the passivation layer and the insulating layer on the second source electrode and the second drain electrode; that is, Figure 2 and Fig.10 As shown, the epitaxial region finally covered by the gate oxide layer includes P + -Other areas on the GaN drift layer except the first source position area, the side walls of the drain step and the areas on the bottom of the drain step except the first drain position area, the bottom and side walls of the isolation trench, and other areas on the second semiconductor basic structure layer except the second source position area, the second drain position area and the second gate position area.

[0101] In this embodiment, the first source electrode, the first drain electrode, the first gate electrode and the second gate electrode may all be film electrodes. Then, when the passivation layer and the gate oxide layer cover the epitaxial region, the first source electrode, the first drain electrode, the first gate electrode and the second gate electrode may all be film electrodes. Figure 2 In the groove electrode shown in the figure, both sides of the groove top of the groove electrode extend onto the gate oxide layer; at the same time, in order to facilitate electrical connection, a groove-shaped metal layer can be provided on the second source electrode and the second drain electrode.

[0102] S310: electrically connecting the second drain electrode to the first drain electrode, and electrically connecting the second gate electrode to the first gate electrode.

[0103] When implementing it, Figure 2 As shown, in order to facilitate the electrical connection between the second drain electrode and the first drain electrode, the second drain electrode and the first drain electrode may be arranged adjacent to each other, so that the electrical connection between the second drain electrode and the first drain electrode may be achieved by directly growing metal between the two.

[0104] Of course, if the second drain electrode and the first drain electrode are not arranged adjacent to each other in actual application, the electrical connection between the second drain electrode and the first drain electrode, and the electrical connection between the second gate electrode and the first gate electrode can be achieved by other electrical connection methods such as metal wire connection.

[0105] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. However, the obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A quasi-vertical P-FET device, characterized in that: include: A first substrate and a first semiconductor base structure layer and a semiconductor drift structure layer sequentially disposed on the first substrate; forming a two-dimensional hole gas in the first semiconductor basic structure layer; The semiconductor drift structure layer includes a P-GaN drift layer, an N-GaN base layer and a P-GaN layer sequentially arranged on the first semiconductor base structure layer. + -GaN drift layer; a drain step is provided in the drain growth region of the semiconductor drift structure layer, and the drain step runs through the entire semiconductor drift structure layer; a gate groove is provided in the first gate position region of the semiconductor drift structure layer, and the gate groove extends to the P-GaN drift layer; A first drain electrode is disposed at the bottom of the drain step and is spaced apart from the semiconductor drift structure layer; A gate oxide layer and a first gate electrode are sequentially arranged on the bottom and sidewall of the gate groove; A first source electrode is provided on the P + -GaN drift layer.

2. The quasi-vertical P-FET device according to claim 1, characterized in that: The first semiconductor basic structure layer includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-GaN base layer which are sequentially arranged on the substrate, and the two-dimensional hole gas is formed between the P-GaN base layer and the AlGaN barrier layer.

3. The quasi-vertical P-FET device according to claim 1 or 2, characterized in that: The gate oxide layer also covers the epitaxial region, and the epitaxial region includes the P + - other regions on the GaN drift layer except the first source location region, the sidewall of the drain step and the region on the bottom of the drain step except the first drain location region.

4. The quasi-vertical P-FET device according to claim 3, characterized in that: Also includes: A passivation layer is arranged on the epitaxial region; and the gate oxide layer of the epitaxial region is arranged on the passivation layer.

5. An integrated inverter, characterized in that: include: An N-FET device and a quasi-vertical P-FET device according to any one of claims 1 to 4; The N-FET device comprises: A second substrate and a second semiconductor basic structure layer arranged on the second substrate, wherein two-dimensional hole gas is formed in the second semiconductor basic structure layer; the second substrate and the first substrate are the same integrated substrate, the second semiconductor basic structure layer and the first semiconductor basic structure layer are formed in an N-FET region and a P-FET region of the same integrated semiconductor basic structure layer, and an isolation groove for cutting off the two-dimensional hole gas is formed between the N-FET region and the P-FET region; A second source electrode, a second drain electrode and a second gate electrode are all disposed on the second semiconductor basic structure layer, and the second gate electrode is located between the second source electrode and the second drain electrode; The second drain electrode is electrically connected to the first drain electrode, and the second gate electrode is electrically connected to the first gate electrode.

6. The integrated inverter according to claim 5, characterized in that: The epitaxial region also includes a bottom and sidewalls of the isolation trench, and other regions on the second semiconductor base structure layer except the second source location region, the second drain location region, and the second gate location region.

7. The integrated inverter according to claim 5, characterized in that: When the first semiconductor basic structure layer includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-GaN base layer which are sequentially arranged on the substrate, the second semiconductor basic structure layer and the first semiconductor basic structure layer are formed in the N-FET region and the P-FET region of the same integrated semiconductor basic structure layer, and an isolation groove for cutting off the two-dimensional hole gas is formed between the N-FET region and the P-FET region, and the P-GaN base layer of the N-FET region except the gate position region is removed.

8. A method for preparing an integrated inverter, characterized in that: The steps include: An integrated semiconductor basic structure layer and a semiconductor drift structure layer are sequentially grown on an integrated substrate; a two-dimensional hole gas is formed in the integrated semiconductor basic structure layer; the semiconductor drift structure layer comprises a P-GaN drift layer, an N-GaN base layer and a P-GaN layer sequentially arranged on the first semiconductor basic structure layer. + -GaN drift layer; Etching and removing the semiconductor drift structure layer in other regions except the P-FET region; Etching the integrated semiconductor basic structure layer to form an isolation groove that cuts off the two-dimensional hole gas between the N-FET region and the P-FET region of the integrated semiconductor basic structure layer; The integrated semiconductor infrastructure layers of the N-FET region and the P-FET region are respectively a first semiconductor infrastructure layer and a second semiconductor infrastructure layer; Growing a second source electrode and a second drain electrode in a second source position region and a second drain position region on the second semiconductor base structure layer, respectively; Etching the semiconductor drift structure layer to form a drain step in the drain growth region of the semiconductor drift structure layer; the drain step runs through the entire semiconductor drift structure layer; Etching the semiconductor drift structure layer to form a gate groove in a first gate position region of the semiconductor drift structure layer; the gate groove extends to the P-GaN drift layer; growing a gate oxide layer in the gate groove; Growing a first drain electrode at the bottom of the drain step, and growing a first source electrode in a first source position region on the semiconductor drift structure layer; Growing a first gate electrode on the gate oxide layer, and growing a second gate electrode in a second gate position region on the second semiconductor base structure layer; The second drain electrode is electrically connected to the first drain electrode, and the second gate electrode is electrically connected to the first gate electrode.

9. The method for preparing an integrated inverter according to claim 8, characterized in that: Before the step of etching the semiconductor drift structure layer to form a gate groove in the first gate position region of the semiconductor drift structure layer, the step further includes: A passivation layer is grown on the first surface of the fabricated device.

Images