Level shifter, power supply circuit, display driving chip and electronic equipment

Abstract

The invention provides a level shifter, a power supply circuit, a display driving chip and electronic equipment. The level shifter comprises a first switch tube, a second switch tube, a first anti-phase unit, a second anti-phase unit and a first pull-up unit, and the first pull-up unit is connected between the output end of the first anti-phase unit and a first direct-current power supply. The first pull-up unit is used for enabling the value of the current flowing through the first pull-up unit to be larger than the value of the current flowing through the first switching tube when a first clock signal input by the first input end of the level converter is suddenly changed from a high level signal to a low level signal and a second clock signal input by the second input end of the level converter is the low level signal. According to the invention, the circuit reliability can be improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a level converter, a power supply circuit, a display driver chip and an electronic device. Background Art

[0002] Level converter (also known as voltage converter or level shifter) (Level Shifter, LS) is a basic circuit often used in system-on-chip (SOC) design. The function of the voltage converter is to convert the level of the input signal from one voltage domain to another voltage domain. For example, the operating voltages of devices in different voltage domains within the chip may be 0~1V, 0~3.3V, 0~7.6V, etc. When devices in different voltage domains need to communicate, the level converter can convert the signals of these devices, such as converting the operating voltage of the signal from 0~1V to 0~3.3V.

[0003] A level converter structure is as follows Figure 1 As shown, the input terminal int1 and the input terminal int2 of the level converter respectively receive two digital clock signals with opposite phases output by the digital clock circuit, and the output terminal out1 and the output terminal out2 of the level converter can output signals to the subsequent circuit. When the digital clock signal received by the input terminal int1 suddenly changes from a high level to a low level due to power failure of the power supply VDD2, T5 changes from an on state to an off state and presents a high impedance state; T3 changes from an off state to an on state. The digital clock signal received by the input terminal int2 remains at a low level, T6 is turned off, T4 is turned on, and the output terminal out2 outputs a high level, then T1 is also turned off and presents a high impedance state. At this time, T1 and T5 form a voltage division branch due to the high impedance state, which can divide the voltage of VDD1, and the output terminal out1 outputs a half-high level. The voltage difference between the output terminal out1 and VDD1 can turn on T2, and the subsequent output terminal out2 outputs a high level, and the output terminal out1 outputs a half-high level. The half-high level output by the output terminal out1 is input to the subsequent circuit, which may reduce the reliability of the circuit. For example, when the signal output from the output terminal out1 is used to control the two switch tubes (a and b) in the subsequent circuit to turn off or on, the half-high level may cause the two switch tubes to be turned on at the same time, and the power supply connected to the switch tube a will be connected to the ground through the two switch tubes, and overcurrent will appear in the circuit, causing the switch tube to burn out. Summary of the invention

[0004] The present application provides a level converter, a power supply circuit, a display driver chip and an electronic device, which can improve circuit reliability.

[0005] In a first aspect, the present application provides a level converter, which includes a first switch tube, a second switch tube, a first inverting unit, a second inverting unit and a first pull-up unit, wherein: a first end of the first switch tube is connected to a first DC power supply, a second end of the first switch tube is connected to a reference ground through the first inverting unit, and a control end of the first switch tube is connected to an output end of the second inverting unit; a first end of the second switch tube is connected to the first DC power supply, a second end of the second switch tube is connected to the reference ground through the second inverting unit, and a control end of the second switch tube is connected to an output end of the first inverting unit; an input end of the first inverting unit and an input end of the second inverting unit are respectively connected to a first input end and a second input end of the level converter, and an output end of the first inverting unit and an output end of the second inverting unit are respectively connected to an output end of the level converter; the first pull-up unit is connected between the output end of the first inverting unit and the first DC power supply, and the first pull-up unit is used for, when a first clock signal input to the first input end of the level converter suddenly changes from a high level signal to a low level signal and a second clock signal input to the second input end of the level converter is a low level signal, a current value flowing through the first pull-up unit is greater than a current value flowing through the first switch tube. Here, the first switch tube M1 and the second switch tube M2 can be P-type metal oxide semiconductor (PMOS) field effect transistors, referred to as PMOS tubes, and accordingly, the first end of the first switch tube and the second switch tube can be the source of the PMOS tube, the second end of the first switch tube and the second switch tube can be the drain of the PMOS tube, and the control end of the first switch tube and the second switch tube can be the gate of the PMOS tube. Here, the first clock signal and the second clock signal are both clock signals, and the clock signal is a periodic pulse signal, which includes a high-level signal and a low-level signal.

[0006] In the present application, when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal, the current value flowing through the first pull-up unit is greater than the current value flowing through the first switch tube, so that the voltage at the output end of the first inverting unit can be pulled up by the first pull-up unit to the voltage of the first DC power supply, so that a high level can be output, which solves the problem of outputting a half-high level, reduces the possibility of damage to the switch tube in the subsequent circuit connected to the level converter, and improves the circuit reliability and safety.

[0007] In combination with the first aspect, in a first possible implementation, when the first clock signal is a high-level signal and the second clock signal is a low-level signal, the voltage of the first pull-up unit is equal to the voltage of the first DC power supply; the first pull-up unit is used to be in a short-circuit state when the first clock signal is a low-level signal and the second clock signal is a high-level signal. In this way, when the first clock signal or the second clock signal does not suddenly change from a high-level signal to a low-level signal, the level converter works normally, and by setting the component parameters of the first pull-up unit, the power consumption of the first pull-up unit can be ignored, and the additional energy consumption is very small, which does not affect the working efficiency of the level converter.

[0008] In combination with the first aspect to any one of the first possible implementations of the first aspect, in a second possible implementation, the first pull-up unit includes a first resistor. In this way, using the first resistor as the first pull-up unit can make the output end of the level converter output a high level, solve the problem of outputting a half-high level, improve circuit reliability and safety, use a resistor to solve the problem, the circuit structure is simple, easy to implement, and low cost.

[0009] In combination with any one of the first possible implementations of the first aspect to the first aspect, in a third possible implementation, the first pull-up unit includes a third switch tube, the first end of the third switch tube is connected to the first DC power supply, and the control end of the third switch tube and the second end of the third switch tube are both connected to the output end of the first inverting unit. In this way, the output end of the level converter outputs a high level by using the third switch tube as the first pull-up unit, which solves the problem of outputting a half-high level and improves the circuit reliability and safety. Compared with a general level converter that only adds one switch tube, the circuit structure is simple, easy to implement, and low in cost.

[0010] In combination with the third possible implementation manner of the first aspect, in a fourth possible implementation manner, the third switch tube is used to be in a conducting state when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal. At this time, the impedance of the third switch tube M3 is much smaller than the impedance of the first switch tube M1. By using the third switch tube, the output end of the level converter can output a high level, which solves the problem of outputting a half-high level and improves the reliability and safety of the circuit.

[0011] In combination with any one of the first aspect to the fourth possible implementation of the first aspect, in a fifth possible implementation, the level converter further includes a second pull-up unit, the second pull-up unit is connected between the first DC power supply and the output end of the second inverting unit, and the second pull-up unit is used for when the second clock signal suddenly changes from a high level signal to a low level signal and the first clock signal is a low level signal, the current value flowing through the second pull-up unit is greater than the current value flowing through the second switch tube. In this way, the existence of the second pull-up unit can make the level converter still directly output a high level when the second clock signal suddenly changes from a high level signal to a low level signal and the first clock signal is a low level signal, avoiding outputting a half-high level. In this way, the first pull-up unit and the second pull-up unit are used in the level converter, and even if the power supply for the clock signal is powered off at any moment, the output end of the level converter can be guaranteed to output a high level, thereby solving the problem of outputting a half-high level, reducing the possibility of damage to the switch tube in the subsequent circuit connected to the level converter, and improving the circuit reliability and safety.

[0012] In combination with the fifth possible implementation of the first aspect, in a sixth possible implementation, the second pull-up unit is used to be in a short-circuit state when the first clock signal is a high-level signal and the second clock signal is a low-level signal; when the first clock signal is a low-level signal and the second clock signal is a high-level signal, the voltage of the second pull-up unit is equal to the voltage of the first DC power supply. In this way, by selecting a second pull-up unit with appropriate component parameters, the power consumption of the second pull-up unit can be ignored when the level converter works normally, and the additional energy consumption is very small, which does not affect the working efficiency of the level converter, and can improve the circuit safety and reliability.

[0013] In combination with any one of the fifth possible implementation manner of the first aspect to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner, the second pull-up unit includes a second resistor. In this way, by using the second resistor as the second pull-up unit, the output end of the level converter can output a high level, which solves the problem of outputting a half-high level, improves circuit reliability and safety, and has a simple circuit structure, is easy to implement, has high applicability, and is low in cost.

[0014] In combination with any one of the fifth possible implementation of the first aspect to the sixth possible implementation of the first aspect, in an eighth possible implementation, the second pull-up unit includes a fourth switch tube, the first end of the fourth switch tube is connected to the first DC power supply, and the control end of the fourth switch tube and the second end of the fourth switch tube are both connected to the output end of the second inverting unit. In this way, by using the fourth switch tube as the second pull-up unit, the output end of the level converter can output a high level, which solves the problem of outputting a half-high level, improves the circuit reliability and safety, and has a simple circuit structure, is easy to implement, has low cost, and is highly applicable.

[0015] In combination with the eighth possible implementation of the first aspect, in a ninth possible implementation, the fourth switch tube is in a conducting state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal. At this time, the impedance of the fourth switch tube is much smaller than the impedance of the second switch tube, so that the output end of the level converter can output a high level instead of a half-high level. In this way, using the fourth switch tube as the second pull-up unit can make the output end of the level converter output a high level, solve the problem of outputting a half-high level, improve the circuit reliability and safety, and the circuit structure is simple, easy to implement, low cost, and high applicability.

[0016] In combination with any one of the first aspect to the ninth possible implementation of the first aspect, in a tenth possible implementation, the first inverting unit includes a fifth switch tube and a sixth switch tube, and the second end of the first switch tube is connected to the reference ground through the fifth switch tube and the sixth switch tube connected in series; the second end of the fifth switch tube and the second end of the sixth switch tube are both connected to the output end of the first inverting unit, and the control end of the fifth switch tube and the control end of the sixth switch tube are both connected to the input end of the first inverting unit; the second inverting unit includes a seventh switch tube and an eighth switch tube, and the second end of the second switch tube is connected to the reference ground through the seventh switch tube and the eighth switch tube connected in series; the second end of the seventh switch tube and the second end of the eighth switch tube are both connected to the output end of the second inverting unit, and the control end of the seventh switch tube and the control end of the eighth switch tube are both connected to the input end of the second inverting unit. Here, the fifth switch tube M5 and the seventh switch tube M7 can be PMOS tubes. The sixth switch tube M6 and the eighth switch tube M8 can be N-type metal oxide semiconductor (N-Metal-Oxide-Semiconductor, NMOS) field effect transistors, referred to as NMOS tubes. In this way, the first inverting unit and the second inverting unit each include two switching tubes. The first inverting unit and the second inverting unit can respectively invert the input first clock signal and the second clock signal through the action of the switching tubes they include, and work together with the first switching tube and the second switching tube to realize the level conversion function.

[0017] In the second aspect, the present application provides a power supply circuit, the power supply circuit includes a digital clock circuit, a voltage conversion circuit and a level converter as in the first aspect and any possible implementation of the first aspect, wherein the input end of the digital clock circuit is connected to the second DC power supply; the first output end and the second output end of the digital clock circuit are respectively connected to the first input end and the second input end of the level converter; the first output end and the second output end of the digital clock circuit are respectively used to output the first clock signal and the second clock signal, and the first clock signal is inverted with the second clock signal; the digital clock circuit is also used to change the first clock signal from a high level signal to a low level signal when the second DC power supply is powered off; the input end of the voltage conversion circuit is connected to the output end of the level converter. In this way, when the second DC power supply is suddenly powered off, the level converter in the power supply circuit can output a high level instead of a half-high level, thereby preventing the voltage conversion circuit from malfunctioning due to a half-high level, thereby improving the reliability and safety of the entire power supply circuit.

[0018] In combination with the second aspect, in a first possible implementation manner, the voltage conversion circuit includes a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube, a first capacitor and a second capacitor, and the input end of the voltage conversion circuit includes a first input end and a second input end, wherein: the second end of the ninth switch tube is connected to the first end of the tenth switch tube through the first capacitor, the first end of the ninth switch tube is connected to the first DC power supply, and the second end of the tenth switch tube is connected to a reference ground; the second end of the eleventh switch tube is connected to the second end of the twelfth switch tube through the first capacitor, the first end of the eleventh switch tube is connected to the reference ground, and the first end of the twelfth switch tube is connected to the output end of the voltage conversion circuit; the second capacitor is connected to the voltage between the output end of the conversion circuit and the reference ground; the first input end of the voltage conversion circuit is connected to the control end of the ninth switch tube, the control end of the eleventh switch tube and the control end of the twelfth switch tube; the second input end of the voltage conversion circuit is connected to the control end of the tenth switch tube; the first input end and the second input end of the voltage conversion circuit are respectively connected to the output end of the first inverting unit and the output end of the second inverting unit; the ninth switch tube is used to be in the off state when the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal; the eleventh switch tube is used to be in the on state when the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal. Here, the voltage conversion circuit can be a charge pump circuit. It can be understood that the ninth switch tube can be a PMOS tube, and the tenth switch tube, the eleventh switch tube and the twelfth switch tube can be NMOS tubes. In the present application, when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal, the ninth switch tube and the eleventh switch tube are not both turned on, so the first DC power supply will not be short-circuited by the ninth switch tube and the eleventh switch tube and directly connected to the reference ground, avoiding the occurrence of large short-circuit current in the voltage conversion circuit, thereby solving the problem of damage to the ninth switch tube and the eleventh switch tube due to the occurrence of a half-high level, and improving the safety and reliability of the power supply circuit.

[0019] In combination with the first possible implementation of the second aspect, in a second possible implementation, the tenth switch tube is used to be in a conducting state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal. In this way, when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal, the ninth switch tube and the eleventh switch tube are not both turned on at this time, avoiding a short-circuit large current in the voltage conversion circuit, and the tenth switch tube is also turned on normally, solving the problem of outputting a half-high level, and improving the safety and reliability of the power supply circuit.

[0020] In combination with the second aspect, in a third possible implementation, the voltage conversion circuit includes a ninth switch tube and a tenth switch tube, and the input end of the voltage conversion circuit includes a first input end, wherein: the second end of the ninth switch tube is connected to the reference ground through the tenth switch tube, and the first end of the ninth switch tube is connected to the first DC power supply; the first input end of the voltage conversion circuit is connected to the control end of the ninth switch tube and the control end of the tenth switch tube; the first input end of the voltage conversion circuit is connected to the output end of the first inverting unit; the ninth switch tube is used to be in an off state when the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal; the tenth switch tube is used to be in an on state when the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal. At this time, the voltage conversion circuit can actually be an inverter. The ninth switch tube can be a PMOS tube, and the tenth switch tube can be an NMOS tube. In the present application, when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal, the ninth switch tube and the tenth switch tube M are not turned on at the same time, thereby avoiding the problem that both switch tubes are turned on, resulting in a short-circuit and large current in the circuit causing damage to the switch tubes, reducing the risk of damage to the switch tube in the voltage conversion circuit due to the level converter outputting a half-high level, improving the circuit reliability and safety, and increasing the service life of the device.

[0021] In combination with the third possible implementation of the second aspect, in a fourth possible implementation, the voltage conversion circuit further includes an eleventh switch tube and a twelfth switch tube, and the input end of the voltage conversion circuit further includes a second input end, wherein: the second end of the eleventh switch tube is connected to the reference ground through the twelfth switch tube, and the first end of the eleventh switch tube is connected to the first DC power supply; the second input end of the voltage conversion circuit is connected to the control end of the eleventh switch tube and the control end of the twelfth switch tube; the second input end of the voltage conversion circuit is connected to the output end of the second inverting unit; the eleventh switch tube is used to be in an off state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal; the twelfth switch tube is used to be in an on state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal. In this way, when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal, the ninth switch tube and the tenth switch tube are not both turned on at the same time. If the second DC power supply loses power at any moment, it can avoid the situation where both switching tubes in the same inverter of the voltage conversion circuit are turned on, thereby reducing the risk of damage to the switching tube in the voltage conversion circuit due to the level converter outputting a half-high level, improving the circuit reliability and safety, and increasing the service life of the device.

[0022] In the third aspect, the present application provides a display driver chip, which includes a linear regulator and any power supply circuit as in the second aspect to the second possible implementation of the second aspect, the linear regulator is connected to the voltage conversion circuit in the power supply circuit, and the linear regulator is used to keep the voltage output by the voltage conversion circuit within the target voltage range. In the display driver chip, the voltage conversion circuit in the power supply circuit can be a charge pump circuit. Since the level converter in the power supply circuit can still output a high level instead of a half-high level when the power supply of the digital clock circuit is powered off, the switch tube in the voltage conversion circuit will not be damaged due to the half-high level, and the safety and reliability of the entire power supply circuit are greatly improved, so that the display driver chip will not work abnormally due to the problem of the half-high level, thereby improving the working stability of the chip.

[0023] In a fourth aspect, the present application provides an input I / output O buffer circuit, the input / output buffer circuit including an electrostatic protection ESD circuit and any power supply circuit as in the second aspect, the third possible implementation of the second aspect to the fourth possible implementation of the second aspect. The electrostatic protection circuit is connected to the power supply circuit, and the electrostatic protection circuit is used to provide an electrostatic discharge path for the power supply circuit. Since the level converter in the power supply circuit still outputs a high level instead of a half-high level when the power supply of the digital clock circuit is powered off, the switch tube in the voltage conversion circuit will not be damaged due to the half-high level, and the safety and reliability of the entire power supply circuit are greatly improved. Therefore, the input / output buffer circuit will not work abnormally due to the problem of the half-high level, thereby improving the circuit stability.

[0024] In a fifth aspect, the present application provides an electronic device, the electronic device comprising a display screen and a display driver chip as in the third aspect, the display screen in the electronic device being connected to the display driver chip, and the display screen being used for displaying based on the drive of the display driver chip. The electronic device may be a communication device, a computer, a notebook, a mobile phone, a tablet computer, or other device, in which the level converter in the display driver chip still outputs a high level instead of a half-high level under abnormal conditions, which can reduce the risk of damage to the switch tube, so that the display driver chip can work normally, thereby enabling the display screen to display normally, reducing the risk of display screen failure (such as green screen flashing, flower screen flashing, etc.), and improving the reliability and working performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of a level converter;

[0026] Figure 2 A schematic diagram of a level converter provided by the present application;

[0027] Figure 3 A timing diagram of a first clock signal provided in the present application changing from a high-level signal to a low-level signal;

[0028] Figure 4 A timing diagram of a second clock signal provided in the present application changing from a high-level signal to a low-level signal;

[0029] Figure 5 Another schematic diagram of the structure of the level converter provided by the present application;

[0030] Figure 6 Another structural schematic diagram of the level converter provided by the present application;

[0031] Figure 7 Another structural schematic diagram of the level converter provided by the present application;

[0032] Figure 8 Another structural schematic diagram of the level converter provided by the present application;

[0033] Fig. 9 Another structural schematic diagram of the level converter provided by the present application;

[0034] Fig.10 Another structural schematic diagram of the level converter provided by the present application;

[0035] Fig.11 Another structural schematic diagram of the level converter provided by the present application;

[0036] Fig.12 A schematic diagram of a power supply circuit provided in this application;

[0037] Fig.13 Another structural schematic diagram of the power supply circuit provided by this application;

[0038] Fig.14 Another structural schematic diagram of the power supply circuit provided in this application;

[0039] Fig.15 Another structural schematic diagram of the power supply circuit provided in this application;

[0040] Fig.16 A schematic diagram of the structure of the display driver chip provided in this application;

[0041] Fig.17 A schematic diagram of a structure of an input / output buffer circuit provided by the present application;

[0042] Fig.18 A schematic diagram of the structure of an electronic device provided in this application. DETAILED DESCRIPTION

[0043] The level converter, power supply circuit and display driver chip provided in this application can be applied to various application fields such as digital circuit field, chip field, terminal field, communication field, etc. The level converter can be applied to the power supply circuit provided in this application, the power supply circuit can be the internal drive circuit of the display driver chip, and the display driver chip can be applied to electronic devices such as communication equipment, computers, mobile phones, audio equipment, etc. The power supply circuit provided in this application can be applied to different application scenarios, such as display drive scenarios, input and output buffer scenarios of digital integrated circuits, etc.

[0044] Combine the following Figure 2-Figure 11 The level converter provided in the present application and its working principle are exemplarily described.

[0045] See also Figure 2 ,like Figure 2As shown, the level converter includes a first switch tube M1, a second switch tube M2, a first inverting unit A1, a second inverting unit A2 and a first pull-up unit P1. Among them, the first end of the first switch tube M1 is connected to the first DC power supply V1, the second end of the first switch tube M1 is connected to the reference ground through the first inverting unit A1, and the control end of the first switch tube M1 is connected to the output end out2 of the second inverting unit A2. The first end of the second switch tube M2 is connected to the first DC power supply V1, the second end of the second switch tube M2 is connected to the reference ground through the second inverting unit, and the control end of the second switch tube M2 is connected to the output end out1 of the first inverting unit A1. Here, the first switch tube M1 and the second switch tube M2 can be P-type metal oxide semiconductor (PMOS) field effect transistors, referred to as PMOS tubes, and accordingly, the first end of the first switch tube and the second switch tube can be the source of the PMOS tube, the second end of the first switch tube and the second switch tube can be the drain of the PMOS tube, and the control end of the first switch tube and the second switch tube can be the gate of the PMOS tube. The PMOS tube can be turned on when its source voltage is greater than the gate voltage. In other words, the PMOS tube can be turned on when a low-level signal is input to its gate. Figure 2 As shown, the input terminal int1 of the first inverting unit and the input terminal int2 of the second inverting unit are respectively connected to the first input terminal and the second input terminal of the level converter, and the output terminal out1 of the first inverting unit and the output terminal out2 of the second inverting unit are respectively connected to the output terminal of the level converter. In other words, the level converter has two input terminals and two output terminals, and the input terminal of the level converter is the input terminal of the first inverting unit and the input terminal of the second inverting unit, and the output terminal of the level converter is the output terminal of the first inverting unit and the output terminal of the second inverting unit.

[0046] In a feasible implementation, the first pull-up unit P1 can be connected between the output terminal out1 of the first inverting unit A1 and the first DC power supply. The first input terminal int1 and the second input terminal int2 of the level converter are used to input the first clock signal and the second clock signal, respectively. Here, the first clock signal and the second clock signal are both clock signals, and the clock signal is a periodic pulse signal, which includes a high-level signal and a low-level signal. Under normal circumstances, the clock signal can be a square wave, that is, the high-level signal and the low-level signal appear at regular intervals. The first clock signal is in antiphase with the second clock signal. Under normal circumstances, the timing of the first clock signal and the second clock signal is as follows: Figure 3 (a) and Figure 4As shown in (a) in the figure. In an abnormal situation, such as when the power supply for the clock signal is powered off, the clock signal may suddenly change from a high-level signal to a low-level signal and remain at a low-level signal before the abnormality is restored. Here, the sudden change of the clock signal from a high-level signal to a low-level signal does not include the normal transition process of a high-level signal to a low-level signal, but refers to the sudden change of the clock signal from a high-level signal to a low-level signal during the period when the clock signal should remain at a high-level signal. For example, Figure 3 As shown in (b) in FIG. 1 , under abnormal conditions, the first clock signal may suddenly change from a high-level signal to a low-level signal at time t1. If the abnormality is not restored before time t4, the first clock signal will continue to remain a low-level signal before time t4. During this process, the second clock signal will continue to remain a low-level signal. For example, Figure 4 As shown in (c), under abnormal circumstances, the second clock signal may suddenly change from a high-level signal to a low-level signal at time t2. If the abnormality is not restored before time t4, the second clock signal will continue to remain a low-level signal before time t4. During this process, the first clock signal will continue to remain a low-level signal. It is understandable that under abnormal circumstances, the first clock signal (the second clock signal) suddenly changes from a high-level signal to a low-level signal, and this process may also occur at any time within the range of time t1 to time t3 (time t2 to time t3), and this application does not limit this. Figure 3 (b) and Figure 4 (c) is only an example. When the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal, if the level converter does not include the first pull-up unit, such as Figure 1 As shown, the output end of the level converter easily generates a half-high level; if the level converter includes a first pull-up unit P1, such as Figure 2As shown, the current value flowing through the first pull-up unit P1 is greater than the current value flowing through the first switch tube M1. At this time, the impedance of the first pull-up unit P1 can be understood to be much smaller than the impedance presented by the first switch tube M1. Between the first DC power supply V1 and the reference ground, the current mainly passes through the first pull-up unit P1 (rather than the first switch tube M1) and the switch tube connected between the reference ground and the output end out1 in the first inverting unit A1. At this time, the impedance of the first pull-up unit P1 is also much smaller than the impedance presented by the switch tube connected between the reference ground and the output end out1 in the first inverting unit. Therefore, the voltage of the output end out1 of the first inverting unit A1 is close to the voltage of the first DC power supply V1, so that the output end out1 of the level converter no longer outputs a half-high level, but outputs a high level. That is to say, when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal, the current value flowing through the first pull-up unit is greater than the current value flowing through the first switch tube, so that the voltage at the output end of the first inverting unit can be pulled up by the first pull-up unit to the voltage of the first DC power supply, so that a high level can be output, which solves the problem of outputting a half-high level, reduces the possibility of damage to the switch tube in the subsequent circuit connected to the level converter, and improves the circuit reliability and safety.

[0047] Please also see Figure 5 , Figure 5 Another structural diagram of the level converter provided by this application. Figure 5 As shown, in Figure 2 The first inverting unit A1 shown may include a fifth switch tube M5 and a sixth switch tube M6, and the second end of the first switch tube M1 is connected to the reference ground through the fifth switch tube M5 and the sixth switch tube M6 connected in series. The second end of the fifth switch tube M5 and the second end of the sixth switch tube M6 are both connected to the output end out1 of the first inverting unit A1, and the control end of the fifth switch tube M5 and the control end of the sixth switch tube M6 are both connected to the input end int1 of the first inverting unit A1. The structure of the second inverting unit A2 is similar to that of the first inverting unit A1. Figure 5 As shown, in Figure 2 The second inverting unit A2 shown may include a seventh switch tube M7 and an eighth switch tube M8, and the second end of the second switch tube M2 is connected to the reference ground through the seventh switch tube M7 and the eighth switch tube M8 connected in series. The second end of the seventh switch tube M7 and the second end of the eighth switch tube M8 are both connected to the output end out2 of the second inverting unit A2, and the control end of the seventh switch tube M7 and the control end of the eighth switch tube M8 are both connected to the input end int1 of the second inverting unit A2.

[0048] Here, the fifth switch tube M5 and the seventh switch tube M7 can be PMOS tubes. The sixth switch tube M6 and the eighth switch tube M8 can be N-type metal oxide semiconductor (N-Metal-Oxide-Semiconductor, NMOS) field effect transistors, referred to as NMOS tubes. In the present application, whether the switch tube is a PMOS tube or an NMOS tube, the first end of the switch tube refers to the source of the switch tube, the second end refers to the drain of the switch tube, and the control end refers to the gate of the switch tube. The NMOS tube can be turned on when its source voltage is less than the gate voltage. In other words, the NMOS tube can be turned on when a high-level signal is input to its gate. That is to say, the first inverting unit and the second inverting unit each include two switch tubes, and the first inverting unit and the second inverting unit can respectively invert the input first clock signal and the second clock signal through the action of the switch tubes they include, and work together with the first switch tube and the second switch tube to realize the level conversion function. It can be understood that Figure 5 M5, M6 and M1 in can correspond to Figure 1 T3, T5 and T1 in Figure 5 M7, M8 and M2 correspond to Figure 1 T4, T6 and T2, Figure 5 V1 in Figure 1 VDD1 in.

[0049] In some feasible implementations, when the first clock signal is a high level signal and the second clock signal is a low level signal, the voltage of the first pull-up unit P1 is equal to the voltage of the first DC power supply V1. Figure 5As shown, at this time, because the input terminal int1 of the first inverting unit inputs a high-level signal, the sixth switch tube M6 is turned on, the fifth switch tube M5 is turned off, and is in a high-impedance state, the output terminal out1 of the first inverting unit is connected to the reference ground through the sixth switch tube M6, the output terminal out1 of the first inverting unit outputs a low-level signal, and the voltage on the first pull-up unit P1 is substantially equal to the voltage of the first DC power supply V1. It can be understood that by selecting a first pull-up unit with appropriate component parameters, the current I1 flowing through the first pull-up unit can be made smaller at this time, and the power W1 consumed by the first pull-up unit (calculated based on the formula W1=V1*I1) can be made smaller, thereby ensuring that the power consumption of the first pull-up unit can be ignored. On the other hand, at this time, because the input terminal int2 of the second inverting unit inputs a low-level signal, the eighth switch tube M8 is turned off, and is in a high-impedance state, and the seventh switch tube M7 is turned on. The second switch tube M2 is also turned on, so the voltage of the output end out2 of the second inverting unit is pulled up to the voltage of the first DC power supply V1 by the second switch tube M2 and the seventh switch tube M7, and the output end of the second inverting unit outputs an out2 high-level signal. In other words, when the first clock signal is a high-level signal and the second clock signal is a low-level signal, the voltage of the first pull-up unit is equal to the voltage of the first DC power supply, and the level converter works normally. By selecting a first pull-up unit with appropriate component parameters, the power consumption of the first pull-up unit can be ignored, and the additional energy consumption is very small, which does not affect the working efficiency of the level converter.

[0050] In some feasible implementations, the first pull-up unit P1 may also be configured to be in a short-circuit state when the first clock signal is a low-level signal and the second clock signal is a high-level signal. Figure 5 As shown, at this time, because the input terminal int2 of the second inverting unit inputs a high-level signal, the eighth switch tube M8 is turned on, the output terminal out2 of the second inverting unit is connected to the reference ground through the eighth switch tube M8, and the output terminal out2 of the second inverting unit outputs a low-level signal. The first switch tube M1 is turned on. At this time, the input terminal int1 of the first inverting unit inputs a low-level signal, so the fifth switch tube M5 is also turned on, the sixth switch tube is turned off and is in a high-impedance state, and the first pull-up unit P1 is equivalent to the first switch tube M1 and the fifth switch tube M5 connected in series short-circuited, so the power consumption of the first pull-up unit is close to 0 and can be ignored. The output terminal out1 of the first inverting unit is connected to the first DC power supply V1 through the first switch tube M1 and the fifth switch tube M5, so the output terminal out1 of the first inverting unit outputs a high-level signal. That is to say, when the first clock signal is a low-level signal and the second clock signal is a high-level signal, the first pull-up unit is in a short-circuit state, the level converter works normally, the power consumption of the first pull-up unit is negligible, and the additional energy consumption is very small, which does not affect the working efficiency of the level converter.

[0051] Please also see Figure 6 , Figure 6 This is another structural diagram of the level converter provided by this application. Figure 6 As shown, in Figure 5 The first pull-up unit P1 shown may include a first resistor R1. At this time, the two ends of the first resistor R1 are respectively connected to the first DC power supply V1 and the output end out1 of the first inverting unit. The first resistor R1 can be used to make the current value flowing through the first resistor R1 greater than the current value flowing through the first switch tube M1 when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal. Specifically, as Figure 6 As shown, the states of the switches in the level converter are as follows: because the second clock signal is a low-level signal, the eighth switch M8 is turned off and the seventh switch M7 is turned on. The second switch M2 remains turned on at this moment, so the output end out2 of the second inverting unit outputs a high-level signal. Then, the first switch M1 is also turned off and is in a high-impedance state. Because the first clock signal suddenly changes from a high-level signal to a low-level signal at this time, the sixth switch M6 is turned off and is in a high-impedance state, and the fifth switch M5 is turned on. Since the switches are in the above state, and the current flowing through the first resistor R1 is greater than the current flowing through the first switch M1, the current between the first DC power supply V1 and the reference ground mainly flows through the first resistor R1 and the sixth switch M6. At this time, the impedance of the first resistor R1 is much smaller than the impedance of the sixth switch M6. Therefore, the voltage of the output end out1 of the first inverting unit is approximately equal to the voltage of the first DC power supply V1, and the output end out1 outputs a high level. In this way, by using the first resistor as the first pull-up unit, the output ends of the level converter can all output high levels, solving the problem of outputting half-high levels, and improving circuit reliability and safety. The problem can be solved by using resistors, and the circuit structure is simple, easy to implement, and low cost.

[0052] Please also see Figure 7 , Figure 7 This is another structural diagram of the level converter provided by this application. Figure 7 As shown, in Figure 5The first pull-up unit P1 shown may include a third switch tube M3, a first end of the third switch tube M3 is connected to the first DC power supply V1, and a control end of the third switch tube M3 and a second end of the third switch tube M3 are both connected to the output end out1 of the first inverting unit. In some feasible embodiments, the third switch tube M3 may be a PMOS tube, a first end of the third switch tube M3 is a source, a second end is a drain, and a control end is a gate. The third switch tube M3 is used to be in a conducting state when the above-mentioned first clock signal suddenly changes from a high-level signal to a low-level signal and the above-mentioned second clock signal is a low-level signal. At this time, the impedance of the third switch tube M3 is much smaller than the impedance of the first switch tube M1. At this time, Figure 7 The states of the other switch tubes except the third switch tube M3 in the level converter are shown in FIG. Figure 6 The states of the switches in the level converter shown are the same, please refer to the relevant description above for details, and will not be repeated here. When each switch is in this state, and the current value flowing through the third switch is greater than the current value flowing through the first switch, then the current between the first DC power supply V1 and the reference ground mainly flows through the third switch M3 and the sixth switch M6. Therefore, the voltage at the output terminal out1 of the first inverting unit is approximately equal to the voltage of the first DC power supply V1, and the output terminal out1 outputs a high level. In this way, the third switch is used as the first pull-up unit, and the output terminals of the level converter all output a high level, which solves the problem of outputting a half-high level and improves the circuit reliability and safety. Compared Figure 1 The level converter shown has only one switch tube added, and has a simple circuit structure, is easy to implement, and has low cost.

[0053] Please also see Figure 8 , Figure 8 This is another structural diagram of the level converter provided by this application. Figure 8 As shown, Figure 2 Compared to the level converter shown, Figure 8The level converter shown also includes a second pull-up unit P2. The second pull-up unit is connected between the first DC power supply V1 and the output end out2 of the second inverting unit. The second pull-up unit P2 is used for when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal, the current value flowing through the second pull-up unit P2 is greater than the current value flowing through the second switch tube M2. At this time, the impedance of the second pull-up unit P2 can be understood as being much smaller than the impedance of the second switch tube M2. Between the first DC power supply V1 and the reference ground, the current mainly passes through the second pull-up unit P2 (rather than the second switch tube M2) and the switch tube connected between the reference ground and the output end out2 in the second inverting unit A2. At this time, the impedance of the second pull-up unit P2 is also much smaller than the impedance of the switch tube connected between the reference ground and the output end out2 in the second inverting unit. Therefore, the voltage of the output end out2 of the second inverting unit A2 is close to the voltage of the first DC power supply V1, so that the output end out2 of the level converter no longer outputs a half-high level, but outputs a high level. That is to say, the level converter includes a first pull-up unit and a second pull-up unit. When the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal, the current value flowing through the second pull-up unit is greater than the current value flowing through the second switch tube, so that the voltage at the output end of the second inverting unit is pulled up by the second pull-up unit to the voltage of the first DC power supply, thereby directly outputting a high level and avoiding outputting a half-high level; when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal, the current value flowing through the first pull-up unit is greater than the current value flowing through the first switch tube, so that the voltage at the output end of the first inverting unit is pulled up by the first pull-up unit to the voltage of the first DC power supply, thereby directly outputting a high level and avoiding outputting a half-high level. In this way, when the power supply for the clock signal is powered off at any moment, the output end of the level converter can be guaranteed to output a high level, thereby solving the problem of outputting a half-high level, reducing the possibility of damage to the switch tube in the subsequent circuit connected to the level converter, and improving the circuit reliability and safety.

[0054] Please also see Fig. 9 , Fig. 9 This is another structural diagram of the level converter provided by this application. Fig. 9 As shown, Figure 8 Compared to the level converter shown, Fig. 9 The first inverting unit A1 in the level converter shown includes a fifth switch tube M5 and a sixth switch tube M6, and the second inverting unit A2 includes a seventh switch tube M7 and an eighth switch tube M8. The connection relationship of these switch tubes is described above and will not be repeated here. In some feasible implementations, the second pull-up unit P2 is used to be in a short-circuit state when the first clock signal is a high-level signal and the second clock signal is a low-level signal. Fig. 9 As shown, at this time, because the input end out1 of the first inverting unit inputs a high-level signal, the sixth switch tube M6 is turned on, the seventh switch tube M7 is turned off, the output end out1 of the first inverting unit is connected to the reference ground through the sixth switch tube M6, and the output end out1 of the first inverting unit outputs a low-level signal. Then the second switch tube M2 is turned on. Because the input end out2 of the second inverting unit inputs a low-level signal, at this time, the seventh switch tube M7 is also turned on, the eighth switch tube M8 is in a high-impedance state, and the second pull-up unit P2 is equivalent to the second switch tube M2 and the seventh switch tube M7 being short-circuited in series, so the power consumption of the second pull-up unit P2 is close to 0 and can be ignored. The output end out2 of the second inverting unit is connected to the first DC power supply V1 through the second switch tube M2 and the seventh switch tube M7, so the output end out1 of the second inverting unit outputs a high-level signal. That is to say, when the first clock signal is a high-level signal and the second clock signal is a low-level signal, the second pull-up unit P2 is in a short-circuit state, the level converter works normally, the power consumption of the second pull-up unit P2 is negligible, and the additional energy consumption is very small, which does not affect the normal operation of the level converter. In addition, by selecting the first pull-up unit P1 with appropriate component parameters, the power consumption of the first pull-up unit P1 can also be ignored. Therefore, the setting of the first pull-up unit P1 and the second pull-up unit P2 does not affect the working efficiency of the level converter, and can improve the circuit safety and reliability.

[0055] In some feasible implementations, when the first clock signal is a low level signal and the second clock signal is a high level signal, the voltage of the second pull-up unit P2 is equal to the voltage of the first DC power supply V1. Fig. 9As shown, at this time, because the input end out2 of the second inverting unit inputs a high-level signal, the eighth switch tube M8 is turned on, the output end out2 of the second inverting unit is connected to the reference ground through the eighth switch tube M8, and the output end out2 of the second inverting unit outputs a low-level signal. At this time, the seventh switch tube M7 and the second switch tube M2 are both in a high-impedance state, which is equivalent to the seventh switch tube M7 and the second switch tube M2 being connected in series and connected in parallel with the second pull-up unit P2, so the voltage on the second pull-up unit P2 is substantially equal to the voltage of the first DC power supply V1. It can be understood that by selecting a second pull-up unit P2 with appropriate component parameters, the current I2 flowing through the second pull-up unit P2 can be made smaller at this time, and the power W2 (calculated based on the formula W2=V1*I2) consumed by the second pull-up unit P2 can be made smaller, thereby ensuring that the power consumption of the second pull-up unit P2 can be ignored. On the other hand, at this time, because the input end out1 of the first inverting unit inputs a low-level signal, the sixth switch tube M6 is in a high-impedance state, and the fifth switch tube M5 is turned on. The first switch tube M1 is also turned on, so the voltage of the output end out1 of the first inverting unit is pulled up to the voltage of the first DC power supply V1 by the first switch tube M and the fifth switch tube M, and the output end out1 of the first inverting unit outputs a high level signal. That is to say, when the first clock signal is a high level signal and the second clock signal is a low level signal, the voltage of the second pull-up unit P2 is equal to the voltage of the first DC power supply V1, and the level converter works normally. By selecting the second pull-up unit P2 with appropriate component parameters, the power consumption of the second pull-up unit P2 can be ignored, and the additional energy consumption is very small, which does not affect the normal operation of the level converter. In addition, at this time, the first pull-up unit P1 is in a short-circuit state, and its power consumption can also be ignored. Therefore, the setting of the first pull-up unit P1 and the second pull-up unit P2 does not affect the working efficiency of the level converter, and can improve the circuit safety and reliability.

[0056] Please also see Fig.10 , Fig.10 This is another structural diagram of the level converter provided by this application. Fig.10 As shown, in Fig. 9 The second pull-up unit P2 shown may include a second resistor R2. At this time, the two ends of the second resistor R2 are respectively connected to the first DC power supply V1 and the output end out2 of the second inverting unit. The second resistor R2 can be used to make the current value flowing through the second resistor R2 greater than the current value flowing through the second switch tube M2 when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal. Specifically, as Fig. 9As shown, the states of the switches in the level converter are as follows: because the first clock signal is a low-level signal, the sixth switch M6 is turned off and the fifth switch M5 is turned on. The first switch M1 remains turned on at this moment, so the output end out1 of the first inverting unit outputs a high-level signal. Then, the second switch M2 is also turned off and is in a high-impedance state. Because the second clock signal suddenly changes from a high-level signal to a low-level signal at this time, the eighth switch M8 is turned off and is in a high-impedance state, and the seventh switch M7 is turned on. Since the switches are in the above state, and the current flowing through the second resistor R2 is greater than the current flowing through the second switch M2, the current between the first DC power supply V1 and the reference ground mainly flows through the second resistor R2 (rather than the second switch M2) and the eighth switch M8. At this time, the impedance of the second resistor R2 is much smaller than the impedance of the eighth switch M8. Therefore, the voltage of the output end out2 of the second inverting unit is approximately equal to the voltage of the first DC power supply V1, and the output end out2 outputs a high level. In this way, by using the second resistor as the second pull-up unit, the output terminals of the level converter can all output high level, thus solving the problem of outputting half high level, improving the circuit reliability and safety, and the circuit structure is simple, easy to implement, highly applicable, and low cost. Fig.10 In the example, the first pull-up unit P1 includes the first resistor R1.

[0057] Exemplarily, when the voltage of the first DC power supply V1 is 7.6V, the voltage of the high-level signal of the first clock signal and the second clock signal is 1.8V, the leakage current between the source and the drain in the off state of the switch tubes such as M1~M2, M5~M8 is about pA level, and the leakage impedance is greater than 1000MΩ, the resistance values ​​of the first resistor and the second resistor can be adjusted so that they consume less power when the level converter is working normally. In fact, the resistance values ​​of the first resistor and the second resistor can be within the range of 1MΩ to 10MΩ. It is found through measurement that a better value is 1MΩ and another better value is 2.2MΩ. When the level converter is working normally, the first resistor R1 and the second resistor R2 consume power alternately in the low-level period of the clock signal. Then, the current I1, I2 and power W1, W2 consumed by the above-mentioned first resistor and the second resistor when the level converter is working normally are:

[0058] I1=I2=V1 / R=7.6v / 2.2MΩ=3.45uA

[0059] W1=W2=7.6v*3.45uA=26.22uW

[0060] It can be seen that the power consumption increased by the first resistor and the second resistor is very low and can be almost ignored.

[0061] When designing the level converter, it can be specifically implemented in the wafer design, then adding the first resistor and / or the second resistor can be specifically implemented by polysilicon doping method or other methods, and the present application does not limit this. It can be understood that adding the first resistor and / or the second resistor in the level converter does not require additional changes to the wafer process, does not increase the cost, and is simple to implement.

[0062] Please also see Fig.11 , Fig.11 This is another structural diagram of the level converter provided by this application. Fig.11 As shown, in Fig. 9 The second pull-up unit P2 shown may include a fourth switch tube M4, a first end of the fourth switch tube M4 is connected to the first DC power supply, and a control end of the fourth switch tube M4 and a second end of the fourth switch tube M4 are both connected to the output end out2 of the second inverting unit. In some feasible implementations, the fourth switch tube M4 may be a PMOS tube, a first end of the fourth switch tube M4 is a source, a second end is a drain, and a control end is a gate. The fourth switch tube M4 is used to be in a conducting state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal, then the impedance of the fourth switch tube M4 is much smaller than the impedance of the second switch tube M2, at this time, Fig.11 The states of the other switch tubes except the fourth switch tube M4 in the level converter are shown in FIG. Fig.10 The states of the switch tubes in the level converter shown are the same, please refer to the relevant description above for details, and will not be repeated here. Each switch tube is in this state, and the current value flowing through the fourth switch tube is greater than the current value flowing through the second switch tube, then the current between the first DC power supply V1 and the reference ground mainly flows through the fourth switch tube M4 and the eighth switch tube M8, so the voltage of the output terminal out2 of the second inverting unit is approximately equal to the voltage of the first DC power supply V1, and the output terminal out2 outputs a high level. In this way, using the fourth switch tube as the second pull-up unit can make the output terminal of the level converter output a high level, solve the problem of outputting a half-high level, improve the circuit reliability and safety, and the circuit structure is simple, easy to implement, low cost, and highly applicable. It can be understood that in Fig.11 In the example, the first pull-up unit P1 includes the third switch tube M3.

[0063] Exemplarily, when the voltage of the first DC power supply V1 is 7.6V, the voltage of the high-level signal of the first clock signal and the second clock signal is 1.8V, the leakage current between the source and the drain of the switch tubes M1-M2, M5-M8, etc. is about pA level when the switch tubes are turned off, and the leakage impedance is greater than 1000MΩ, the saturation current parameters of the third switch tube and the fourth switch tube can be adjusted to the range of 2-4uA (when the source-drain voltage Vsd=7.6v). Then, the current I1, I2, power W1, W2 consumed by the third switch tube and the fourth switch tube when the level converter is working normally are:

[0064] I1=I2=2~4uA

[0065] W1=W2=7.6v*(2~4)uA=(15.2~30.4)uW

[0066] It can be seen that the power consumption increased by the third switch tube and the fourth switch tube is very low and can be almost ignored.

[0067] When designing the level converter, it can be specifically implemented in the wafer design, and then adjusting the component parameters of the third switch tube and the fourth switch tube can be specifically implemented by adjusting the channel width-to-length ratio of the third switch tube and the fourth switch tube. It can be understood that adding the third switch tube and / or the fourth switch tube to the level converter does not require additional changes to the wafer process, does not increase the cost, and is simple to implement.

[0068] In the present application, by adding a first pull-up unit P1 between the output end out1 of the level converter and the first DC power supply V1, when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal, the current value flowing through the first pull-up unit P1 is greater than the current value flowing through the first switch tube M1, so that the current can flow to the reference ground through the first DC power supply, the first pull-up unit (rather than the first switch tube), and the sixth switch tube. By selecting a first pull-up unit with appropriate component parameters, it can be ensured that the impedance of the first pull-up unit is much smaller than the impedance of the sixth switch tube at this time, so that the output end out1 of the level converter can output a high level, solve the problem of outputting a half-high level, reduce the possibility of loss of the switch tube in the subsequent circuit, and improve the reliability and safety of the circuit. In addition, a second pull-up unit P2 can be added between another output end out2 of the level converter and the first DC power supply V1, so as to ensure that when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal, the output end out2 still outputs a high level, solves the problem of outputting a half-high level, and thus greatly improves the safety of the circuit.

[0069] Combine the following Figures 12 to 15 The power supply circuit provided in this application and its working principle are introduced.

[0070] See also Fig.12 , Fig.12 This is a structural diagram of a power supply circuit provided by the present application. As shown in the figure, the power supply circuit 1 may include a digital clock circuit 11, a voltage conversion circuit 12 and a level converter 10. Here, the level converter 10 may be as follows Figure 2 , Figure 5-Figure 11 A level converter as shown in any of the diagrams. Fig.12 As shown, the input end of the digital clock circuit 11 in the power supply circuit 1 is connected to the second DC power supply V2. It can be understood that the voltage of the second DC power supply V2 is lower than the voltage of the first DC power supply V1. The first output end out111 and the second output end out112 of the digital clock circuit 11 are respectively connected to the first input end int1 and the second input end int2 of the level converter 10. The first output end out111 and the second output end out112 of the digital clock circuit 11 are respectively used to output a first clock signal and a second clock signal, and the first clock signal is inverted with the second clock signal. The digital clock circuit 11 is also used to change the first clock signal from a high level signal to a low level signal when the second DC power supply V2 is powered off, or the digital clock circuit 11 is also used to change the second clock signal from a high level signal to a low level signal when the second DC power supply V2 is powered off. The input end of the voltage conversion circuit 12 is connected to the output end of the level converter.

[0071] Please also see Fig.13 , Fig.13 Another structural diagram of the power supply circuit provided in this application. Fig.13 For example Fig.12 The voltage conversion circuit 12 in the power supply circuit 1 shown in the figure is a specific example. At this time, the voltage conversion circuit is actually a charge pump circuit. The power supply circuit can be applied to the display driving scene to convert the voltage provided by the power supply into a negative voltage to provide it to the subsequent circuit. Fig.13As shown, the voltage conversion circuit 12 includes a ninth switch tube M9, a tenth switch tube M10, an eleventh switch tube M11, a twelfth switch tube M12, a first capacitor C1 and a second capacitor C2, and the input end of the voltage conversion circuit 12 includes a first input end int121 and a second input end int122. Among them, the second end of the ninth switch tube M9 is connected to the first end of the tenth switch tube M10 through the first capacitor C1, the first end of the ninth switch tube M9 is connected to the first DC power supply V1, and the second end of the tenth switch tube M10 is connected to the reference ground. The second end of the eleventh switch tube M11 is connected to the second end of the twelfth switch tube M12 through the first capacitor C1, the first end of the eleventh switch tube M11 is connected to the reference ground, and the first end of the twelfth switch tube M12 is connected to the output end out121 of the voltage conversion circuit 12; the second capacitor C2 is connected between the output end out121 of the voltage conversion circuit and the reference ground. The first input terminal int121 of the voltage conversion circuit 12 is connected to the control terminal of the ninth switch tube M9, the control terminal of the eleventh switch tube M11, and the control terminal of the twelfth switch tube M12; the second input terminal int122 of the voltage conversion circuit 12 is connected to the control terminal of the tenth switch tube M10. The first input terminal int121 and the second input terminal int122 of the voltage conversion circuit 12 are respectively connected to the output terminal out1 of the first inverting unit and the output terminal out2 of the second inverting unit. It can be understood that the ninth switch tube can be a PMOS tube, and the tenth switch tube, the eleventh switch tube, and the twelfth switch tube can be NMOS tubes.

[0072] like Fig.13 As shown, the level converter in the power supply circuit can be as described above Figure 2 , Figure 5-Figure 11The level converter of any of the diagrams in the figure, therefore, the ninth switch tube M9 can be used to be in the off state when the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal. At this time, the output end out1 of the first inverting unit outputs a high level, and the ninth switch tube M9 is in the off state. The output end out2 of the second inverting unit also outputs a high level, and the tenth switch tube M10 is in the on state. The first DC power supply V1 cannot charge the first capacitor C1 through the ninth switch tube M9. The eleventh switch tube M11 can be used to be in the on state when the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal. At this time, the output end out1 of the first inverting unit outputs a high level, the eleventh switch tube M11 is in the on state, the twelfth switch tube M12 is also in the on state, and the first capacitor C1 can be discharged through the loop composed of the eleventh switch tube M11, the second capacitor C2 and the twelfth switch tube M12. It is understandable that the ninth switch tube M9 and the eleventh switch tube M11 are not both turned on at this time, so the first DC power supply V1 will not be short-circuited by the ninth switch tube M9 and the eleventh switch tube M11 and directly connected to the reference ground, thereby avoiding the occurrence of a large short-circuit current in the voltage conversion circuit, thereby solving the problem of damage to the ninth switch tube M9 and the eleventh switch tube M11 due to a half-high level, and improving the safety and reliability of the power supply circuit.

[0073] In some possible implementations, such as Fig.13 As shown, the tenth switch tube M10 can be used to be in a conducting state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal. At this time, the output end out2 of the second inverting unit outputs a high level, so the tenth switch tube M10 is in a conducting state. At this time, the output end out1 of the first inverting unit also outputs a high level, the ninth switch tube M9 is in an off state, and the eleventh switch tube M11 and the twelfth switch tube M12 are both in a conducting state. Therefore, the ninth switch tube M9 and the eleventh switch tube M11 are not both turned on at this time, avoiding a short-circuit large current in the voltage conversion circuit, and the tenth switch tube M10 is also turned on normally, solving the problem of outputting a half-high level, and improving the safety and reliability of the power supply circuit.

[0074] Please also see Fig.14 , Fig.14 Another structural diagram of the power supply circuit provided in this application. Fig.14 For example Fig.12 The voltage conversion circuit 12 in the power supply circuit 1 shown in the figure is specifically exemplified. In this case, the voltage conversion circuit can actually be an inverter. The power supply circuit can be applied to input and output buffering scenarios to improve the driving capability. Fig.14As shown, the voltage conversion circuit 12 includes a ninth switch tube M9 and a tenth switch tube M10, and the input end of the voltage conversion circuit 12 includes a first input end int121. The second end of the ninth switch tube M9 is connected to the reference ground through the tenth switch tube M10, and the first end of the ninth switch tube M9 is connected to the first DC power supply V1; the first input end int121 of the voltage conversion circuit 12 is connected to the control end of the ninth switch tube M9 and the control end of the tenth switch tube M10; the first input end int121 of the voltage conversion circuit 12 is connected to the output end out1 of the first inverting unit. The ninth switch tube M9 may be a PMOS tube, and the tenth switch tube M10 may be an NMOS tube.

[0075] like Fig.14 As shown, the level converter in the power supply circuit can be as described above Figure 2 , Figure 5-Figure 11 In any of the illustrated level converters, when the first clock signal suddenly changes from a high level signal to a low level signal and the second clock signal is a low level signal, the output terminal out1 of the first inverting unit outputs a high level instead of a half-high level, and at this time the ninth switch tube M9 is in an off state, and the tenth switch tube M10 is in an on state. In this way, the ninth switch tube M9 and the tenth switch tube M10 are not turned on at the same time, thereby avoiding the problem that both switch tubes are turned on, resulting in a short circuit and a large current in the circuit causing damage to the switch tube, reducing the risk of damage to the switch tube in the voltage conversion circuit due to the output of the half-high level by the level converter, improving the circuit reliability and safety, and increasing the service life of the device.

[0076] Please also see Fig.15 , Fig.15 This is another structural diagram of the power supply circuit provided by this application. Fig.15 As shown, Fig.14 Compared with the voltage conversion circuit in the power supply circuit shown, Fig.15 The voltage conversion circuit 12 shown also includes an eleventh switch tube M11 and a twelfth switch tube M12, and the input end of the voltage conversion circuit also includes a second input end int122. The second end of the eleventh switch tube M11 is connected to the reference ground through the twelfth switch tube M12, and the first end of the eleventh switch tube M11 is connected to the first DC power supply; the second input end int122 of the voltage conversion circuit is connected to the control end of the eleventh switch tube M11 and the control end of the twelfth switch tube M12; the second input end int122 of the voltage conversion circuit is connected to the output end out2 of the second inverting unit.

[0077] like Fig.15As shown, when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal, the output terminal out2 of the second inverting unit outputs not a half-high level but a high level, at which time the eleventh switch tube M11 is in an off state and the twelfth switch tube M12 is in an on state. In this way, the eleventh switch tube M11 and the twelfth switch tube M12 are not both turned on at the same time. In addition, when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal, the ninth switch tube M9 and the tenth switch tube M10 are not both turned on at the same time. In this way, when the second DC power supply is powered off at any moment, the situation where both switch tubes in the same inverter of the voltage conversion circuit are turned on can be avoided, thereby reducing the risk of damage to the switch tube in the voltage conversion circuit due to the output of a half-high level by the level converter, improving the circuit reliability and safety, and improving the service life of the device.

[0078] In the present application, a level converter including a first pull-up unit and / or a second pull-up unit can be applied in a power supply circuit, and a voltage conversion circuit in the power supply circuit serves as a post-stage circuit of the level converter. In the case where the power supply for the digital clock signal input to the level converter is powered off, the output end of the level converter outputs a high level instead of a half-high level, which can avoid the situation where two specific switch tubes in the voltage conversion circuit in the power supply circuit are turned on at the same time, resulting in short-circuit and large current damage, thereby reducing the possibility of damage to these switch tubes and improving the reliability and safety of the power supply circuit.

[0079] The present application also provides a display driver chip (Display Driver IC, DDIC), the display driver chip includes a linear regulator and Fig.12 or Fig.13 In the power supply circuit shown, the linear regulator is connected to a voltage conversion circuit in the power supply circuit, and the linear regulator is used to keep the voltage output by the voltage conversion circuit within a target voltage range. Fig.16 A schematic diagram of the structure of a display driver chip provided by the present application. In the display driver chip, the voltage conversion circuit in the power supply circuit can be a charge pump circuit. Since the level converter in the power supply circuit can still output a high level instead of a half-high level when the power supply of the digital clock circuit is powered off, the switch tube in the voltage conversion circuit will not be damaged due to the half-high level, and the safety and reliability of the entire power supply circuit are greatly improved, so that the display driver chip will not work abnormally due to the problem of the half-high level, thereby improving the working stability of the chip.

[0080] The present application also provides an input I / output O buffer circuit, the input / output buffer circuit includes an electrostatic protection ESD circuit and a Fig.12 , Fig.14 or Fig.15The power supply circuit shown in the figure is connected to the electrostatic protection circuit, and the electrostatic protection circuit is used to provide an electrostatic discharge path for the power supply circuit. Fig.17 A schematic diagram of the structure of the input / output buffer circuit provided by the present application. In the input / output buffer circuit, the voltage conversion circuit in the power supply circuit can be an inverter. Since the level converter in the power supply circuit still outputs a high level instead of a half-high level when the power supply of the digital clock circuit is powered off, the switch tube in the voltage conversion circuit will not be damaged due to the half-high level, and the safety and reliability of the entire power supply circuit are greatly improved. Therefore, the input / output buffer circuit will not work abnormally due to the problem of the half-high level, thereby improving the circuit stability.

[0081] The present application also provides an electronic device, which may include Figure 2 , Figure 5-Figure 11 Alternatively, the electronic device may include a level converter as shown in any of the diagrams Figure 12-Figure 15 The power supply circuit of any of the diagrams in the figure, or the electronic device may include the above-mentioned display driver chip or input / output buffer circuit. The electronic device may be a communication device, a computer, a notebook, a mobile phone, a tablet computer and other devices, and this application does not limit this. Fig.18 A schematic diagram of the structure of an electronic device provided in this application. Fig.18 Take the electronic device including the above display driver chip and display screen as an example. Fig.18 As shown, the display screen in the electronic device is connected to a display driver chip, the display driver chip is used to drive the display screen, and the display screen is used to display based on the drive of the display driver chip. In the electronic device, the level converter in the display driver chip still outputs a high level instead of a half-high level under abnormal conditions, which can reduce the risk of damage to the switch tube, so that the display driver chip can work normally, so that the display screen can display normally, reduce the risk of display screen failure (such as flashing green screen, flashing screen, etc.), and improve the reliability and working performance of the electronic device.

[0082] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A level converter, characterized in that: The level converter comprises a first switch tube, a second switch tube, a first inverting unit, a second inverting unit and a first pull-up unit, wherein: A first end of the first switch tube is connected to a first DC power supply, a second end of the first switch tube is connected to a reference ground through the first inverting unit, and a control end of the first switch tube is connected to an output end of the second inverting unit; A first end of the second switch tube is connected to the first DC power supply, a second end of the second switch tube is connected to the reference ground through the second inverting unit, and a control end of the second switch tube is connected to the output end of the first inverting unit; The input end of the first inverting unit and the input end of the second inverting unit are respectively connected to the first input end and the second input end of the level converter, and the output end of the first inverting unit and the output end of the second inverting unit are respectively connected to the output end of the level converter; The first pull-up unit is connected between the output end of the first inverting unit and the first DC power supply. The first pull-up unit is used to ensure that the current value flowing through the first pull-up unit is greater than the current value flowing through the first switch tube when the first clock signal input into the first input end of the level converter suddenly changes from a high-level signal to a low-level signal and the second clock signal input into the second input end of the level converter is a low-level signal.

2. The level converter according to claim 1, wherein: When the first clock signal is a high level signal and the second clock signal is a low level signal, the voltage of the first pull-up unit is equal to the voltage of the first DC power supply; The first pull-up unit is configured to be in a short-circuit state when the first clock signal is a low-level signal and the second clock signal is a high-level signal.

3. The level converter according to claim 1 or 2, characterized in that: The first pull-up unit includes a first resistor.

4. The level converter according to claim 1 or 2, characterized in that: The first pull-up unit includes a third switch tube, a first end of the third switch tube is connected to the first DC power supply, and a control end of the third switch tube and a second end of the third switch tube are both connected to the output end of the first inverting unit.

5. The level converter according to claim 4, characterized in that: The third switch tube is used to be in a conducting state when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal.

6. The level converter according to any one of claims 1 to 5, characterized in that: The level converter also includes a second pull-up unit, which is connected between the first DC power supply and the output end of the second inverting unit. The second pull-up unit is used to make the current value flowing through the second pull-up unit greater than the current value flowing through the second switch tube when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal.

7. The level converter according to claim 6, characterized in that: The second pull-up unit is used to be in a short-circuit state when the first clock signal is a high-level signal and the second clock signal is a low-level signal; When the first clock signal is a low level signal and the second clock signal is a high level signal, the voltage of the second pull-up unit is equal to the voltage of the first DC power supply.

8. The level converter according to claim 6 or 7, characterized in that: The second pull-up unit includes a second resistor.

9. The level converter according to claim 6 or 7, characterized in that: The second pull-up unit includes a fourth switch tube, a first end of the fourth switch tube is connected to the first DC power supply, and a control end of the fourth switch tube and a second end of the fourth switch tube are both connected to the output end of the second inverting unit.

10. The level converter according to claim 9, characterized in that: The fourth switch tube is in a conducting state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal.

11. The level converter according to any one of claims 1 to 10, characterized in that: The first inverting unit includes a fifth switch tube and a sixth switch tube, the second end of the first switch tube is connected to the reference ground through the fifth switch tube and the sixth switch tube connected in series; the second end of the fifth switch tube and the second end of the sixth switch tube are both connected to the output end of the first inverting unit, and the control end of the fifth switch tube and the control end of the sixth switch tube are both connected to the input end of the first inverting unit; The second inverting unit includes a seventh switch tube and an eighth switch tube, and the second end of the second switch tube is connected to the reference ground through the seventh switch tube and the eighth switch tube connected in series; the second end of the seventh switch tube and the second end of the eighth switch tube are both connected to the output end of the second inverting unit, and the control end of the seventh switch tube and the control end of the eighth switch tube are both connected to the input end of the second inverting unit.

12. A power supply circuit, characterized in that: The power supply circuit comprises a digital clock circuit, a voltage conversion circuit and a level converter according to any one of claims 1 to 11, wherein: The input end of the digital clock circuit is connected to the second DC power supply; the first output end and the second output end of the digital clock circuit are respectively connected to the first input end and the second input end of the level converter; the first output end and the second output end of the digital clock circuit are respectively used to output the first clock signal and the second clock signal, and the first clock signal is inverted with the second clock signal; the digital clock circuit is also used to suddenly change the first clock signal from a high level signal to a low level signal when the second DC power supply is powered off; The input end of the voltage conversion circuit is connected to the output end of the level converter.

13. The power supply circuit according to claim 12, characterized in that: The voltage conversion circuit includes a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube, a first capacitor and a second capacitor, and the input end of the voltage conversion circuit includes a first input end and a second input end, wherein: The second end of the ninth switch tube is connected to the first end of the tenth switch tube through the first capacitor, the first end of the ninth switch tube is connected to the first DC power supply, and the second end of the tenth switch tube is connected to the reference ground; The second end of the eleventh switch tube is connected to the second end of the twelfth switch tube through the first capacitor, the first end of the eleventh switch tube is connected to the reference ground, and the first end of the twelfth switch tube is connected to the output end of the voltage conversion circuit; the second capacitor is connected between the output end of the voltage conversion circuit and the reference ground; The first input end of the voltage conversion circuit is connected to the control end of the ninth switch tube, the control end of the eleventh switch tube and the control end of the twelfth switch tube; the second input end of the voltage conversion circuit is connected to the control end of the tenth switch tube; The first input terminal and the second input terminal of the voltage conversion circuit are respectively connected to the output terminal of the first inverting unit and the output terminal of the second inverting unit; The ninth switch tube is used to be in an off state when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal; The eleventh switch tube is configured to be in a conducting state when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal.

14. The power supply circuit according to claim 13, characterized in that: The tenth switch tube is configured to be in a conducting state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal.

15. The power supply circuit according to claim 12, characterized in that: The voltage conversion circuit includes a ninth switch tube and a tenth switch tube, and the input end of the voltage conversion circuit includes a first input end, wherein: The second end of the ninth switch tube is connected to the reference ground through the tenth switch tube, and the first end of the ninth switch tube is connected to the first DC power supply; the first input end of the voltage conversion circuit is connected to the control end of the ninth switch tube and the control end of the tenth switch tube; the first input end of the voltage conversion circuit is connected to the output end of the first inverting unit; The ninth switch tube is used to be in an off state when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal; The tenth switch tube is configured to be in a conducting state when the first clock signal suddenly changes from a high-level signal to a low-level signal and the second clock signal is a low-level signal.

16. The power supply circuit according to claim 15, characterized in that: The voltage conversion circuit further includes an eleventh switch tube and a twelfth switch tube, and the input end of the voltage conversion circuit further includes a second input end, wherein: The second end of the eleventh switch tube is connected to the reference ground through the twelfth switch tube, and the first end of the eleventh switch tube is connected to the first DC power supply; the second input end of the voltage conversion circuit is connected to the control end of the eleventh switch tube and the control end of the twelfth switch tube; the second input end of the voltage conversion circuit is connected to the output end of the second inverting unit; The eleventh switch tube is used to be in an off state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal; The twelfth switch tube is configured to be in a conducting state when the second clock signal suddenly changes from a high-level signal to a low-level signal and the first clock signal is a low-level signal.

17. A display driver chip, characterized in that: The display driver chip includes a linear regulator and a power supply circuit as described in any one of claims 12 to 14, wherein the linear regulator is connected to the power supply circuit, and the linear regulator is used to keep the voltage output by the voltage conversion circuit within a target voltage range.

18. An electronic device, characterized in that: The electronic device comprises a display screen and a display driver chip as claimed in claim 17, the display screen in the electronic device is connected to the display driver chip, and the display screen is used for displaying based on the drive of the display driver chip.

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