Up-converter and satellite communication system
By introducing multiple detection branches and logic control modules into the upconverter, the detection and adaptation of reference clock signals of different frequencies is solved, and the problem of insufficient flexibility in reference clock adaptation in traditional satellite communication systems is improved. System flexibility and cost-effectiveness.
Patent Information
- Application Number
- CN202411476767.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2024-12-31
AI Technical Summary
The reference clock adaptation flexibility of traditional satellite communication systems is low, resulting in increased system cost and increased complexity, and it is impossible to effectively adapt to changes in different reference clock signals.
Design an up-converter, including an intermediate frequency signal frequency conversion module, a reference clock processing module, a logic control module and a radio frequency switch, detect and adapt reference clock signals of different frequencies through multiple detection branches, and control the radio frequency switch through a logic control module. Turn on the corresponding channel to generate an adaptive local oscillator frequency.
It improves the flexibility of the upconverter, can adapt to the switching of different reference clock signals, reduces system costs, and monitors the reference signal quality to prevent bad clocks from affecting signal quality.
Smart Images
Figure CN119232088A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of radio frequency communication technology, and in particular to an up-converter and a satellite communication system. Background Art
[0002] Traditional satellite communication systems include modems, block up-converters (BUCs), low noise block down-converters (LNBs), power supply systems, and antenna feed systems. The modem is connected to the up-converter via an intermediate frequency cable. The modem provides the up-converter with a transmitting intermediate frequency signal and a reference clock signal. The up-converter filters the transmitting intermediate frequency signal, amplifies the intermediate frequency signal, mixes it, and then generates the required RF frequency. After filtering, it performs multi-stage power amplification. The reference clock is used as the reference clock of the phase-locked loop to generate the corresponding local oscillator frequency.
[0003] In actual applications, different modems use different reference clocks according to system design, such as 10MHz reference clock signals and 50MHz reference clock signals. Even the same system may switch between reference clocks. In this regard, according to the traditional solution, a different up-converter needs to be designed for each reference clock signal, but such a design will result in low system flexibility. In order to meet the changes in reference clocks, multiple up-converters need to be produced, which further increases the cost of the system. Summary of the invention
[0004] The present application provides an up-converter and a satellite communication system, which solves the problem of low flexibility in reference clock adaptation of satellite communication systems in related technologies. The present application can meet the application requirements of different reference clocks and different systems, has high flexibility, and can identify and monitor the quality of reference signals to prevent poor reference clocks from affecting the system signal quality.
[0005] In a first aspect, the present application provides an up-converter connected to a modem to receive an output signal provided by the modem, the up-converter comprising an intermediate frequency signal conversion module, a reference clock processing module, a logic control module, a radio frequency switch and a phase-locked loop module.
[0006] The input end of the intermediate frequency signal conversion module is connected to the output signal provided by the modem, and the intermediate frequency signal conversion module is used to amplify and mix the intermediate frequency signal using the local oscillator frequency;
[0007] Multiple input ends of the reference clock processing module are connected to the output signal provided by the modem, and each input end of the reference clock processing module corresponds to a detection branch. The reference clock processing module is used to detect and compare the frequency and power of the reference clock signal in the output signal provided by the modem through the multiple detection branches to determine the frequency of the reference clock and output a frequency comparison signal;
[0008] The input end of the logic control module is connected to the detection output end of the reference clock processing module, and the logic control module is used to determine the output control signal in combination with the frequency comparison signal output by the detection output end of the reference clock processing module;
[0009] The RF switch includes a control end, an output end and multiple input ends. The control end of the RF switch is connected to the control output end of the logic control module. The multiple input ends of the RF switch are respectively connected to the multiple output ends of the reference clock processing module in a one-to-one correspondence. The RF switch is used to select the reference clock signal connected to the target input end of the RF switch according to the control signal received by the control end of the RF switch and output it through the output end of the RF switch.
[0010] The reference input end of the phase-locked loop module is connected to the output end of the radio frequency switch. The phase-locked loop module is used to generate a local oscillator frequency provided to the intermediate frequency signal frequency conversion module according to the reference clock signal output by the radio frequency switch.
[0011] In a second aspect, the present application also provides a satellite communication system, which includes the above-mentioned up-converter.
[0012] The up-converter of the present application realizes detection and adaptation of multiple reference clock signals of different frequencies through multiple detection branches in the reference clock processing module, so that when the corresponding reference clock signal is connected, the up-converter can control the RF switch to conduct the corresponding channel through the logic control module, so that the phase-locked loop module can output the corresponding local oscillator frequency. Moreover, when the reference clock signal is switched, the reference clock processing module can also be used for adaptation, making the use of the up-converter more flexible, and realizing the adaptive switching of the reference clock signal with high flexibility. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 A schematic diagram of the structure of an up-converter provided in one embodiment of the present application;
[0014] Figure 2 A schematic diagram of the structure of a reference clock processing module provided in an embodiment of the present application;
[0015] Figure 3 A schematic diagram of the structure of a logic control module provided in one embodiment of the present application;
[0016] Figure 4A schematic diagram of the structure of a logic control module provided in another embodiment of the present application;
[0017] Figure 5 A schematic structural diagram of an up-converter provided in another embodiment of the present application. DETAILED DESCRIPTION
[0018] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only the parts related to the embodiments of the present application rather than all structures are shown in the accompanying drawings, and those skilled in the art should be able to think of it after reading the specification of this application that as long as the technical features do not contradict each other, any combination of the technical features can constitute an optional implementation method.
[0019] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally represents that the objects associated before and after are in an "or" relationship. In the description of the present application, "multiple" means two or more, and "several" means one or more.
[0020] Traditional satellite communication systems include modems, upconverters, low-noise downconverters, power systems, and antenna systems. The modem is responsible for digital signal processing, providing intermediate frequency signals and reference clocks for upconverters, or providing reference clocks for low-noise downconverters and processing intermediate frequency signals output by downconverters. The upconverter is responsible for converting the transmitted intermediate frequency signal to the required RF frequency and amplifying the signal. The low-noise downconverter is responsible for converting the received RF signal to an intermediate frequency that the modem can demodulate and providing sufficient receiving gain. The power system is responsible for powering the equipment (such as BUC, LNB, and others), and the antenna system includes antennas, polarizers, filters, turntables, etc., which are responsible for transmitting signals to satellites and receiving signals from satellites.
[0021] In actual applications, different modems use different reference clocks according to system design, such as 10MHz reference clock signals and 50MHz reference clock signals. Even the same system may switch between reference clocks. According to the traditional solution, different up-converters need to be designed for each reference clock signal, but such a design will result in low flexibility in system matching. In order to meet the changes in reference clocks, multiple up-converters need to be designed, which further increases the cost and complexity of the system.
[0022] In this regard, the present application provides an up-converter and a satellite communication system. The satellite communication system includes the up-converter of the present application as well as a modem, a low-noise down-converter, a power supply system and an antenna system. However, compared with the related art, the up-converter of the present application is provided with a corresponding detection branch to adapt the reference clock signal, which improves the flexibility of the system and effectively reduces the system cost.
[0023] Figure 1 This is a schematic diagram of the structure of an up-converter provided in an embodiment of the present application. The up-converter is connected to a modem and receives an output signal provided by the modem. Figure 1 As shown, the up-converter includes an intermediate frequency signal conversion module 110 , a reference clock processing module 120 , a logic control module 130 , a radio frequency switch 140 and a phase-locked loop module 150 .
[0024] The input end of the intermediate frequency signal conversion module 110 is connected to the output signal provided by the modem, and the intermediate frequency signal conversion module 110 can use the local oscillator frequency to amplify and mix the intermediate frequency signal. The multiple input ends of the reference clock processing module 120 are all connected to the output signal provided by the modem, and each input end of the reference clock processing module 120 corresponds to a detection branch. The reference clock processing module 120 is used to detect and compare the frequency and power of the reference clock signal in the output signal provided by the modem through multiple detection branches to determine the frequency of the reference clock and output a frequency comparison signal.
[0025] In addition, the input end of the logic control module 130 is connected to the detection output end of the reference clock processing module 120, and the logic control module 130 is used to determine the output control signal in combination with the frequency comparison signal output by the detection output end of the reference clock processing module 120. The RF switch 140 includes a control end, an output end and multiple input ends. The control end of the RF switch 140 is connected to the control output end of the logic control module 130, and the multiple input ends of the RF switch 140 are respectively connected to the multiple output ends of the reference clock processing module 120 in a one-to-one correspondence. It can be imagined that the RF switch 140 is a multi-input single-output device, thereby providing multiple signal channels, which are used to select the reference clock signal connected to the target input end of the RF switch 140 according to the control signal received by the control end of the RF switch 140 and output it through the output end of the RF switch 140. In addition, the reference input end of the phase-locked loop module 150 is connected to the output end of the RF switch 140, and the phase-locked loop module 150 is used to generate the local oscillator frequency provided to the intermediate frequency signal conversion module 110 according to the reference clock signal output by the RF switch 140.
[0026] It can be understood that the up-converter provides multiple detection branches through the reference clock processing module 120 thereon, so as to extract the reference clock signal in the input signal connected through the detection branch, and then when the logic control module 130 determines that the corresponding detection branch is connected with the corresponding reference clock signal, the RF switch 140 is controlled to open the signal channel corresponding to the detection branch, so that the phase-locked loop module 150 can generate the local oscillation frequency according to the corresponding reference clock signal. As for the intermediate frequency signal in the output signal, it will be processed by the intermediate frequency signal conversion module 110 of the up-converter, and the intermediate frequency signal will be mixed with the local oscillation frequency provided by the phase-locked loop module 150 to provide the corresponding radio frequency for the satellite communication system.
[0027] Exemplarily, when a 10 MHz or 50 MHz reference clock signal is used in a satellite communication process, the reference clock processing module of the up-converter includes detection branches corresponding to 10 MHz and 50 MHz, so that when a 10 MHz or 50 MHz reference clock signal is doped in the output signal provided by the modem, the up-converter can detect through the reference clock processing module whether the frequency corresponding to the reference clock signal is 10 MHz or 50 MHz, and pass the processed reference clock signal to the phase-locked loop module to realize the output of the local oscillator frequency according to the corresponding phase-locked loop configuration, thereby providing the satellite communication system with a radio frequency frequency adapted to the reference clock signal.
[0028] Therefore, the up-converter can detect and adapt multiple reference clock signals of different frequencies through multiple detection branches in the reference clock processing module, so that when the corresponding reference clock signal is connected, the up-converter can control the RF switch to conduct the corresponding channel through the logic control module, so that the phase-locked loop module can output the corresponding local oscillator frequency. Moreover, when the reference clock signal is switched, the reference clock processing module can also be used for adaptation, making the use of the up-converter more flexible and realizing the adaptive switching of the reference clock signal with high flexibility.
[0029] In one embodiment, the reference clock processing module includes at least two detection branches, and different detection branches correspond to different frequency bands to adapt to the corresponding reference clock signal. For example, based on the above example, the reference clock processing module includes detection branches corresponding to a 10MHz reference clock signal and a 50MHz reference clock signal, so that when the corresponding reference clock is connected, a corresponding channel can be provided to process the reference clock signal, so that the phase-locked loop module can provide a local oscillator frequency according to the reference clock information.
[0030] Specifically, the detection branch includes a first bandpass filter, a first amplifier, a power divider and a logarithmic detector. The input end of the first bandpass filter serves as the input end of the detection branch, the output end of the first bandpass filter is connected to the input end of the first amplifier, the output end of the first amplifier is connected to the input end of the power divider, the first output end of the power divider serves as the output end of the detection branch, the second output end of the power divider is connected to the logarithmic detector, the power divider is used to divide the signal power into two paths, and the logarithmic detector is used to detect the power intensity of the reference signal.
[0031] It can be imagined that the first bandpass filter is a device for accessing the reference clock signal in the detection branch. The frequency bands corresponding to the first bandpass filters in each detection branch are different, and they adapt to the corresponding reference clock signal, so that different detection branches adapt to a reference clock signal. Then, the reference clock signal corresponding to the detection branch can be accessed through the first bandpass filter, and amplified through the first amplifier, and the power divider can divide the amplified reference clock signal, so that one signal is given to the RF switch and the other is given to the logarithmic detector.
[0032] Figure 2 A schematic diagram of the structure of a reference clock processing module provided in an embodiment of the present application is shown in FIG. Figure 2As shown, two detection branches are provided in the reference clock processing module, the frequency of the reference clock signal corresponding to each detection branch is different, and each detection branch includes a bandpass filter, a first amplifier, a power divider and a logarithmic detector connected in sequence. Specifically, the dotted box in the figure indicates each detection branch, wherein the output end of the bandpass filter BPF1 in the first detection branch is connected to the input end of the amplifier A1, the output end of the amplifier A1 is connected to the input end of the power divider PD1, the first output end of the power divider PD1 is connected to an input end of the RF switch, and the second output end of the power divider PD1 is connected to the input end of the logarithmic detector LD1.
[0033] In the second detection branch, the output end of the bandpass filter BPF2 is connected to the input end of the amplifier A2, the output end of the amplifier A2 is connected to the input end of the power divider PD2, the first output end of the power divider PD2 is connected to the other input end of the RF switch, and the second output end of the power divider PD2 is connected to the input end of the logarithmic detector LD2. It can be imagined that the output end of the logarithmic detector LD1 and the output end of the logarithmic detector LD2 are respectively connected to different input ends of the frequency comparison unit, so that the frequency comparison unit provides the logic control module with the corresponding comparison result according to the voltage value output by each logarithmic detector, so that it can control the RF switch.
[0034] Exemplarily, in the case where the reference clock processing module includes a first detection branch corresponding to a 10MHz reference clock signal and a second detection branch corresponding to a 50MHz reference clock signal, when the output signal provided by the modem carries a corresponding 10MHz reference clock signal, the first detection branch can extract the reference clock signal from the output signal through the bandpass filter BPF1, and then after amplification by the amplifier A1, the power divider PD1 provides a signal to the logarithmic detector LD1, and the logarithmic detector LD1 generates a voltage signal corresponding to the frequency of the reference clock signal. Similarly, in the second detection branch, since there is no access to the corresponding 50MHz reference clock signal, the voltage signal provided by the logarithmic detector LD2 is small, and in this regard, the frequency comparison unit can output a corresponding comparison result according to the accessed voltage signal, and then, the logic control module can output a corresponding control signal based on the set functional mode and the comparison result to control the RF switch. Therefore, through the corresponding detection branch, the up-converter can adapt to the switching of reference clocks of multiple different frequencies, making the generation of RF signals more convenient and efficient, which helps to improve the flexibility of the up-converter.
[0035] In some embodiments, the reference clock processing module further includes a frequency comparison unit, the frequency comparison unit includes a plurality of input terminals, each input terminal of the frequency comparison unit is respectively connected to the output terminal of the logarithmic detector in a different detection branch, the output terminal of the frequency comparison unit is used as the detection output terminal of the reference clock processing module, and the frequency comparison unit is used to determine the voltage output of all logarithmic detectors to output a frequency comparison signal. It can be imagined that, based on the above-mentioned setting of two detection branches, the frequency comparison unit is connected to the voltage output of the logarithmic detector in the two detection branches, so as to compare the corresponding voltage magnitudes and then transmit the comparison result to the logic control module, so that the logic control module can output the corresponding control signal.
[0036] In one embodiment, when there are two detection branches, the frequency comparison unit includes a first hysteresis comparator, the non-inverting input terminal of the first hysteresis comparator is connected to the output terminal of the logarithmic detector in one detection branch, and the inverting input terminal of the first hysteresis comparator is connected to the output terminal of the logarithmic detector in the other detection branch. Figure 2 ,based on Figure 2 In the structure shown, the non-inverting input terminal of the first hysteresis comparator can be connected to the voltage signal provided by the logarithmic detector LD1, and the inverting input terminal of the first hysteresis comparator can be connected to the voltage signal provided by the logarithmic detector LD2, so that the first hysteresis comparator can represent different comparison results by outputting corresponding high-level signals or low-level signals.
[0037] In another embodiment, when there are three detection branches, the frequency comparison unit includes an adder, a second hysteresis comparator and a third hysteresis comparator. The output end of the logarithmic detector of the first detection branch and the output end of the logarithmic detector of the second detection branch are respectively connected to two input ends of the adder, the output end of the adder is connected to the non-inverting input end of the second hysteresis comparator, and the output end of the logarithmic detector of the third detection branch is connected to the inverting input end of the second hysteresis comparator.
[0038] In addition, the output end of the logarithmic detector of the first detection branch is also connected to the non-inverting input end of the third hysteresis comparator, and the output end of the logarithmic detector of the second detection branch is also connected to the inverting input end of the third hysteresis comparator. The output end of the third hysteresis comparator and the output end of the second hysteresis comparator both serve as the output end of the frequency comparison unit.
[0039] It can be understood that the voltage signal output by the logarithmic detector on the first detection branch and the second detection branch is compared through the third hysteresis comparator, and for the third detection branch, the signal connected to the third detection branch is determined by comparing it with the sum of the voltage signals provided by the first detection branch and the second detection branch, that is, the frequency comparison unit can provide two comparison results for the logic control module.
[0040] The response speed of the logarithmic detector for power detection of the reference clock signal is fast. Therefore, the up-converter uses the frequency comparison unit to compare the voltage values output by the logarithmic detector in each detection branch, and can quickly provide the corresponding comparison results to the logic control module, so as to facilitate faster switching control of the RF switch, which helps to improve the response speed of the system.
[0041] In one embodiment, the logic control module includes a multiplexing unit and a micro control unit, wherein the first input end of the multiplexing unit is connected to the output end of the reference clock processing module, and the output end of the multiplexing unit is connected to the control end of the radio frequency switch, and the first input end of the multiplexing unit is also connected to the first control interface of the micro control unit. The second control interface of the micro control unit is connected to the second input end of the multiplexing unit, and the third control interface of the micro control unit is connected to the control end of the multiplexing unit. The micro control unit is used to determine the signal output through the first control interface and the signal output through the third control interface according to the frequency comparison signal, so as to control the radio frequency switch to open the corresponding channel.
[0042] Figure 3 A schematic diagram of the structure of a logic control module provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, in the case where there are two detection branches, the multiplexing unit includes a multiplexer U1, and the multiplexer U1 includes two input interfaces. Specifically, the first input interface of the multiplexer U1 is connected to the detection output end of the reference clock processing module and the first control interface of the micro control unit U2, the second input interface of the multiplexer U1 is also connected to the second control interface of the micro control unit U2, and the control interface of the multiplexer U1 is connected to the third control interface of the micro control unit U2. The multiplexer U1 is used to select the input signal connected to the corresponding input interface according to the selection signal output by the third control interface of the micro control unit U2, and control the RF switch to open the corresponding channel according to the input signal.
[0043] It can be understood that the first input interface in the multiplexer U1 is connected to the signal provided by the detection output end of the reference clock processing module, for example, the output end of the frequency comparison unit connected to the first input interface of the multiplexer U1 is connected to the electrical signal corresponding to the comparison result (recorded as Vop). The second input interface of the multiplexer U1 is the signal provided by the connected micro-control unit U2 (recorded as Vom). In addition, the control interface of the multiplexer U1 is the third control interface of the connected micro-control unit U2, so that the micro-control unit U2 provides a corresponding selection signal (recorded as Venc) so that the multiplexer U1 outputs one of the connected signals (recorded as Vc_SW).
[0044] Figure 4A schematic diagram of the structure of a logic control module provided in another embodiment of the present application is shown in FIG. Figure 4 As shown, in one embodiment, when there are three detection branches, the multiplexing unit includes two multiplexers, each of which includes two input interfaces. Specifically, the multiplexer unit includes a first multiplexer U1 and a second multiplexer U3.
[0045] Among them, the first input interface of the first multiplexer U1 is connected to a detection output terminal on the reference clock processing module and is also connected to a first control interface on the micro control unit U2, and the signal connected to the first input interface of the first multiplexer U1 is recorded as Vop1. The second input interface of the first multiplexer U1 is connected to a second control interface on the micro control unit U2, and the signal connected to the second input interface of the first multiplexer U1 is recorded as Vom1. The control interface of the first multiplexer U1 is connected to a third control interface on the micro control unit U2, and the signal connected to the control interface of the first multiplexer U1 is recorded as Venc1.
[0046] The first input interface of the second multiplexer U3 is connected to another detection output terminal on the reference clock processing module and is also connected to another first control interface on the micro control unit U2. The signal connected to the first input interface of the second multiplexer U3 is recorded as Vop2. The second input interface of the second multiplexer U3 is connected to another second control interface on the micro control unit U2. The signal connected to the second input interface of the second multiplexer U3 is recorded as Vom2. The control interface of the second multiplexer U3 is connected to another third control interface on the micro control unit U2. The signal connected to the control interface of the second multiplexer U3 is recorded as Venc2.
[0047] In this regard, the microcontroller unit U2 provides a corresponding input signal for the second input interface of each multiplexer, and also controls the multiplexer through the corresponding third control interface to select the corresponding input signal to output to the RF switch, so as to control the RF switch to open the corresponding channel according to the two input signals. It can be imagined that when there are two input signals, when selecting the three channels in the RF switch, different high and low levels can be used to correspond to different channels. For example, if both the two selection signals are low-level signals, the RF switch can select and open the first channel; if both the two selection signals are high-level signals, the RF switch can select and open the second channel; if the two selection signals include one high-level signal and one low-level signal, the RF switch can select and open the third channel.
[0048] In some embodiments, the microcontroller is provided with functional modes, such as comparator mode, ADC (Analog to Digital Converter) comparison mode, first forced mode and second forced mode. For the selection of the above functional modes, the user can configure different working modes according to application needs and use different reference switching modes. The microcontroller can output corresponding electrical signals through the second control interface and the third control interface to correspond to the above functional modules.
[0049] Specifically, in the comparator mode, the microcontroller sets the configuration parameter register information of two corresponding phase-locked loop modules compiled in advance, and the high-speed I / O pin of the microcontroller is used to select the corresponding configuration parameter information according to the comparator frequency comparison signal and configure the phase-locked loop module.
[0050] In the ADC comparison mode, the ADC detection interface of the microcontroller unit is respectively connected to the signal voltage of each detection branch. The microcontroller unit is used to determine the power according to a preset calibration table, and output a target control signal in the presence of a target reference clock signal with maximum power and a power greater than a threshold so that the RF switch selects the channel corresponding to the target reference clock signal. The calibration table includes each voltage at a plurality of preset clock frequencies and the power corresponding to each voltage.
[0051] In the first forced mode, the microcontroller outputs a first control signal, which is used to make the RF switch select the channel corresponding to the first reference clock signal. In the second forced mode, the microcontroller outputs a second control signal, which is used to make the RF switch select the channel corresponding to the second reference clock signal.
[0052] Therefore, by providing multiple functional modes, the satellite communication system can adapt to different reference clock frequencies more flexibly. While being more flexible, it can also configure corresponding modes to identify and monitor the quality of the reference clock signal to prevent poor reference clocks from affecting the system signal quality.
[0053] In one embodiment, the intermediate frequency signal frequency conversion module includes a high-pass filter, a second amplifier, a mixer, a second band-pass filter and a third amplifier connected in sequence, wherein the frequency band of the high-pass filter corresponds to the intermediate frequency signal frequency, and the mixer is used to mix the intermediate frequency signal amplified by the second amplifier using the local oscillator frequency generated based on the reference clock signal and output it to the band-pass filter. It can be understood that after the output signal of the modem passes through the high-pass filter, the intermediate frequency signal frequency conversion module can extract the intermediate frequency signal therein, and then after amplification by the second amplifier, the intermediate frequency signal amplified by the second amplifier is mixed with the local oscillator frequency received by the mixer, so as to be transmitted to the second band-pass filter and then amplified by the third amplifier to generate the corresponding radio frequency.
[0054] Figure 5 A schematic diagram of the structure of an up-converter provided for another embodiment of the present application, in which a reference clock including a reference clock signal corresponding to 10 MHz or a reference clock signal corresponding to 50 MHz is taken as an example, and two detection branches are provided in the reference clock processing module. Specifically, the output signals provided by the modem are respectively connected to the bandpass filter BPF1, the bandpass filter BPF2 and the high-pass filter HPF1, wherein the output end of the bandpass filter BPF1 is connected to the input end of the amplifier A1, the output end of the amplifier A1 is connected to the input end of the power divider PD1, the first output end of the power divider PD1 is connected to an input end of the radio frequency switch SW1, and the second output end of the power divider PD1 is connected to the input end of the logarithmic detector LD1.
[0055] The output end of the bandpass filter BPF2 is connected to the input end of the amplifier A2, the output end of the amplifier A2 is connected to the input end of the power divider PD2, the first output end of the power divider PD2 is connected to the other input end of the RF switch SW1, and the second output end of the power divider PD2 is connected to the input end of the logarithmic detector LD2.
[0056] In addition, the output end of the logarithmic detector LD1 and the output end of the logarithmic detector LD2 are both connected to the hysteresis comparator Com1, specifically, the output end of the logarithmic detector LD1 is connected to the non-inverting input end of the hysteresis comparator Com1, and the output end of the logarithmic detector LD2 is connected to the inverting input end of the hysteresis comparator Com1. The output end of the hysteresis comparator Com1 is connected to the first input interface of the multiplexer.
[0057] Moreover, the first input interface of the multiplexer U1 is also connected to the first control interface of the micro control unit U2, the second input interface of the multiplexer U1 is connected to the second control interface of the micro control unit U2, and the control interface of the multiplexer U1 is connected to the third control interface of the micro control unit U2. The multiplexer U1 is used to select the input signal connected to the corresponding input interface according to the selection signal output by the third control interface of the micro control unit U2, and control the RF switch SW1 to open the corresponding channel according to the input signal. The output end of the RF switch SW1 is connected to the phase-locked loop module to provide a reference clock signal for the phase-locked loop module.
[0058] In addition, the intermediate frequency signal frequency conversion module includes a high-pass filter HPF1, an amplifier A3, a mixer Mix1, a band-pass filter BPF3 and an amplifier A4 connected in sequence. It can be imagined that the frequency band of the high-pass filter HPF1 corresponds to the intermediate frequency signal frequency. In this regard, after the output signal provided by the modem is connected, the high-pass filter HPF1 selects the intermediate frequency signal frequency from it, and enters the mixer Mix1 after amplification through the amplifier A3. The mixer Mix1 uses the received local oscillator frequency to mix the intermediate frequency signal amplified by the amplifier A3 and outputs it to the band-pass filter BPF3, and then amplifies it through the amplifier A4 to generate the corresponding radio frequency frequency. Among them, the local oscillator frequency can be filtered by the band-pass filter BPF4 and then connected to the mixer Mix1.
[0059] For example, taking the up-converter of a satellite transmitter with an operating frequency of 29-30 GHz as an example, the intermediate frequency range of its transmission is 0.95-1.95 GHz, the transmission local oscillator frequency is 28.05 GHz, and the external input reference clock frequency may be 10 MHz or 50 MHz.
[0060] Based on this, in the comparator mode, the software firmware in the microcontroller unit compiles the corresponding configuration parameter information in advance, which can be stored in the form of an internal configuration table of the product. After determining the corresponding solution, the corresponding registers of the phase-locked loop are configured according to the parameters in the table to generate the corresponding local oscillator frequency. The corresponding internal configuration table of the product is as follows:
[0061]
[0062] From the above table, we can see that the local oscillator frequency F out With external reference frequency F ref The relationship is as follows:
[0063]
[0064] It can be imagined that, through the corresponding configuration scheme, after determining the reference clock frequency, the up-converter can select the corresponding configuration scheme to configure the register of the phase-locked loop, so as to generate the corresponding local oscillator frequency. The first input interface of the multiplexer U1 is connected to the output end of the hysteresis comparator Com1 to access the electrical signal corresponding to the comparison result (denoted as Vop). The second input interface of the multiplexer U1 is the signal provided by the connected micro-control unit U2 (denoted as Vom). In addition, the control interface of the multiplexer U1 is the third control interface of the connected micro-control unit U2, so that the micro-control unit U2 provides a corresponding selection signal (denoted as Vc_SW) so that the multiplexer U1 outputs one of the connected signals. For example, when the frequency of the reference clock signal is 10MHz, the voltage value detected by the logarithmic detector LD1 is greater than the voltage value detected by the logarithmic detector LD2. In response, the hysteresis comparator Com1 outputs a high-level signal, that is, Vop is high-level. Correspondingly, the Venc output by the microcontroller U2 is low-level, so that the multiplexer U1 outputs the signal connected to its first input interface, so that the RF switch turns on the channel corresponding to the 10MHz reference clock, and at this time, the Vom output by the microcontroller U2 is in a high-impedance state. The microcontroller U2 monitors the level state of Vop in real time through the high-speed I / O pin, and configures the corresponding register parameter information for the phase-locked loop according to the high and low levels of Vop, and only configures the different parts of the phase-locked loop register.
[0065] Based on this, in comparator mode, the mode response speed is very fast. Referring to the response time of the logarithmic detector of 10ns, the microcontroller interrupt processing + register configuration time is about 15us, and the phase-locked loop re-locks the phase in about 150us, so the overall switching time is less than 200us.
[0066] In the ADC comparison mode, this mode is stable and reliable, and is not easily disturbed by the instantaneous mutation of the reference. The microcontroller unit is provided with a calibration table, which includes the voltages at multiple preset clock frequencies and the power corresponding to each voltage. It is conceivable that different reference clock input powers are calibrated, such as using a logarithmic detector to perform power detection on the reference clock. The advantage of the logarithmic detector is that the response speed is very fast, about 10ns, and it is the fastest power detector among various detectors. For example, the reference power corresponding to the detection voltage of the 10 / 50MHz reference clock is calibrated respectively, and the signal source is used to simulate the reference input, and the output power of the signal source is adjusted so that the reference input power is adjusted in 1dB steps from -25dBm to +10dBm. The ADC inside the MCU records the corresponding voltage value to complete the calibration of the two reference powers, as shown in the following table (only part is shown):
[0067]
[0068]
[0069] The detection interface of the microcontroller unit is respectively connected to the signal voltages of the above-mentioned two detection paths, namely, the voltage V1 output by the logarithmic detector LD1 and the voltage V2 output by the logarithmic detector LD2. It can be understood that in the ADC comparison mode, the microcontroller unit detects the above-mentioned voltage V1 and voltage V2, and can determine the corresponding input power P1 and input power P2 according to the calibration ratio table, and then the microcontroller unit compares the power of the input power P1 and the input power P2, and takes the input power that is greater than the threshold and has a larger power as the current reference clock. Optionally, in one embodiment, if the power of the two reference clock signals is too low and does not exceed the threshold, the microcontroller unit maintains the current state.
[0070] The Venc output by the microcontroller U2 is a high-level signal, and in response, the multiplexer U1 outputs the signal connected to its second input interface, that is, the microcontroller U2 can refer to the RF switch through the output signal Vom. For example, if Vom is a low-level signal, the RF switch turns on the channel corresponding to the 10MHz reference clock, and if Vom is a high-level signal, the RF switch turns on the channel corresponding to the 50MHz reference clock. When configuring the phase-locked loop, the microcontroller can configure the corresponding register parameters of the phase-locked loop according to the above-mentioned product internal configuration table.
[0071] In addition, the microcontroller unit U2 is also provided with a mode for forcing the use of the corresponding reference clock, such as the first forced mode and the second forced mode. In the first forced mode, the microcontroller unit outputs a first control signal, and in response to this, after receiving the first control signal, the RF switch SW1 turns on the channel corresponding to the 10MHz reference clock; in the second forced mode, the microcontroller unit outputs a second control signal, and in response to this, after receiving the second control signal, the RF switch SW1 turns on the channel corresponding to the 50MHz reference clock. It can be understood that in the first forced mode or the second forced mode, the system cannot perform soft switching, which can be used to locate the problem of reference clock failure, and can continue to work even when the logarithmic detector, hysteresis comparator, and system error design configure two reference clocks at the same time.
[0072] An embodiment of the present application also provides a satellite communication system, which includes the up-converter provided in the above embodiment. In this regard, the satellite communication system can adapt to the frequency switching of different reference clocks without designing corresponding up-converter structures for different reference clocks, thereby improving the flexibility of the system.
[0073] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0074] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.
Claims
1. An up-converter, characterized in that: connected to a modem to receive an output signal provided by the modem, the up-converter comprising: An intermediate frequency signal frequency conversion module, the input end of which is connected to the output signal provided by the modem, and the intermediate frequency signal frequency conversion module is used to amplify and mix the intermediate frequency signal using the local oscillator frequency; A reference clock processing module, wherein multiple input terminals of the reference clock processing module are connected to the output signal provided by the modem, each input terminal of the reference clock processing module corresponds to a detection branch, and the reference clock processing module is used to detect and compare the frequency and power of the reference clock signal in the output signal provided by the modem through the multiple detection branches to determine the frequency of the reference clock and output a frequency comparison signal; A logic control module, wherein an input end of the logic control module is connected to a detection output end of the reference clock processing module, and the logic control module is used to determine an output control signal in combination with a frequency comparison signal output by the detection output end of the reference clock processing module; A radio frequency switch, wherein the radio frequency switch comprises a control end, an output end and multiple input ends, the control end of the radio frequency switch is connected to the control output end of the logic control module, the multiple input ends of the radio frequency switch are respectively connected to the multiple output ends of the reference clock processing module in a one-to-one correspondence, and the radio frequency switch is used to select the reference clock signal connected to the target input end of the radio frequency switch according to the control signal received by the control end of the radio frequency switch and output it through the output end of the radio frequency switch; A phase-locked loop module, wherein a reference input end of the phase-locked loop module is connected to an output end of the radio frequency switch, and the phase-locked loop module is used to generate a local oscillator frequency provided to the intermediate frequency signal conversion module according to a reference clock signal output by the radio frequency switch.
2. The up-converter according to claim 1, characterized in that: The reference clock processing module comprises at least two detection branches, wherein the detection branches comprise a first bandpass filter, a first amplifier, a power divider and a logarithmic detector; The input end of the first band-pass filter serves as the input end of the detection branch, the output end of the first band-pass filter is connected to the input end of the first amplifier, the output end of the first amplifier is connected to the input end of the power divider, the first output end of the power divider serves as the output end of the detection branch, the second output end of the power divider is connected to the logarithmic detector, the power divider is used to divide the signal power into two paths, and the logarithmic detector is used to detect the power intensity of the signal; The first bandpass filters in different detection branches correspond to different frequency bands.
3. The up-converter according to claim 2, characterized in that: The reference clock processing module also includes a frequency comparison unit, which includes multiple input terminals. Each input terminal of the frequency comparison unit is respectively connected to the output terminal of the logarithmic detector in a different detection branch. The output terminal of the frequency comparison unit serves as the detection output terminal of the reference clock processing module. The frequency comparison unit is used to determine the voltage output by all logarithmic detectors to output a frequency comparison signal.
4. The up-converter according to claim 3, characterized in that: In the case where there are two detection branches, the frequency comparison unit includes a first hysteresis comparator, a non-inverting input end of the first hysteresis comparator is connected to the output end of the logarithmic detector in one detection branch, and an inverting input end of the first hysteresis comparator is connected to the output end of the logarithmic detector in the other detection branch; or, In the case where there are three detection branches, the frequency comparison unit includes an adder, a second hysteresis comparator and a third hysteresis comparator; The output end of the logarithmic detector of the first detection branch and the output end of the logarithmic detector of the second detection branch are respectively connected to the two input ends of the adder, the output end of the adder is connected to the non-inverting input end of the second hysteresis comparator, and the output end of the logarithmic detector of the third detection branch is connected to the inverting input end of the second hysteresis comparator; The output end of the logarithmic detector of the first detection branch is also connected to the non-inverting input end of the third hysteresis comparator, and the output end of the logarithmic detector of the second detection branch is also connected to the inverting input end of the third hysteresis comparator. The output end of the third hysteresis comparator and the output end of the second hysteresis comparator both serve as the output end of the frequency comparison unit.
5. The up-converter according to claim 1, characterized in that: The logic control module includes a multiplexing unit and a micro control unit; The first input end of the multiplexing unit is connected to the output end of the reference clock processing module, and the output end of the multiplexing unit is connected to the control end of the radio frequency switch, and the first input end of the multiplexing unit is also connected to the first control interface of the micro control unit; The second control interface of the microcontroller unit is connected to the second input end of the multiplexing unit, and the third control interface of the microcontroller unit is connected to the control end of the multiplexing unit. The microcontroller unit is used to determine the signal output through the first control interface and the signal output through the third control interface according to the frequency comparison signal to control the radio frequency switch to open the corresponding channel.
6. The up-converter according to claim 5, characterized in that: In the case where there are two detection branches, the multiplexing unit comprises a multiplexer, and the multiplexer comprises two input interfaces; Among them, the first input interface of the multiplexer is connected to the detection output end of the reference clock processing module and the first control interface of the micro control unit, the second input interface of the multiplexer is also connected to the second control interface of the micro control unit, and the control interface of the multiplexer is connected to the third control interface of the micro control unit. The multiplexer is used to select the input signal connected to the corresponding input interface according to the selection signal output by the third control interface of the micro control unit, so as to control the radio frequency switch to open the corresponding channel according to the input signal.
7. The up-converter according to claim 5, characterized in that: In the case where there are three detection branches, the multiplexing unit includes two multiplexers, and each of the multiplexers includes two input interfaces; Among them, the first input interface of each of the multiplexers is correspondingly connected to different detection output ends on the reference clock processing module and different first control interfaces on the micro control unit, the second input interface of each of the multiplexers is correspondingly connected to different second control interfaces on the micro control unit, and the control interface of each of the multiplexers is correspondingly connected to different third control interfaces on the micro control unit. The two multiplexers are used to select the input signals connected to the corresponding two input interfaces according to the two selection signals output by different third control interfaces on the micro control unit, so as to control the RF switch to open the corresponding channel according to the two input signals.
8. The up-converter according to claim 5, characterized in that: The microcontroller unit is provided with a comparator mode, an ADC comparison mode, a first forcing mode and a second forcing mode; In the comparator mode, the microcontroller is provided with two configuration parameter information corresponding to the phase-locked loop module, and the microcontroller is used to select the corresponding configuration parameter information according to the frequency comparison signal and configure the phase-locked loop module; In the ADC comparison mode, the detection interface of the microcontroller unit is respectively connected to the signal voltage of each detection branch, and the microcontroller unit is used to determine the power according to a preset calibration table, and output a target control signal in the presence of a target reference clock signal with maximum power and power greater than a threshold value so that the radio frequency switch selects the channel corresponding to the target reference clock signal, and the calibration table includes each voltage at a plurality of preset clock frequencies and the power corresponding to each voltage one by one; In the first forced mode, the micro control unit outputs a first control signal, where the first control signal is used to enable the radio frequency switch to select a channel corresponding to a first reference clock signal; In the second forced mode, the micro control unit outputs a second control signal, and the second control signal is used to enable the radio frequency switch to select a channel corresponding to the second reference clock signal.
9. The up-converter according to any one of claims 1 to 8, characterized in that: The intermediate frequency signal frequency conversion module includes a high-pass filter, a second amplifier, a mixer, a second band-pass filter and a third amplifier connected in sequence, wherein the mixer is used to mix the intermediate frequency signal amplified by the second amplifier using the received local oscillator frequency generated based on the reference clock signal and output it to the second band-pass filter.
10. A satellite communication system, characterized in that: Comprising the up-converter as claimed in any one of claims 1 to 9.