Circuit for reducing delay dissipation of flight time measurement system
The circuit addresses signal processing circuit delays in time-of-flight measurement systems by dynamically adjusting PGA gain and optimizing the comparator, ensuring accurate and low-power operation across varying signal amplitudes.
Patent Information
- Application Number
- CN202411462386.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2024-12-31
AI Technical Summary
Existing time-of-flight measurement systems face challenges in accurately compensating for signal processing circuit delays that vary with input signal amplitude, leading to measurement errors and increased power consumption due to the use of ADC chips and non-optimized PGA gain steps.
A circuit design incorporating a digital signal processing unit, comparator, control unit, PGA circuit, and peak detection unit, with a low-delay comparator and current regulation, dynamically adjusts PGA gain based on signal amplitude to maintain stability and reduce delay fluctuations, while optimizing the comparator and minimizing power consumption.
The circuit achieves reduced delay variation and power consumption by adaptively controlling PGA gain, maintaining signal stability and accuracy across varying signal amplitudes, thereby improving time measurement precision and reducing power usage.
Smart Images
Figure CN119232163A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of time measurement, and in particular to a circuit for reducing delay dissipation of a flight time measurement system. Background Art
[0002] In the process of using a time-to-digital converter to measure time, a signal processing circuit is often required to process the system's analog signal into a digital signal. Therefore, the time measured by the time-to-digital converter includes not only the time of the time measurement target link, but also the delay of each signal processing circuit, such as Figure 1 As shown in Figure 1. If the signal processing circuit delay is fixed, it is easy to compensate, but usually the delay of the processing circuit will change with the input signal, making compensation difficult or costly, and errors in time measurement results are difficult to avoid. Therefore, reducing the spread of signal processing circuit delay is important to reduce the time measurement error of the system.
[0003] In the traditional solution, the signal processing circuit only includes a comparator, such as Figure 2 As shown in Figure 1, the propagation delay of this circuit is large when the input signal amplitude changes.
[0004] There is a solution to reduce the delay spread of signal processing circuits. Figure 3 As shown in the figure, it uses an ADC chip to sample the signal amplitude, and controls the gain of the PGA (programmable gain amplifier) by digital means to keep the signal amplitude of the transducer at a certain level. This solution reduces the processing delay of the signal processing circuit under different amplitude input signals to a certain extent, and can reduce the delay dispersion of the signal processing circuit to a certain extent, but it still cannot meet the demand. At the same time, this solution uses an ADC chip to sample the signal strength, which will increase the circuit cost and power consumption; this solution requires the PGA gain step to be fine, resulting in a large number of stages and a large chip area; the ADC internal comparator of this solution is not optimized, and the PGA needs to be always open, which greatly increases the power consumption. Summary of the invention
[0005] The purpose of the present invention is to provide a circuit with small delay variation and low power consumption for reducing the delay dissipation of a time-of-flight measurement system in response to the problems existing in the prior art.
[0006] The object of the present invention is achieved through the following technical solutions:
[0007] A circuit for reducing delay dissipation of a time-of-flight measurement system comprises a digital signal processing unit, a comparator, a control unit, and a PGA circuit. The circuit further comprises a peak detection unit. The comparator, the PGA circuit, and the peak detection unit constitute a signal processing circuit, which is respectively connected to the digital signal processing unit and the control unit. The peak detection unit detects the amplitude of the signal amplified by the PGA circuit, and dynamically adjusts the gain of the PGA circuit according to the deviation between the detection result and the ideal signal.
[0008] As a further technical solution, the comparator is a low delay dissipation comparator.
[0009] As a further technical solution, the low delay dissipation comparator includes a comparator body and a current regulation circuit, and the current regulation circuit is connected to the differential amplifier of the comparator body to regulate the charging or discharging current of the differential amplifier.
[0010] As a further technical solution, the current regulating circuit includes transistors M9 and M 10 The gate and drain of transistor M9 are connected to the drain of transistor M2 and the drain of transistor M4 of the differential amplifier, the source of transistor M9 is connected to the power ground GND of the circuit, and transistor M 10 The gate and drain of are connected to the drain of transistor M1 and the drain of transistor M3 of the differential amplifier. 10 The source is connected to the circuit's power ground GND.
[0011] As a further technical solution, the peak detection unit is connected between the control unit and the PGA circuit, and PGA gain control is achieved by adaptively adjusting the negative feedback resistance of the folded common-source and common-gate class AB amplifier according to the result of the peak detection unit.
[0012] As a further technical solution, when the result of the peak detection unit is lower than the value set by the user, the gain of the PGA circuit increases from the lowest level until the result of the peak detection unit is greater than the value set by the user or the PGA circuit reaches the maximum gain level.
[0013] As a further technical solution, the PGA circuit is in an open state only when the signal fluctuates greatly, and is in a closed state in other cases.
[0014] Compared with the prior art, the present invention has the following advantages:
[0015] 1. The present invention adopts a peak detection unit to sample the signal strength, thereby reducing circuit cost and power consumption;
[0016] 2. Due to the optimization of the comparator, the signal processing circuit can maintain a small delay change within a large signal amplitude change range, the PGA gain stage requirement is low, and the chip area is reduced;
[0017] 3. Due to the optimization of the comparator, the signal processing circuit can maintain a small delay change within a larger signal amplitude change range. Within a certain signal change range, the PGA circuit can be turned off, greatly reducing the circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 This is a time measurement error analysis diagram of a time-to-digital converter;
[0019] Figure 2 It is a traditional signal processing circuit;
[0020] Figure 3 An existing circuit diagram for reducing circuit delay spread;
[0021] Figure 4 is a circuit diagram of the present invention;
[0022] Figure 5 for Figure 4 Detailed circuit diagram of PGA and peak detection module in;
[0023] Figure 6 for Figure 4 Circuit diagram of a low to medium delay dissipation comparator. DETAILED DESCRIPTION
[0024] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
[0025] Example 1
[0026] The overall design of the present invention is as follows: The peak detection unit of the present invention detects the signal amplitude after being amplified by the PGA circuit (PGA for short), and dynamically adjusts the PGA gain according to the deviation between the detection result and the ideal signal to maintain signal stability. At the same time, the present invention optimizes the design of the comparator part, greatly reducing its delay dispersion under different input signals. The entire echo signal processing circuit maintains extremely small delay fluctuations within a larger input signal amplitude variation range, thereby improving the accuracy of the time measurement system when the input signal amplitude changes. The PGA circuit is only turned on when the signal fluctuates greatly, and is turned off in other cases (most of the time), greatly reducing circuit power consumption.
[0027] Specifically, the present embodiment provides a circuit for reducing the delay dissipation of a flight time measurement system. Figure 4As shown, the circuit includes a digital signal processing unit, a comparator, a control unit, a PGA circuit and a peak detection unit. The comparator, the PGA circuit and the peak detection unit constitute a signal processing circuit, which is connected to the digital signal processing unit and the control unit respectively. The peak detection unit detects the amplitude of the signal amplified by the PGA circuit, and dynamically adjusts the gain of the PGA circuit according to the deviation between the detection result and the ideal signal.
[0028] Example 2
[0029] This embodiment uses a low-delay dissipation comparator as the comparator of this embodiment. The low-delay dissipation comparator includes a comparator body and a current regulating circuit. The current regulating circuit is connected to the differential amplifier of the comparator body to regulate the charging or discharging current of the differential amplifier.
[0030] The rest of this embodiment is the same as that of Embodiment 1.
[0031] Example 3
[0032] like Figure 6 As shown, this embodiment provides a specific low-delay dissipation comparator, which includes a comparator body and a current regulation circuit, wherein the current regulation circuit includes transistors M9 and M 10 The gate and drain of transistor M9 are connected to the drain of transistor M2 and the drain of transistor M4 of the differential amplifier, the source of transistor M9 is connected to the power ground GND of the circuit, and transistor M 10 The gate and drain of are connected to the drain of transistor M1 and the drain of transistor M3 of the differential amplifier. 10 The source is connected to the circuit's power ground GND.
[0033] for Figure 6 The comparator in (without M9 and M 10 ), the first stage is a differential amplifier, which contributes the most to the delay variation. The delay variation caused by overdrive is mainly due to the parasitic load capacitance (C Load ) changes in the charging rate. If the input signal amplitude is high, the charging or discharging current (I charge ) is large, so the secondary circuit output will flip quickly, and vice versa. Delay time (T pd ) can be approximated as Where α is the DC operating point related coefficient. Since ΔV is proportional to the input overdrive voltage, it is obvious that in order to maintain a relatively constant T at different input overdrive voltages, pd , I can be adjusted dynamically by ΔV charge In order to adjust I charge , designed the current regulation circuit (M9 and M10 ),like Figure 6 As shown. The current sink of the current regulating circuit is adaptively increased or decreased. As a result, the small propagation delay of the high amplitude input increases. The propagation delay associated with the low amplitude input decreases as the comparator bandwidth increases due to the reduced load impedance on the differential amplifier. Therefore, the delay spread is minimized.
[0034] The rest of this embodiment is the same as that of Embodiment 2.
[0035] Example 4
[0036] like Figure 5 As shown, the peak detection unit is connected between the control unit and the PGA circuit, and the PGA gain control is achieved by adaptively adjusting the negative feedback resistor of the folded cascode class AB amplifier according to the result of the peak detection unit. When the result of the peak detection unit is lower than the value set by the user, the gain of the PGA circuit increases from the minimum level until the result of the peak detection unit is greater than the value set by the user or the PGA circuit reaches the maximum gain level. If the original signal is strong enough, the PGA circuit is only turned on when the signal fluctuates greatly, and is turned off in other cases to achieve low power consumption applications.
[0037] The rest of this embodiment is the same as that of Embodiment 1.
[0038] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A circuit for reducing delay dissipation of a time-of-flight measurement system, comprising a digital signal processing unit, a comparator, a control unit, and a PGA circuit, characterized in that: The circuit also includes a peak detection unit. The comparator, PGA circuit and peak detection unit constitute a signal processing circuit, which is connected to the digital signal processing unit and the control unit respectively. The peak detection unit detects the amplitude of the signal amplified by the PGA circuit and dynamically adjusts the gain of the PGA circuit according to the deviation between the detection result and the ideal signal.
2. A circuit for reducing delay dissipation in a time-of-flight measurement system according to claim 1, characterized in that: The comparator is a low delay dissipation comparator.
3. A circuit for reducing delay dissipation of a time-of-flight measurement system according to claim 1, characterized in that: The low delay dissipation comparator comprises a comparator body and a current regulating circuit, wherein the current regulating circuit is connected to a differential amplifier of the comparator body to regulate a charging or discharging current of the differential amplifier.
4. The circuit for reducing delay dissipation of a time-of-flight measurement system according to claim 1, characterized in that: The current regulating circuit includes transistors M9 and M 10 The gate and drain of transistor M9 are connected to the drain of transistor M2 and the drain of transistor M4 of the differential amplifier, the source of transistor M9 is connected to the power ground GND of the circuit, and transistor M 10 The gate and drain of are connected to the drain of transistor M1 and the drain of transistor M3 of the differential amplifier. 10 The source is connected to the circuit's power ground GND.
5. The circuit for reducing delay dissipation of a time-of-flight measurement system according to claim 1, characterized in that: The peak detection unit is connected between the control unit and the PGA circuit, and the PGA gain control is achieved by adaptively adjusting the negative feedback resistance of the folded cascode class AB amplifier according to the result of the peak detection unit.
6. The circuit for reducing delay dissipation of a time-of-flight measurement system according to claim 5, characterized in that: When the result of the peak detection unit is lower than the value set by the user, the gain of the PGA circuit increases from the minimum level until the result of the peak detection unit is greater than the value set by the user or the PGA circuit reaches the maximum gain level.
7. The circuit for reducing delay dissipation of a time-of-flight measurement system according to claim 1, characterized in that: The PGA circuit is in an open state only when the signal fluctuates greatly, and is in a closed state in other cases.