Semiconductor device, control method for semiconductor device, and control program

Abstract

Embodiments of the invention relate to a semiconductor device, a control method for the semiconductor device, and a control program. The invention provides a semiconductor device capable of accurately operating while suppressing propagation of interference noise, a control method for the semiconductor device, and a control program. A semiconductor device according to the present disclosure includes: a charge redistribution sequential comparison type first AD converter including a redundant comparison operation in a sequential comparison operation, and outputting an analog differential first input signal as a digital first output signal using a reference voltage; a first pin to which a reference voltage is supplied from the outside; a first variable impedance circuit provided on the signal line between the first AD converters and capable of changing impedance; and a first control circuit that controls an impedance of the first variable impedance circuit in accordance with an operating condition of the first AD converter.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-105804 filed on June 28, 2023 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, a control method for the semiconductor device, and a control program, for example, a semiconductor device capable of accurately operating while suppressing propagation of disturbance noise, a control method for the semiconductor device, and a control program. Background Art

[0004] The following is a list of publicly available technologies.

[0005] [Non-Patent Document 1] Akira Matsuzawa, “Future of Analog-ADC Development”, [Online], March 15, 2013, [Retrieved May 2023], Internet,<URL:http: / / www.ssc.pe.titech.ac.jp / publications / 2013 / RFanalog / matsu_open_130315.pdf>

[0006] Non-Patent Document 1 discloses a charge redistribution type successive approximation AD converter. Summary of the invention

[0007] In a charge redistribution type successive approximation AD converter, reference voltage noise is generated on a signal line that propagates a reference voltage due to charging and discharging by switching capacitance during continuous comparison operations. In particular, in a comparison operation for determining the value of a high bit of a digital signal, since a large capacity switching is performed, a current change caused by charging and discharging becomes drastic, and the noise generated on the signal line that propagates the reference voltage becomes large. Therefore, there is a problem that noise is transmitted to other circuits that share the signal line that propagates the reference voltage, and these other circuits cannot operate accurately.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] A semiconductor device according to an embodiment of the present disclosure includes: a charge redistribution type successive approximation first AD converter, which includes a redundant comparison operation in a continuous comparison operation and outputs an analog differential first input signal as a first digital output signal using a reference voltage; a first pin, to which a reference voltage is supplied from the outside; a first variable impedance circuit, which is arranged on a signal line between the first AD converters and is configured to be able to change impedance; and a first control circuit, which controls the impedance of the first variable impedance circuit according to an operating condition of the first AD converter.

[0010] A control method of a semiconductor device according to an embodiment of the present disclosure is a control method of a semiconductor device including a charge redistribution type successive approximation first AD converter, the first AD converter including a redundant comparison operation in a continuous comparison operation, and outputting an analog differential first input signal as a first digital output signal using a reference voltage; a first pin to which a reference voltage is externally supplied; a first variable impedance circuit, which is provided on a signal line between the first AD converters and is configured to be able to change impedance; and a first control circuit, which controls the impedance of the first variable impedance circuit according to an operating condition of the first AD converter, controls the impedance of the first variable impedance circuit to a first impedance, performs a comparison operation to determine a value of a high bit in a first predetermined range of a plurality of bits representing a first output signal in the first AD converter, controls the impedance of the first variable impedance circuit to a second impedance lower than the first impedance, performs a comparison operation to determine a value of a low bit other than a high bit in a plurality of bits representing a first output signal in the first AD converter, and performs a redundant comparison operation.

[0011] A control program according to an embodiment of the present disclosure includes a redundant comparison operation in a sequential comparison operation, and outputs a first analog differential input signal as a first digital output signal using a reference voltage; a first AD converter of a charge redistribution type sequential comparison type; a first pin to which a reference voltage is externally supplied; a first variable impedance circuit which is provided on a signal line between the first AD converters and is capable of changing impedance; and a first control circuit which controls the impedance of the first variable impedance circuit according to an operating condition of the first AD converter, and the control program is a control program which causes a computer to perform a control process in a semiconductor device, and controls the impedance of the first variable impedance circuit to be a first impedance, and performs a comparison operation to determine a value of a high bit within a first predetermined range of a plurality of bits representing a first output signal in the first AD converter, and controls the impedance of the first variable impedance circuit to be a second impedance lower than the first impedance, and in the first AD converter, performs a comparison operation to determine a value of a low bit other than a high bit in a plurality of bits representing the first output signal, and performs a redundant comparison operation to be performed by the computer.

[0012] The present disclosure can provide a semiconductor device capable of operating accurately while suppressing propagation of disturbance noise, a control method for the semiconductor device, and a control program. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment.

[0014] Figure 2 is shown in more detail Figure 1 FIG. 2 is a diagram of an AD converter of a semiconductor device shown in FIG.

[0015] Figure 3 is a diagram showing a specific example of the semiconductor device according to the first embodiment.

[0016] Figure 4 is used to explain Figure 3 A diagram of interference noise generated in a semiconductor device shown.

[0017] Figure 5 It is shown Figure 3 A timing diagram of the operation of the semiconductor device is shown.

[0018] Figure 6 is used to explain Figure 3 The waveform diagram of the interference noise generated in the semiconductor device shown.

[0019] Figure 7 It is used to explain Figure 3 A diagram showing a sequential comparison operation of each AD converter provided in the semiconductor device shown.

[0020] Figure 8 is a block diagram showing a configuration example of a semiconductor device according to a second embodiment.

[0021] Fig. 9 is a diagram showing a specific example of the semiconductor device according to the second embodiment.

[0022] Fig.10 is a block diagram showing a configuration example of a semiconductor device according to a third embodiment.

[0023] Fig.11 It is shown Fig.10 A timing diagram of the operation of the semiconductor device is shown.

[0024] Fig.12 is a block diagram showing another configuration example of the semiconductor device according to the third embodiment.

[0025] Fig.13 is a diagram showing a first configuration example of a pre-inspected semiconductor device.

[0026] Fig.14 is used to explain Fig.13 Schematic diagram of the propagation path of interference noise generated in the semiconductor device shown in .

[0027] Fig.15 It is shown in Fig.13 0 is a timing chart of the operation of each AD converter provided in the semiconductor device shown in .

[0028] Fig.16 is used to explain Fig.13 Graph showing a waveform of noise generated in a semiconductor device shown in FIG.

[0029] Fig.17 is a diagram showing a second configuration example of a pre-inspected semiconductor device.

[0030] Fig.18 is used to explain Fig.17 Schematic diagram of the propagation path of interference noise generated in the semiconductor device shown in .

[0031] Fig.19 is used to explain Fig.17 Graph showing a waveform of noise generated in a semiconductor device shown in FIG.

[0032] Fig. 20 is a diagram showing a third configuration example of a pre-inspected semiconductor device.

[0033] Fig.21 is used to explain Fig. 20 Schematic diagram of the propagation path of interference noise generated in the semiconductor device shown in .

[0034] Fig. 22 is used to explain Fig. 20 Graph showing a waveform of noise generated in a semiconductor device shown in FIG.

[0035] Fig.23 is used to explain Fig. 20 1 is a diagram showing an ideal sequential comparison operation of an AD converter provided in a semiconductor device as shown in FIG.

[0036] Fig.24 is used to explain Fig. 20 A diagram of a problem occurring in a sequential comparison operation of an AD converter provided in a semiconductor device shown in FIG.

[0037] Fig.25 is a diagram showing a fourth configuration example of a semiconductor device for pre-inspection

[0038] Fig.26 is used to explain Fig.25 A diagram showing an ideal sequential comparison operation of an AD converter provided in a semiconductor device is shown.

[0039] Fig. 27 is used to explain Fig.25 A diagram showing a problem occurring in a sequential comparison operation of an AD converter provided in a semiconductor device. DETAILED DESCRIPTION

[0040] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The accompanying drawings are simplified, and therefore, the technical scope of the embodiments should not be narrowly interpreted based on the description in the accompanying drawings. The same reference numerals are assigned to the same elements, and redundant descriptions are omitted.

[0041] For convenience, the following embodiments may be divided into a plurality of parts or embodiments when necessary. However, unless otherwise specified, they are not unrelated to each other, and one embodiment may be part or all of a modification example, an application example, a detailed description, a supplementary description, etc. of another embodiment. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, amounts, ranges, etc.) is not limited to a specific number, but may be not less than or equal to a specific number, except where the number is clearly indicated and is clearly limited to a specific number in principle.

[0042] Furthermore, in the following embodiments, constituent elements (including operation steps, etc.) are not necessarily essential except in the case where they are specifically specified and in the case where they are considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is assumed that the shape, etc. is substantially approximated or similar to the shape, etc. except in the case where they are specifically specified and in the case where they are considered to be obvious in principle, etc. The same applies to the above-mentioned numbers, etc., including numerals, values, amounts, ranges, etc.

[0043] <Preliminary Study by the Inventor>

[0044] Before describing the semiconductor device according to the present embodiment, a semiconductor device that the inventors et al. have preliminarily studied will be described.

[0045] Fig.13 is a diagram showing a configuration example of a semiconductor device 5 that is preliminarily studied. The semiconductor device 5 is, for example, an MCU (microcontroller unit) equipped with a plurality of AD converters. Fig.13 In the example of FIG. 5 , the semiconductor device is provided with two AD converters 51 , 52 on a chip 50 . The semiconductor device 5 is also provided with a plurality of pins, which serve as an interface between the chip 50 and the outside of the semiconductor device 5 .

[0046] The pin AVCC is supplied with a common high potential side power supply voltage (hereinafter referred to as power supply voltage AVCC) for the AD converters 51 and 52 from the outside of the semiconductor device 5. The pin AVSS is supplied with a common low potential side power supply voltage (hereinafter referred to as power supply voltage AVSS) for the AD converters 51 and 52 from the outside of the semiconductor device 5. In other words, the AD converters 51 and 52 share the pins AVCC and AVSS.

[0047] The pin VREFH is supplied with a common high potential side reference voltage (hereinafter referred to as reference voltage VREFH) for the AD converters 51 and 52 from the outside of the semiconductor device 5. The pin AVSS is supplied with a common low potential side reference voltage (hereinafter referred to as reference voltage VREFL) for the AD converters 51 and 52 from the outside of the semiconductor device 5. In other words, the AD converters 51 and 52 share the pins VREFH and VREFL.

[0048] Here, parasitic inductance L51 is formed on the signal line connected to pin AVCC through a circuit board substrate, a lead frame, a bonding wire, etc. (all not shown). Similarly, parasitic inductance L52 is formed on the signal line connected to pin VREFH. Parasitic inductance L53 is formed on the signal line connected to pin VREFL. Parasitic inductance L54 is formed on the signal line connected to pin AVSS.

[0049] One differential input signal and the other differential input signal of the differential input signal IN1 which are analog and AD-converted by the AD converter 51 are respectively supplied to the pins INP1 and INN1 from the outside of the semiconductor device 5. One differential input signal and the other differential input signal of the differential input signal IN2 which are analog and AD-converted by the AD converter 52 are respectively supplied to the pins INP2 and INN2 from the outside of the semiconductor device 5.

[0050] At pin OUT1, a digital output signal (hereinafter referred to as output signal OUT1) as a result of AD conversion by AD converter 51 is output to the outside of semiconductor device 5. At pin OUT2, a digital output signal (hereinafter referred to as output signal OUT2) as a result of AD conversion by AD converter 52 is output to the outside of semiconductor device 5.

[0051] The AD converter 51 is a charge redistribution type successive approximation AD converter, which converts the analog differential input signal IN1 into a digital output signal OUT1 using a binary search algorithm and outputs it. The AD converter 51 is configured to perform AD conversion based on the difference between the reference voltages VREFH and VREFL of the differential input signal IN1, so it can improve the power supply voltage AVCC, AVSS fluctuation elimination rate.

[0052] The AD converter 51 performs continuous comparison operations on the input signal IN1 while redistributing the charge stored in each of the plurality of capacitance elements based on the potential of the input signal IN1 and the reference voltages VREFH and VREFL by switching the connection of the plurality of capacitance elements by a plurality of switches.

[0053] Among the multiple terminals provided in the AD converter 51, the reference voltage VREFH is provided to the terminal VH1. The power supply voltage AVCC is provided to the terminal VH2. The reference voltage VREFL is provided to the terminal VL1. The power supply voltage AVSS is provided to the terminal VL2. The power supply voltages AVCC and AVSS are used to drive the AD converter 51, and the reference voltages VREFH and VREFL are used in the sequential comparison operation of the AD converter 51.

[0054] Like AD converter 51, AD converter 52 is a charge redistribution type successive approximation AD converter, which converts analog differential input signal IN2 into digital output signal OUT2 using a binary search algorithm and outputs it. AD converter 52 is configured to perform AD conversion based on the difference between reference voltages VREFH and VREFL of differential input signal IN2, so it can improve the power supply voltage AVCC, AVSS fluctuation elimination rate.

[0055] The AD converter 52 performs continuous comparison operations for the input signal IN2 while redistributing the charge stored in each of the plurality of capacitors based on the potential of the input signal IN1 and the reference voltages VREFH and VREFL by switching the connection of the plurality of capacitors by a plurality of switches.

[0056] Among the multiple terminals provided in the AD converter 52, the reference voltage VREFH is provided to the terminal VH1. The power supply voltage AVCC is provided to the terminal VH2. The reference voltage VREFL is provided to the terminal VL1. The power supply voltage AVSS is provided to the terminal VL2. The power supply voltages AVCC and AVSS are used to drive the AD converter 52, and the reference voltages VREFH and VREFL are used in the sequential comparison operation of the AD converter 52.

[0057] Fig.14 1 is a diagram for explaining a propagation path of disturbance noise generated in the semiconductor device 5 . Fig.15 is a timing chart showing the operation of each AD converter provided in the semiconductor device 5 . Fig.16 is a waveform diagram for explaining noise generated in the semiconductor device 5 .

[0058] Generally, it is known that in an inductance such as the parasitic inductances L51 to L54 , impedance greatly changes due to a sudden change in current.

[0059] Here, for example, in the AD converter 52, it is assumed that the capacitance switching of the sequential comparison operation is performed asynchronously with the AD converter 51 (see Fig.15 ). At this time, at the terminals VH1 and VL1 of the AD converter 52 (terminals to which the reference voltages VREFH and VREFL are supplied), the current changes due to the charging and discharging caused by the capacitor switching. In particular, in the comparison operation for determining the value of the high bit of the digital output signal OUT2, since the large capacitor switching is performed, the current change due to the charging and discharging becomes rapid. When such a rapid change in the current at the terminals VH1 and VL1 of the AD converter 52 is sent to the parasitic inductances L52 and L53, the impedance of the parasitic inductances L52 and L53 changes greatly (see Fig.16 ). Therefore, the reference voltages VREFH and VREFL supplied to the terminals VH1 and VL1 of the AD converter 51 will also vary greatly (see Fig.16 ). In other words, the noise generated at the terminals VH1, VL1 of the aggressor AD converter 52 is transmitted to the terminals VH1, VL1 of the victim AD converter 51. Therefore, the AD converter 51 may no longer be able to operate accurately.

[0060] Therefore, the present inventors have next considered the semiconductor device 6 .

[0061] Fig.17 is a diagram showing a configuration example of a semiconductor device 6 of pre-inspection. Compared with the semiconductor device 5, the semiconductor device 6 further includes a bypass capacitor C51 on the chip 50. The bypass capacitor C51 is provided within the chip 50 between a common signal line through which a reference voltage VREFH is propagated for the AD converters 51, 52 and a common signal line through which a reference voltage VREFL is propagated for the AD converters 51, 52. The capacitance value of the bypass capacitor C51 is, for example, about 100 pF to 1 nF. The other configurations of the semiconductor device 6 are the same as those of the semiconductor device 5, and therefore their description is omitted.

[0062] Fig.18 1 is a diagram for explaining a propagation path of disturbance noise generated in the semiconductor device 6 . Fig.19 is a waveform diagram for explaining noise generated in the semiconductor device 6 .

[0063] In the semiconductor device 6, as in the case of the semiconductor device 5, the current changes abruptly at the terminals VH1, VL1 of the AD converter 52 due to the charging and discharging of the capacitance caused by the sequential comparison operation. However, in the semiconductor device 6, the change of the current flowing through each of the parasitic inductances L52, L53 is suppressed by the bypass capacitor C51, so the change of the impedance of each of the parasitic inductances L52, L63 becomes small (see Fig.19 ). Therefore, the reference voltage VREFH, VREFL supplied to each of the terminals VH1, VL1 of the AD converter 51 is suppressed (see Fig.19 ). In other words, propagation of noise generated at each of the terminals VH1, VL1 of the AD converter 52 as the aggressor to the terminals VH2, VL1 of the AD converter 51 as the victim is suppressed. Therefore, the AD converter 51 can operate accurately.

[0064] However, in the semiconductor device 6, since the scale of the bypass capacitor C51 is large, the chip size increases.

[0065] Therefore, the present inventors have next considered the semiconductor device 7 .

[0066] Fig. 20 1 is a diagram showing a configuration example of a pre-inspected semiconductor device 7. The semiconductor device 7 includes resistor elements R51, R52, R61, R62 on a chip 50 instead of the bypass capacitor C51, and the scale of these resistor elements is smaller than that of the bypass capacitor C51 compared with the semiconductor device 6.

[0067] The resistance element R51 is provided on a signal line branched from a signal line shared with the AD converter 52 among signal lines between the pin VREFH and the terminal VH1 of the AD converter 51. The resistance element R52 is provided on a signal line branched from a signal line shared with the AD converter 52 among signal lines between the pin VREFL and the terminal VL1 of the AD converter 51. The resistance element R61 is provided on a signal line branched from a signal line shared with the AD converter 51 among signal lines between the pin VREFH and the terminal VH1 of the AD converter 52. The resistance element R62 is provided on a signal line branched from a signal line shared with the AD converter 51 among signal lines between the pin VREFL and the terminal VL1 of the AD converter 52. The other configurations of the semiconductor device 7 are the same as those of the semiconductor device 6, and therefore their descriptions are omitted. Therefore, the semiconductor device 7 can suppress an increase in circuit scale compared with the semiconductor device 6.

[0068] Fig.21 2 is a diagram for explaining a propagation path of disturbance noise generated in the semiconductor device 7 . Fig. 22 is a waveform diagram for explaining noise generated in the semiconductor device 7 .

[0069] In the semiconductor device 7, as in the case of the semiconductor device 5, the current suddenly changes at the terminals VH1, VL1 of the AD converter 52 due to the charging and discharging of the capacitance caused by the sequential comparison operation. However, in the semiconductor device 7, the change of the current flowing through each of the parasitic inductances L52, L53 is suppressed due to the resistance elements R51, R52, R61, R62, thereby reducing the change of the impedance of each of the parasitic inductances L52, L63 (refer to Fig. 22 ). Therefore, fluctuation of the reference voltage VREFH, VREFL supplied to each of the terminals VH1, VL1 of the AD converter 51 is suppressed (reference voltage Fig. 22 ). In other words, the propagation of the noise generated at each of the terminals VH1, VL1 of the AD converter 52 as the aggressor to the terminals VH2, VL1 of the AD converter 51 as the victim is suppressed. However, due to the IR drop caused by the resistance elements R61, R62, the reference voltage VREFH, VREFL supplied to each of the terminals VH1, VL1 of the AD converter 52 as the aggressor fluctuates greatly (see Fig. 22 ). Therefore, the AD converter 52 cannot operate accurately.

[0070] Fig.23 7 is a diagram for explaining an ideal sequential comparison operation of an AD converter provided in the semiconductor device 7. Fig.23In the example of FIG. 5 , the AD converter 52 converts the analog input signal IN2 into a 4-bit wide digital output signal OUT2 and outputs it.

[0071] First, the AD converter 52 samples the input signal IN2 and holds the sampled input signal IN2.

[0072] Next, the AD converter 52 performs a sequential comparison operation on the input signal IN1 while redistributing the charge accumulated in each of the multiple capacitor elements based on the potential of the input signal IN2 and the reference voltages VREFH, VREFL (hereinafter collectively referred to as the reference voltage VREF) by switching the connection of the multiple capacitor elements using multiple switches.

[0073] First, the AD converter 52 performs a comparison operation to determine the value of the most significant bit (MSB) of the 4 bits representing the output signal OUT2. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA conversion value of the digital value 4b'1000 set to "1" for the most significant bit. If the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "1", and if the potential of the input signal IN2 is less than the DA conversion value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "0". Fig.23 In the example of , since the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is determined to be "1".

[0074] Subsequently, the AD converter 52 performs a comparison operation by switching the connection of the capacitive elements with a switch and redistributing the charge to determine the value of the second highest bit (the second bit from the top) of the output signal OUT2. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA conversion value of the digital value 4b'1100 set to "1" for the second highest bit. If the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1100, the second highest bit of the output signal OUT2 is determined to be "1", and if the potential of the input signal IN2 is less than the DA conversion value of the digital value 4b'1100, the second highest bit of the output signal OUT2 is determined to be "0". Fig.23 In the example of , since the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1100, the second highest bit of the output signal OUT2 is determined to be "1".

[0075] Subsequently, the AD converter 52 performs a comparison operation by switching the connection of the capacitor elements with a switch and redistributing the charge to determine the value of the third highest bit (the third bit from the top) of the output signal OUT2. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA conversion value of the digital value 4b'1110, where the third highest bit is set to "1". If the potential of the input signal IN2 is equal to or greater than the digital value 4b'1110, the upper third of the bits of the output signal OUT2 are confirmed as "1". If the potential of the input signal IN2 is less than the DA conversion value of the digital value 4b'1110, the upper third of the bits of the output signal OUT2 are confirmed as "0". Fig.23 In the example of FIG. 4 , the upper third bits of the output signal OUT2 are confirmed as “0” because the potential of the input signal IN2 is smaller than the DA conversion value of the digital value 4b′1110.

[0076] Subsequently, the AD converter 52 performs a comparison operation by switching the connection of the capacitor elements and redistributing the charges to determine the value of the fourth highest bit (least significant bit) of the output signal OUT2. Specifically, the AD converter 52 compares the potential of the sampled input signal IN2 with the DA conversion value of the digital value 4b'1011, where the least significant bit is set to "1". If the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1011, the least significant bit of the output signal OUT2 is confirmed to be "1". If the potential of the input signal IN2 is less than the DA conversion value of the digital value 4b'1011, the least significant bit of the output signal OUT2 is confirmed to be "0". Fig.23 In the example of FIG. 4 , the least significant bit of the output signal OUT2 is confirmed to be “0” because the potential of the input signal IN2 is smaller than the DA conversion value of the digital value 4b′1101.

[0077] Therefore, the AD converter 52 ideally converts the analog input signal IN2 into AD and outputs the output signal OUT2 having a digital value of 4b'1100.

[0078] Fig.24 1 is a diagram for explaining a problem that occurs in a sequential comparison operation of an AD converter provided in the semiconductor device 7. Fig.24 In the example shown in FIG. 5 , the AD converter 52 converts the analog input signal IN2 into a digital output signal OUT2 having a width of 4 bits and outputs it.

[0079] like Fig.24As shown, after confirming the most significant bit of the output signal OUT2, the AD converter 52 performs a comparison operation by switching the connection of the capacitor element and redistributing the charge to determine the value of the second highest bit of the output signal OUT1. Here, due to the IR drop caused by the resistor elements R61 and R62, the reference voltages VREFH and VREFL provided to the AD converter 52 fluctuate greatly as the connection of the capacitor elements is switched. Therefore, the AD converter 52 may generate a comparison error due to a setting error. Fig.24 In the example of , although the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1100, the potential of the input signal IN1 is judged to be less than the DA conversion value of the digital value 4b'1100. Therefore, the second highest bit of the output signal OUT2 is erroneously confirmed as "0".

[0080] Therefore, the AD converter 52 erroneously converts the analog input signal IN2 into AD, and outputs the output signal OUT2 having a digital value of 4b'1011.

[0081] Therefore, the present inventors have next considered the semiconductor device 8 .

[0082] Fig.25 7 is a diagram showing a configuration example of a semiconductor device 8 that has been preliminarily considered. Compared with the semiconductor device 7, the semiconductor device 8 is equipped with AD converters 61 and 62 instead of the AD converters 51 and 52. Each of the AD converters 61 and 62 is configured to also include a redundant comparison operation in the sequential comparison operation. Therefore, even if each of the AD converters 61 and 62 generates a comparison error due to the fluctuation of the reference voltages VREFH and VREFL caused by the IR drop of the resistor elements R51, R52, R61, and R62, the comparison error can be recovered by the redundant comparison.

[0083] Fig.26 8 is a diagram for explaining an ideal sequential comparison operation of an AD converter provided in the semiconductor device 8. Fig.26 In the example shown in FIG. 6 , the AD converter 62 converts the analog input signal IN2 into a digital output signal OUT2 having a width of 4 bits and outputs it.

[0084] like Fig.26As shown, after confirming the most significant bit of the output signal OUT2, the AD converter 62 performs a comparison operation by switching the connection of the capacitor element and redistributing the charge to determine the value of the second bit of the output signal OUT2. Here, due to the IR drop caused by the resistor elements R61 and R62, the reference voltages VREFH and VREFL provided to the AD converter 52 fluctuate greatly as the connection of the capacitor elements is switched. Therefore, the AD converter 62 may generate a comparison error due to a setting error. Fig.26 In the example of FIG. 1 , although the potential of the input signal IN2 is equal to or greater than the DA-converted value of the digital value 4b'1100, the potential of the input signal IN1 is determined to be less than the DA-converted value of the digital value 4b'1100. Therefore, the second upper bit of the output signal OUT2 is erroneously determined to be "0".

[0085] Here, the AD converter 62 performs a redundant comparison operation having the same resolution as the comparison operation 24 for determining the value of the third highest bit of the output signal OUT2 by switching the connection of the capacitive elements and distributing the charge after the comparison operation for determining the value of the third highest bit of the output signal OUT2.

[0086] Specifically, in the comparison operation for determining the value of the third upper bit of the output signal OUT2, when the potential of the input signal IN2 is determined to be equal to or greater than the DA conversion value of the comparison target digital value, the AD converter 62 performs a comparison between the potential of the input signal IN1 and the DA conversion value of the digital value obtained by adding 4'b0010 to the comparison target digital value in the next redundant comparison operation. In addition, in the comparison operation for determining the value of the third upper bit of the output signal OUT2, when it is determined that the potential of the input signal IN2 is less than the DA conversion value of the comparison target digital value, the AD converter 62 performs a comparison between the DA conversion value of the digital value obtained by subtracting 4'b0010 from the comparison target digital value and the potential of the input signal IN1 in the next redundant comparison operation.

[0087] exist Fig.26 In the example, the AD converter 62 has determined that the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4'b1010 in the comparison operation for determining the value of the third highest bit of the output signal OUT2, and therefore in the next redundant comparison operation, the potential of the input signal IN1 is compared with the digital value 4'b1100 obtained by adding 4'b0010 to the digital value 4'b1010.

[0088] Then, in Fig.26In the example of , the potential of the input signal IN2 is determined to be equal to or greater than the DA conversion value of the digital value 4'b1100. Therefore, in the comparison operation for determining the value of the lowest bit, the AD converter 62 compares the DA conversion value of the digital value obtained by adding 4'b0001 to the comparison target digital value with the potential of the input signal IN2. Specifically, in the comparison operation for determining the value of the lowest bit, the AD converter 62 compares the digital value 4'b1101 obtained by adding 4'b0001 to the digital value 4'b1100 with the potential of the input signal IN2. The comparison operation for determining the value of the lowest bit by the AD converter 62 is the same as in the case of the AD converter 52.

[0089] Note that if the potential of the input signal IN2 is determined to be smaller than the DA conversion value of the digital value 4′b1100, the AD converter 62 compares the DA conversion value of the digital value obtained by subtracting 4′b00001 from the comparison target digital value with the potential of the input signal IN1.

[0090] In this way, ideally, the AD converter 62 can recover from the comparison error caused by the fluctuation of the reference voltages VREFH and VREFL due to the IR drop of the resistors R61 and R62 through the redundant comparison. The same applies to the AD converter 61.

[0091] However, actually, even in the redundant comparison operation, the AD converter 62 may generate a comparison error due to the fluctuation of the reference voltages VREFH and VREFL caused by the IR drop of the resistors R61 and R62 (see FIG. Fig. 27 ).

[0092] Therefore, a semiconductor device 1 capable of operating accurately while suppressing the propagation of disturbance noise has been found.

[0093] <First Embodiment>

[0094] Figure 1 1 is a block diagram showing a configuration example of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is, for example, an MCU equipped with a plurality of AD converters. In this embodiment, the semiconductor device 1 is described as an example in which two AD converters 11 and 12 are equipped on a chip 10.

[0095] Specifically, the semiconductor device 1 includes AD converters 11, 12, control circuits 13, 14, variable impedance circuits Z11, Z12, and variable impedance circuits Z21, Z22 on a chip 10. In addition, the semiconductor device 1 is provided with a plurality of pins that perform an interface between the chip 10 and the outside of the semiconductor device 1.

[0096] The pin AVCC is supplied with a common high potential side power supply voltage (hereinafter referred to as power supply voltage AVCC) for the AD converters 11 and 12 from the outside of the semiconductor device 1. The pin AVSS is supplied with a common low potential side power supply voltage (hereinafter referred to as power supply voltage AVSS) for the AD converters 11 and 12 from the outside of the semiconductor device 1. In other words, the AD converters 11 and 12 share the pins AVCC and AVSS.

[0097] The pin VREFH is supplied with a common high potential side reference voltage (hereinafter referred to as reference voltage VREFH) for the AD converters 11 and 12 from the outside of the semiconductor device 1. The pin VREFL is supplied with a common low potential side reference voltage (hereinafter referred to as reference voltage VREFL) for the AD converters 11 and 12 from the outside of the semiconductor device 1. In other words, the AD converters 11 and 12 share the pins VREFH and VREFL.

[0098] Parasitic inductance L1 is formed on the signal line connected to pin AVCC through the circuit board substrate, lead frame, bonding wire, etc. (all not shown). Similarly, parasitic inductance L2 is formed on the signal line connected to pin VREFH. Parasitic inductance L3 is formed on the signal line connected to pin VREFL. Parasitic inductance L4 is formed on the signal line connected to pin AVSS.

[0099] Pins INP1 and INN1 are respectively supplied with one analog differential input signal and the other analog differential input signal of analog differential input signal IN1 AD-converted by AD converter 11 from the outside of semiconductor device 1. Pins INP2 and INN2 are respectively supplied with one analog differential input signal and the other analog differential input signal of analog differential input signal IN2 AD-converted by AD converter 12 from the outside of semiconductor device 1.

[0100] At pin OUT1, a digital output signal (hereinafter referred to as output signal OUT1) as a result of AD conversion by the AD converter 11 is output to the outside of the semiconductor device 1. At pin OUT2, a digital output signal (hereinafter referred to as output signal OUT2) as a result of AD conversion by the AD converter 12 is output to the outside of the semiconductor device 1.

[0101] The AD converter 11 is a charge redistribution type successive approximation AD converter, and uses a binary search algorithm to output the analog differential input signal IN1 as a digital output signal OUT1 based on the difference between the reference voltages VREFH and VREFL. Since the AD converter 11 is configured to perform AD conversion based on the difference between the reference voltages VREFH and VREFL of the differential input signal IN1, it can improve the power supply voltage AVCC and AVSS fluctuation elimination rate. In addition, the AD converter 11 is configured to further include a redundant comparison operation in the sequential comparison operation.

[0102] Among the multiple terminals provided in the AD converter 11, the terminal VH1 is provided with a reference voltage VREFH. The terminal VH2 is provided with a power supply voltage AVCC. The terminal VL1 is provided with a reference voltage VREFL. The terminal VL2 is provided with a power supply voltage AVSS. The power supply voltages AVCC and AVSS are used to drive the AD converter 11, and the reference voltages VREFH and VREFL are used as the basis for the sequential comparison operation of the AD converter 11.

[0103] Figure 2 1 is a diagram showing a specific configuration example of the AD converter 11. The AD converter 11 includes a DA converter 111, a comparator 112, and a sequential comparison register circuit 113. The DA converter 111 is composed of a DA converter 111u provided on the INP1 side of one input signal of the differential input signal IN1 and a DA converter 111d provided on the INN1 side of the other input signal of the differential value input signal IN2. The DA converter 111u includes: capacitance elements Cu0, Cu1 indicating a minimum capacitance value 2^0·C; n-1 (where n is an integer of 2 or more) capacitance elements Cu2 to Cun, which are binary weighted relative to the capacitance value of the capacitance element Cu1; a redundant capacitance element Cur indicating the same capacitance value 2^(k-1)·C (where k is any one of 1 to n) as the capacitance element Cuk; and switches Su0, Su1 to Sun, Sur provided corresponding to each of the capacitance elements Cu0, Cu1 to Cun, Cur. The DA converter 111d includes: capacitor elements Cd0 and Cd1 indicating a minimum capacitance value of 2^0·C; n-1 (where n is an integer of 2 or more) capacitor elements Cd2 to Cdn, which are binary weighted relative to the capacitance value of the capacitor element Cd1; a redundant capacitor element Cdr indicating the same capacitance value 2^(k-1)·C (where k is any one of 1 to n) as the capacitor element Cdk; and switches Sd0, Sd1 to Sdn, Sdr provided corresponding to each of the capacitor elements Cd0, Cd1 to Cdn, Cdr. The DA converter 111 also has a function of sampling and holding the potential of the input signal IN1.

[0104] The AD converter 11 uses a comparator 112 and a sequential comparison register circuit 113 to perform a sequential comparison operation between the output of the DA converter 111 and the potential of the input signal IN1, while switching the connection of multiple capacitor elements through multiple switches, and redistributing the charge accumulated in each of the multiple capacitor elements based on the potential of the input signal IN1 in the DA converter 111 and the reference voltages VREFH and VREFL.

[0105] The variable impedance circuit Z11 is provided on a signal line branched from a signal line shared with the AD converter 12, between the pin VREFH and the terminal VH1 of the AD converter 11. For example, the variable impedance circuit Z11 includes m (where m is an integer of 2 or more) signal lines Z11_1 to Z11_m having different impedances, and a switch SW11 that selects any one of the m signal lines Z11-Z11_m based on a control signal from the control circuit 13.

[0106] The variable impedance circuit Z12 is provided on a signal line branched from a signal line shared with the AD converter 12, between the pin VREFL and the terminal VL1 of the AD converter. For example, the variable impedance circuit Z12 includes m (where m is an integer of 2 or more) signal lines Z12_1 to Z12_m having different impedances, and a switch SW12 for selecting any one of the m signal lines Z11_Z12_m based on a control signal from the control circuit 13.

[0107] The control circuit 13 controls the operation of the AD converter 11 and the impedance of each of the variable impedance circuits Z11 , Z12 .

[0108] The AD converter 12 is a charge redistribution type sequential comparison type AD converter, which converts the analog differential input signal IN2 into a digital output signal OUT2 based on the difference of the reference voltages VREFH and VREFL using a binary search algorithm. The AD converter 12 is configured to perform AD conversion based on the difference of the reference voltages VREFH and VREFL of the differential input signal IN2, thereby improving the power supply voltage AVCC and AVSS rejection rate.

[0109] Furthermore, the AD converter 12 is configured to include a redundant comparison operation in the sequential comparison operation.

[0110] Among the multiple terminals provided in the AD converter 12, the terminal VH1 is provided with a reference voltage VREFH. The terminal VH2 is provided with a power supply voltage AVCC. The terminal VL1 is provided with a reference voltage VREFL. The terminal VL2 is provided with a power supply voltage AVSS. The power supply voltages AVCC and AVSS are used to drive the AD converter 12, and the reference voltages VREFH and VREFL are used as the basis for the sequential comparison operation of the AD converter 12.

[0111] The specific configuration of the AD converter 12 is the same as that of the AD converter 11 , and thus the description is omitted.

[0112] The variable impedance circuit Z21 is provided on a signal line branched from a signal line shared with the AD converter 11, between the pin VREFH and the terminal VH1 of the AD converter. For example, the variable impedance circuit Z21 includes m (where m is an integer of 2 or more) signal lines Z21_1 to Z21_m having different impedances, and a switch SW21 that selects any one of the m signal lines Z21-Z21_m based on a control signal from the control circuit 14.

[0113] The variable impedance circuit Z22 is provided in a signal line branched from a signal line common to the AD converter 11 among signal lines between the pin VREFL and the terminal VL1 of the AD converter 12. For example, the variable impedance circuit Z22 includes m signal lines Z22_1 to Z22_m having different impedances, and a switch SW22 that selects any one of the m signal lines based on a control signal from the control circuit 14.

[0114] The control circuit 14 controls the operation of the AD converter 12 and the impedance of each of the variable impedance circuits Z21 and Z22 .

[0115] (Example of Semiconductor Device 1)

[0116] Figure 3 1 is a diagram showing an example of a semiconductor device 1 as a semiconductor device 1a. Figure 3 As shown, compared with the semiconductor device 1 , the semiconductor device 1 a includes variable resistance circuits R11 , R12 , R21 , and R22 as examples of variable impedance circuits Z11 , Z12 , Z21 , and Z22 .

[0117] The variable resistor circuit R11 is configured to be able to change the resistance value of a signal line branched from a signal line shared with the AD converter 12 among the signal lines between the pin VREFH and the terminal VH1 of the AD converter 11, according to a control signal from the control circuit 13. The variable resistor circuit R12 is configured to be able to change the resistance value of a signal line branched from a signal line shared with the AD converter 12 among the signal lines between the pin VREFL and the terminal VL1 of the AD converter 11, according to a control signal from the control circuit 13. The variable resistor circuit R21 is configured to be able to change the resistance value of a signal line branched from a signal line shared with the AD converter 11 among the signal lines between the pin VREFH and the terminal VH1 of the AD converter 12, according to a control signal from the control circuit 14. The variable resistor circuit R22 is configured to be able to change the resistance value of a signal line branched from a signal line shared with the AD converter 11 among the signal lines between the pin VREFL and the terminal VL1 of the AD converter 12, according to a control signal from the control circuit 14.

[0118] The other configurations of the semiconductor device 1 a are the same as those of the semiconductor device 1 , and thus their descriptions are omitted.

[0119] Figure 4 1 is a diagram for explaining a propagation path of disturbance noise generated in the semiconductor device 1 a . Figure 5 is a timing chart showing the operation of the semiconductor device 1 a . Figure 6 is a waveform diagram for explaining noise generated in the semiconductor device 1 a .

[0120] In general, it is well known that the impedance of an inductance such as parasitic inductances L1 to L4 may vary greatly due to a sudden change in current.

[0121] Here, for example, it is assumed that in the AD converter 12, the capacitance switching of the sequential comparison operation is performed asynchronously with the AD converter 11. At this time, at the terminals VH1 and VL1 (terminals to which the reference voltages VREFH and VREFL are provided) of the AD converter 12, the current changes due to the charging and discharging caused by the capacitance switching. In particular, in the comparison operation for determining the high-bit value of the digital output signal OUT2, because a large capacitance switching is performed, the current change due to the charging and discharging becomes sharp. When such a sharp current change at the terminals VH1 and VL1 of the AD converter 12 is sent to the parasitic inductances L2 and L3, the impedance of the parasitic inductances L2 and L3 changes greatly. Therefore, the reference voltages VREFH and VREFL provided to the terminals VH1 and VL1 of the AD converter 11 also change greatly. In other words, the noise generated at the terminals VH1 and VL1 of the aggressor AD converter 12 is sent to the terminals VH1 and VL1 of the victim AD converter 11. Therefore, the AD converter 11 cannot operate accurately.

[0122] Therefore, in the semiconductor device 1a, in the comparison operation for determining the value of the high bit of the output signal OUT2, since the current change caused by the capacitor switching is sudden and the interference noise may become large, the resistance value of the variable resistance circuits R21 and R22 increases. Therefore, the change of the current flowing through each of the parasitic inductances L2 and L3 is suppressed, resulting in a decrease in the impedance change of each of the parasitic inductances L2 and L3 (see Figure 6 ). Therefore, the fluctuation of the reference voltage VREFH, VREFL supplied to each of the terminals VH1, VL1 of the AD converter 11 is suppressed (see Figure 6 ). In other words, propagation of noise generated at each of the terminals VH1 , VL1 of the AD converter 12 as the aggressor to the terminals VH1 , VL1 of the AD converter 11 as the victim is suppressed.

[0123] However, since the resistance value of each of the variable resistance circuits R21, R22 is large, the reference voltage VREFH, VREFL supplied to each of the terminals VH1, VL1 of the AD converter 12 as the attacker fluctuates greatly due to IR drop (see Figure 6 ). Therefore, the AD converter 12 may cause a comparison error in the comparison operation for determining the value of the upper bit of the output signal OUT2.

[0124] Therefore, in the semiconductor device 1a, in the comparison operation for determining the value of the lower bit of the output signal OUT2 (the remaining bits except the upper bit within a certain range), the change in the current due to the capacitor switching is small and the interference noise is small, and in the redundant comparison operation for re-determining any one of the multiple bits representing the output signal OUT2, the resistance value of each variable resistance circuit in the variable resistance circuits R21, R22 is set lower than that in the comparison operation for determining the value of the upper bit. In the redundant comparison operation, in the redundant comparison operation, the resolution of the comparison is equal to or greater than the resolution of the comparison operation for determining the value of the lowest bit among the comparison operations for determining the value of the upper bit within a certain range including the highest bit (the weight of the binary search is equal to or less than this value). In other words, the resolution of the comparison is equal to or greater than the resolution of the comparison operation performed in a state where the resistance value of each variable resistance circuit in the variable resistance circuits R21, R22 is set to high (the weight of the binary search is equal to or less than this value).

[0125] Therefore, the IR drop caused by the variable resistance circuits R21, R22 is suppressed, and the fluctuation of the reference voltages VREFH, VREFL supplied to each of the terminals VH1, VL1 of the AD converter 12 as the attacker is suppressed (see Figure 6 ). Therefore, the AD converter 12 can accurately perform the comparison operation for determining the lower bit value and the redundant comparison operation.

[0126] In the present embodiment, although the case where AD converter 12 serves as an attacker and AD converter 11 serves as a victim is described as an example, the case where AD converter 11 serves as an attacker and AD converter 12 serves as a victim is also the same.

[0127] That is, in the comparison operation for determining the value of the high bit of the output signal OUT1, the semiconductor device 1a having a fast current change due to capacitor switching and easily generating interference noise increases the resistance value of each of the variable resistance circuits R11 and R12 to suppress the interference noise. In addition, in the comparison operation for determining the value of the low bit of the output signal OUT1, the semiconductor device 1a having a slow current change due to capacitor switching and less likely to generate interference noise sets the resistance value of each of the variable resistance circuits R11 and R12 to be lower than that in the comparison operation for determining the value of the high bit in the redundant comparison operation to suppress the IR drop.

[0128] Therefore, in the semiconductor device 1a, each of the AD converters 11 and 12 can operate accurately while suppressing the propagation of interference noise. The control circuits 13 and 14 can appropriately change the resistance value set in each of the variable resistance circuits R11, R12, R21, and R22 according to the operating environment, etc.

[0129] Figure 7 1 is a diagram for explaining a sequential comparison operation of an AD converter provided in a semiconductor device 1a. Figure 7 In the example of FIG. 1 , the AD converter 12 converts the analog input signal IN2 into a 4-bit wide digital output signal OUT2 and outputs it.

[0130] First, the AD converter 12 samples the input signal IN2 and holds the sampled input signal IN2.

[0131] Next, the AD converter 12 performs a sequential comparison operation on the input signal IN2 while redistributing the charge stored in each of the multiple capacitor elements based on the potential of the input signal IN2 and the reference voltages VREFH, VREFL (hereinafter collectively referred to as the reference voltage VREF) by switching the connection of the multiple capacitor elements using multiple switches.

[0132] In the initial state, since the current change caused by the capacitance switching is rapid and interference noise may occur, the variable resistance circuits R11, R12, R21, and R22 are set to high resistance values. This suppresses the interference noise.

[0133] First, the AD converter 12 performs a comparison operation to determine the value of the most significant bit (MSB) of the 4 bits representing the output signal OUT2. Specifically, the AD converter 12 compares the potential of the sampled input signal IN2 with the DA conversion value of the digital value 4b'1000 with the most significant bit set to "1". If the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is confirmed to be "1". If the potential of the input signal IN2 is less than the DA conversion value of the digital value 4b'1000, the most significant bit of the output signal OUT2 is confirmed to be "0". Figure 7 In the example of , since the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1000, it is confirmed that the highest bit of the output signal OUT2 is "1".

[0134] Subsequently, the AD converter 12 performs a comparison operation by switching the connection of the capacitive element with a switch and redistributing the charge to determine the value of the second highest bit of the output signal OUT2. Specifically, the AD converter 12 compares the potential of the sampled input signal IN2 with the DA conversion value of the digital value 4b'1100 that sets the second highest bit to "1". If the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1100, it is confirmed that the second highest bit of the output signal OUT2 is "1", and if the potential of the input signal IN2 is less than the DA conversion value of the digital value 4b'1100, it is confirmed that the second highest bit of the output signal OUT2 is "0".

[0135] However, since the resistance values ​​of the variable resistor circuits R21 and R22 are high, the reference voltages VREFH and VREFL provided to the AD converter 12 fluctuate greatly due to IR drop. Therefore, the AD converter 12 may generate a comparison error due to a setting error. Figure 7 In the example of , although the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1100, the potential of the input signal IN2 is judged to be less than the DA conversion value of the digital value 4b'1100. Therefore, the second upper bit of the output signal OUT2 is erroneously confirmed as "0".

[0136] Subsequently, when the current change due to the capacitor switching becomes gentle and the interference noise is less likely to occur, the variable resistance circuits R21, R22 are switched to a low resistance value. Therefore, the IR drop caused by the variable resistance circuits R21, R22 is suppressed, and the fluctuation of the reference voltages VREFH, VREFL supplied to the AD converter 12 is also suppressed. Therefore, the AD converter 12 can accurately perform the comparison operation and the redundant comparison operation for determining the value of the lower bit.

[0137] Subsequently, the AD converter 12 performs a comparison operation by switching the connection of the capacitive element with a switch and redistributing the charge to determine the value of the third highest bit of the output signal OUT2. Specifically, the AD converter 12 compares the potential of the sampled input signal IN2 with the DA conversion value of the digital value 4b'1010 setting the third highest bit to "1".

[0138] Subsequently, the AD converter 12 performs a redundant comparison operation with the same resolution (at least the same or higher resolution (same or lower binary search weight) as the comparison operation for determining the value of the second highest bit) by switching the connection of the capacitive elements with the switch and redistributing the charge. Specifically, in the comparison operation for determining the value of the third highest bit, if the potential of the input signal IN2 is determined to be equal to or greater than the DA conversion value of the digital value to be compared, then in the next redundant comparison operation, the AD converter 12 compares the potential of the input signal IN2 with the DA conversion value of the digital value obtained by adding 4'b0010 to the digital value to be compared. Similarly, in the comparison operation for determining the value of the third highest bit, if the potential of the input signal IN2 is determined to be less than the DA conversion value of the digital value to be compared, then in the next redundant comparison operation, the AD converter 12 compares the potential of the input signal IN2 with the DA conversion value of the digital value obtained by subtracting 4'b0010 from the digital value to be compared.

[0139] exist Figure 7 In the example of , in the comparison operation for determining the value of the third upper bit of the output signal OUT2, because the potential of the input signal IN2 is determined to be equal to or greater than the DA conversion value of the digital value 4'b1010, in the next redundant comparison operation, the AD converter 12 compares the potential of the input signal IN2 with the digital value 4'b1100 obtained by adding 4'b0010 to the digital value 4'b1010.

[0140] Then, in Figure 7 In the example of , the potential of the input signal IN2 is determined to be equal to or greater than the DA conversion value of the digital value 4'b1100. Therefore, in the comparison operation for determining the value of the next least significant bit, the AD converter 62 compares the potential of the input signal IN2 with the digital value 4'b1101 obtained by adding 4'b0001 to the digital value 4'b1100. For example, if the potential of the input signal IN2 is equal to or greater than the DA conversion value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "1", and if the potential of the input signal IN2 is less than the DA conversion value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "0". Figure 7 In the example of , since the potential of the input signal IN2 is smaller than the DA conversion value of the digital value 4b'1101, the least significant bit of the output signal OUT2 is determined to be "0".

[0141] Therefore, the AD converter 12 converts the analog input signal IN2 into a digital signal, and outputs an output signal OUT2 having a digital value 4b'1100.

[0142] In this way, in the comparison operation for determining the value of the higher bit of the output signal OUT1, in which the current change due to the capacitor switching is sharp and interference noise is likely to occur, the semiconductor device 1a increases the resistance value of each of the variable resistance circuits R11, R12 to suppress the interference noise. Similarly, compared with the comparison operation for determining the value of the higher bit, in the comparison operation for determining the value of the lower bit of the output signal OUT1, in which the current change due to the capacitor switching is gentle and interference noise is unlikely to occur, and in the redundant comparison operation, the semiconductor device 1a reduces the resistance value of each of the variable resistance circuits R11, R12 to suppress the IR drop.

[0143] Likewise, in a comparison operation for determining the value of a higher bit of the output signal OUT2, in which the current change due to capacitor switching is sharp and interference noise is likely to occur, the semiconductor device 1a increases the resistance value of each of the variable resistance circuits R21, R22 to suppress interference noise. Likewise, in a comparison operation for determining the value of a lower bit of the output signal OUT2, and in a redundant comparison operation, in which the current change due to capacitor switching is gentle and interference noise is unlikely to occur, the semiconductor device 1a reduces the resistance value of each of the variable resistance circuits R21, R22 to suppress IR drop, compared to a comparison operation for determining the value of a higher bit.

[0144] By doing so, in the semiconductor device 1 a , each of the AD converters 11 , 12 can operate accurately while suppressing the propagation of disturbance noise.

[0145] <Second Embodiment>

[0146] Figure 8 1 is a block diagram showing a configuration example of a semiconductor device 2 according to the second embodiment. While the semiconductor device 1 is provided with two AD converters 11 , 12 , the semiconductor device 2 is provided with one AD converter 11 .

[0147] Specifically, the semiconductor device 2 is equipped with an AD converter 11, a control circuit 13, and variable impedance circuits Z11 and Z12 on a chip 20. In addition, the semiconductor device 2 is provided with at least pins AVCC, AVSS, VREFH, VREFL, INP1, INP2, and OUT1 as interfaces between the chip 20 and the outside of the semiconductor device 2.

[0148] The configurations of the AD converter 11, the control circuit 13, and the variable impedance circuits Z11, Z12 are the same as those in the case of the semiconductor device 1, and thus their descriptions are omitted. Likewise, the connection relationship between the AD converter 11, the control circuit 13, the variable impedance circuits Z11, Z12, and each pin is the same as that in the case of the semiconductor device 1, and thus their descriptions are omitted.

[0149] Here, parasitic inductance L1 is formed on the signal line connected to the pin AVCC through the circuit board substrate, lead frame, bonding wire, etc. (all not shown). Similarly, parasitic inductance L2 is formed on the signal line connected to the pin VREFH. Parasitic inductance L3 is formed on the signal line connected to the pin VREFL. Parasitic inductance L4 is formed on the signal line connected to the pin AVSS.

[0150] (Specific Example of Semiconductor Device 2)

[0151] Fig. 9 2 is a diagram showing a specific example of a semiconductor device 2 as a semiconductor device 2a. Fig. 9 As shown, the semiconductor device 2a includes variable resistance circuits R11, R12 as specific examples of variable impedance circuits Z11, Z12, compared with the semiconductor device 2. Other configurations of the semiconductor device 2a are the same as those of the semiconductor device 2, and thus their descriptions are omitted.

[0152] For example, it is assumed that a capacitance switching operation of a sequential comparison operation is performed in the AD converter 11. At this time, at the terminals VH1 and VL1 of the AD converter 11, the charge and discharge caused by the capacitance switching causes a current change. In particular, in the comparison operation for determining the value of the high bit of the digital output signal OUT1, capacitance switching is performed, so the current change caused by the charge and discharge becomes sharp. When this sharp current change at the terminals VH1 and VL1 of the AD converter 11 is sent to the parasitic inductances L2 and L3, the impedance of the parasitic inductances L2 and L3 changes greatly. Therefore, the noise generated on the signal line on which the reference voltages VREFH and VREFL propagate becomes larger. Therefore, the noise is sent to other circuits (not shown) that share the signal lines on which the reference voltages VREFH and VREFL propagate, and these other circuits cannot operate accurately.

[0153] Therefore, in the semiconductor device 2a, in the comparison operation for determining the value of the high bit of the output signal OUT1, in which the current change caused by the capacitor switching is sharp and interference noise may occur, the resistance value of each variable resistance circuit in the variable resistance circuits R11 and R12 is increased to suppress the interference noise. Similarly, compared with the comparison operation for determining the value of the high bit, in the comparison operation for determining the value of the low bit of the output signal OUT1, in which the current change caused by the capacitor switching is mild and interference noise is unlikely to occur, and in the redundant comparison operation, the semiconductor device 2a reduces the resistance value of each variable resistance circuit in the variable resistance circuits R11 and R12 to suppress IR drop. Therefore, in the semiconductor device 2a, the AD converter 11 can operate accurately while suppressing the propagation of interference noise.

[0154] <Third Embodiment>

[0155] Fig.10 3 is a block diagram showing a configuration example of a semiconductor device 3 according to the third embodiment. Compared with the semiconductor device 2, the semiconductor device 3 includes switches SW31, SW32 instead of the variable impedance circuits Z11, Z12.

[0156] The switch SW31 is provided between the pin VREFH and the pin AVCC and the terminal VH1 of the AD converter 11, and connects the pin VREFH or the pin AVCC to the terminal VH1 of the AD converter 11 according to the control signal from the control circuit 13. The switch SW32 is provided between the pin VREFL and the pin AVSS and the terminal VL1 of the AD converter 11, and connects the pin VREFL or the pin AVSS to the terminal VL1 of the AD converter 11 according to the control signal from the control circuit 13.

[0157] Fig.11 is a timing diagram showing the operation of the semiconductor device 3. First, in a comparison operation for determining the value of the higher bit of the output signal OUT1, in which the current change associated with the capacitor switching is sharp and interference noise may occur, the semiconductor device 3 connects the pins AVCC, AVSS and the terminals VH1, VL1 of the AD converter 11 through the switches SW31, SW32. Here, since the AD converter 11 is configured to perform AD conversion on the differential input signal IN1 based on the difference of the reference voltages VREFH, VREFL, the power supply voltages AVCC, AVSS have a high fluctuation elimination rate. Therefore, the propagation of the noise (i.e., interference noise) generated at VH1, VL1 of the AD converter 11 is suppressed.

[0158] Likewise, in the comparison operation for determining the value of the lower bit of the output signal OUT1, in which the current change associated with the capacitance switching is mild and interference noise is less likely to occur, and in the redundant comparison operation, the semiconductor device 3 connects the pins VREFH, VREFL and the terminals VH1, VL1 of the AD converter 11 through the switches SW31, SW32. Therefore, in the semiconductor device 3, the AD converter 11 can operate accurately while suppressing the propagation of interference noise.

[0159] Similarly, the semiconductor device 1 may be provided with switches SW31 , SW32 instead of the variable impedance circuits Z11 , Z12 , and with switches SW41 , SW42 instead of the variable impedance circuits Z21 , Z22 . Fig.12 : is a block diagram showing a configuration example of a semiconductor device 3a. The semiconductor device 3a is provided with switches SW31, SW32 instead of the variable impedance circuits Z11, Z12, and is provided with switches SW41, SW42 instead of the variable impedance circuits Z21, Z22.

[0160] The switch SW41 is provided between the pin VREFH and the pin AVCC and the terminal VH1 of the AD converter 12, and selects any one of the pin VREFH and the pin AVCC according to the control signal from the control circuit 14 and connects it to the terminal VH1 of the AD converter 12. The switch SW42 is provided between the pin VREFL and the pin AVSS and the terminal VL1 of the AD converter 12, and selects any one of the pin VREFL and the pin AVSS according to the control signal from the control circuit 14 and connects it to the terminal VL1 of the AD converter 12.

[0161] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it goes without saying that various modifications can be made without departing from the gist thereof.

[0162] Furthermore, the present disclosure may execute some or all of the processes of the semiconductor devices 1 to 3 by executing a computer program on a CPU (Central Processing Unit).

[0163] When loaded into a computer, the above-mentioned program includes a set of instructions (or software codes) for causing a computer to perform one or more functions described in the embodiment. The program can be stored in a non-transient computer-readable medium or a tangible storage medium. Non-limiting examples of computer-readable media or tangible storage media include RAM (random access memory), ROM (read-only memory), flash memory, SSD (solid-state drive) or other storage technologies, CD-ROM, DVD (digital versatile disk), Blu-ray (registered trademark) optical disk or other optical disk storage device, cassette, magnetic tape, magnetic disk storage device or other magnetic storage device. The program can be sent on a temporary computer-readable medium or communication medium. Non-limiting examples of temporary computer-readable media or communication media include electrical, optical, acoustic or other forms of propagation signals.

Claims

1. A semiconductor device, comprising: a first AD converter of a charge redistribution type, the first AD converter including a redundant comparison operation in a sequential comparison operation, and outputting a first output signal in a digital form by converting an analog differential first input signal using a reference voltage; and a first variable impedance circuit, provided on a signal line between a first pin to which the reference voltage is externally supplied and the first AD converter, and configured to be able to change impedance, A first control circuit controls the impedance of the first variable impedance circuit according to the operating condition of the first AD converter.

2. The semiconductor device according to claim 1, wherein the first control circuit controls the impedance of the first variable impedance circuit to be a first impedance when the first AD converter performs a comparison operation to determine a value of a high bit within a first predetermined range of a plurality of bits representing the first output signal, and Wherein, when the first AD converter performs a comparison operation to determine the value of a lower bit other than the higher bit within the first predetermined range of the multiple bits representing the first output signal, and performs a first redundant comparison operation, the first control circuit controls the impedance of the first variable impedance circuit to a second impedance lower than the first impedance.

3. The semiconductor device according to claim 2, The first AD converter is configured to perform the first redundant comparison operation at a resolution equal to or higher than the comparison operation for determining the value of the least significant bit of the upper bits within the first predetermined range.

4. The semiconductor device according to claim 1, The first AD converter comprises: a first DA converter, a first comparator, and a first sequential comparison register circuit, the first DA converter comprises a plurality of first capacitive elements and a plurality of first switches, and The first DA converter is configured to perform a sequential comparison of the potential of the first input signal with the output of the first DA converter using the first comparator and the first sequential comparison register circuit, and to redistribute the charges stored in the plurality of first capacitive elements by switching the connections of the plurality of first capacitive elements using the plurality of first switches based on the potential of the first input signal and the reference voltage.

5. The semiconductor device according to claim 1, The first variable impedance circuit is a first variable resistance circuit configured to be able to change resistance.

6. The semiconductor device according to claim 1, wherein the first AD converter is driven by a power supply voltage, and The first variable impedance circuit is a first selection circuit, which selects the first pin or the second pin to which the power supply voltage is provided from the outside according to the operating condition of the first AD converter, and provides the reference voltage to the first AD converter.

7. The semiconductor device according to claim 6, The first variable impedance circuit is configured to be able to select any one of a plurality of parasitic inductance formation paths.

8. The semiconductor device according to claim 1, further comprising: a second AD converter of a charge redistribution type, the second AD converter including a redundant comparison operation in a sequential comparison operation, and outputting a second output signal in a digital form by converting an analog differential second input signal using the reference voltage; a second variable impedance circuit, which is provided on a signal line between the first pin to which the reference voltage is supplied from the outside and the second AD converter and is configured to be able to change impedance; as well as A second control circuit controls the impedance of the second variable impedance circuit according to the operating condition of the second AD converter.

9. The semiconductor device according to claim 8, wherein the first control circuit controls the impedance of the first variable impedance circuit to be a first impedance when the first AD converter performs a comparison operation to determine the value of the upper bit within a first predetermined range representing the plurality of bits of the first output signal, wherein when the first AD converter performs a comparison operation for determining the value of the lower bits excluding the upper bits within the first predetermined range of the plurality of bits representing the first output signal and performs the comparison operation with a first redundancy, the first control circuit controls the impedance of the first variable impedance circuit to a second impedance lower than the first impedance, wherein the second control circuit controls the impedance of the second variable impedance circuit to a third impedance when the second AD converter performs a comparison operation to determine the value of the upper bit within a second predetermined range representing the plurality of bits of the second output signal, and Wherein, when the second AD converter performs a comparison operation to determine the value of the lower bits excluding the upper bits within the second predetermined range of the multiple bits representing the second output signal, and performs a comparison operation with second redundancy, the second control circuit controls the impedance of the second variable impedance circuit to a fourth impedance lower than the third impedance.

10. The semiconductor device according to claim 9, wherein the first AD converter is configured to perform the comparison operation with the first redundancy at a resolution equal to or higher than the comparison operation for determining the value of the least significant bit among the upper bits within the first predetermined range, And wherein the second AD converter is configured to perform the comparison operation with the second redundancy at a resolution equal to or higher than the comparison operation for determining the value of the least significant bit among the upper bits within the second predetermined range.

11. The semiconductor device according to claim 8, The first AD converter comprises: a first DA converter, a first comparator, and a first sequential comparison register circuit, and the first DA converter comprises a plurality of first capacitive elements and a plurality of first switches. wherein the first DA converter is configured to perform sequential comparison of the potential of the first input signal with the output of the first DA converter using the first comparator and the first sequential comparison register circuit, and at the same time redistribute the charges stored in the plurality of first capacitive elements based on the potential of the first input signal and the reference voltage by switching the connection of the plurality of first capacitive elements with the plurality of first switches, The second AD converter has: a second DA converter, a second comparator, and a second sequential comparison register circuit, the second DA converter has a plurality of second capacitive elements and a plurality of second switches, and The second DA converter is configured to perform sequential comparison of the potential of the second input signal with the output of the second DA converter using the second comparator and the second sequential comparison register circuit, and to redistribute the charges stored in the plurality of second capacitive elements based on the potential of the second input signal and the reference voltage by switching the connection of the plurality of second capacitive elements using the plurality of second switches.

12. The semiconductor device according to claim 8, wherein the first variable impedance circuit is a first variable resistance circuit configured to be able to change the resistance value, and The second variable impedance circuit is a second variable resistance circuit configured to be able to change the resistance value.

13. The semiconductor device according to claim 8, wherein the first AD converter is driven by a power supply voltage, wherein the first variable impedance circuit is a first selection circuit, the first selection circuit selects the first pin or the second pin to which the power supply voltage is provided from the outside according to the operating condition of the first AD converter, and provides it to the first AD converter as the reference voltage, wherein the second AD converter is driven by the power supply voltage, and The second variable impedance circuit is a second selection circuit, which selects the first pin or the second pin to which the power supply voltage is supplied from the outside according to the operating condition of the second AD converter, and provides it to the second AD converter as the reference voltage.

14. The semiconductor device according to claim 13, wherein the first variable impedance circuit is configured to be able to select any one of the formation paths of the plurality of parasitic inductances, and The second variable impedance circuit is configured to be capable of selecting any one of the formation paths of the plurality of parasitic inductances.

15. A control method for a semiconductor device, the method comprising: a first AD converter of a charge redistribution type sequential comparison type, the first AD converter including a redundant comparison operation in a sequential comparison operation, and outputting a first output signal in a digital form by converting an analog differential first input signal using a reference voltage; a first variable impedance circuit, the first variable impedance circuit being provided on a signal line between a first pin to which the reference voltage is externally supplied and the first AD converter, and being configured to change impedance; as well as a first control circuit, the first control circuit controlling the impedance of the first variable impedance circuit according to the operating condition of the first AD converter, wherein the impedance of the first variable impedance circuit is controlled to be a first impedance, wherein the first AD converter performs a comparison operation to determine a value of a high bit within a first predetermined range of the plurality of bits representing the first output signal, wherein the impedance of the first variable impedance circuit is controlled to be a second impedance lower than the first impedance, and The first AD converter performs a comparison operation to determine values ​​of lower bits excluding the upper bits within the first predetermined range of the plurality of bits representing the first output signal, and performs a redundant comparison operation.

16. A control program for executing a control process in a semiconductor device on a computer, the control program comprising: a first AD converter of a charge redistribution type sequential comparison type, the first AD converter including a redundant comparison operation in a sequential comparison operation, and outputting a first output signal in a digital form by converting an analog differential first input signal using a reference voltage; A first variable impedance circuit is provided on a signal line between a first pin to which a reference voltage is externally supplied and the first AD converter, and is configured to change impedance; as well as a first control circuit that controls the impedance of the first variable impedance circuit according to the operating condition of the first AD converter, The process of controlling the impedance of the first variable impedance circuit to be a first impedance, wherein a comparison operation is performed in the first AD converter to determine the value of the upper bit within a first predetermined range among the plurality of bits representing the first output signal, wherein the impedance of the first variable impedance circuit is controlled to be a second impedance lower than the first impedance, and A process in which a comparison operation is performed in the first AD converter to determine the value of a lower bit other than the upper bit within a first predetermined range among the plurality of bits representing the first output signal, and a redundant comparison operation is performed.

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