Convolutional coding method based on timing interruption

Abstract

The invention relates to a convolutional coding method based on timing interruption, which comprises the following steps of: setting the lengths of an annular array and an output cache array according to a convolutional coding scheme, initializing, and setting the interruption frequency of a timer matched with the rate of output data stream; in one round, outputting a convolutional coding result when a timer is interrupted and triggered each time; when one round is finished, parallel information input into the encoder is subjected to parallel-serial conversion through bit operation, information bits to be encoded are input into the annular array, and the shifting process of the shifting register is completed; and connecting a vector or generating a polynomial according to an encoder of the convolutional encoding scheme, and performing continuous exclusive-or operation on bit values at corresponding positions to generate output bits. By combining the timing interruption characteristic of the microcontroller in the embedded system and the structure and input and output characteristics of convolutional coding, the memory space is remarkably saved, the running speed is increased, and the method is suitable for various coding rates and easy to expand.

Description

Technical Field

[0001] The invention relates to a technology in the field of communications, in particular to a convolutional coding method based on timed interruption. Background Art

[0002] Convolutional coding is a commonly used channel coding technology to improve the reliability of data transmission and is widely used in various communication systems, such as satellite communications. The defects and shortcomings of existing convolutional coding are that most of the existing convolutional coding is implemented based on FPGA. Compared with microcontroller implementation, it is more expensive, consumes more power, and has poor flexibility. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention proposes a convolutional coding method based on timed interruption, which combines the characteristics of the timed interruption of the microcontroller in the embedded system and the structure and input and output characteristics of the convolutional coding, significantly saves memory space, improves the operating speed, adapts to a variety of coding rates, and is easy to expand.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention relates to a convolutional coding method based on timed interruption. The lengths of a ring array and an output buffer array are set and initialized according to a convolutional coding scheme, and the frequency of a timer interruption matching the rate of an output data stream is set; each time a timer interruption is triggered in a round, a convolutional coding result is output; when a round is finished, parallel information of an input encoder is converted into serial parallel information through bit operation, information bits to be encoded are input into the ring array, and a shifting process of a shift register is completed; according to an encoder connection vector or a generating polynomial of a convolutional coding scheme, continuous XOR operation is performed on bit values ​​at corresponding positions to generate output bits.

[0006] The method specifically includes:

[0007] Step 1. Initialize the ring array A, output buffer array B and timer interrupt: According to the convolutional coding scheme (n, k, K), set the length of the ring array to k*K, the length of the output buffer array to n, and initialize them to all 0; define the head p of the ring array as the encoder input position and initialize it to 0. Set the frequency of the timer interrupt to match the rate of the output data stream.

[0008] Step 2: The timer interrupt is triggered n times as a round, m represents the number of times the timer interrupt has been triggered in a round, and each time the timer interrupt is triggered, the convolution coding result B[m-1] is output. When m=n, execute steps 3 and 4 for the next round of encoding, otherwise skip.

[0009] Step 3, complete the parallel-to-serial conversion through bit operation, input k information bits to be encoded into the circular array, and perform the shift process of the shift register: replace the value A[p] at position p of array A with each input information bit, and shift the pointer, that is, move the head position backward by one position, that is, p=(p+k*K-1)mod(K*k), repeat k times to input k information bits to be encoded.

[0010] Step 4: According to the encoder connection vector or generating polynomial of the convolutional coding scheme, continuous XOR operations are performed on the bit values ​​at the corresponding positions to implement modulo 2 addition, and n output bits are generated and stored in the output buffer array B[0]~B[n-1].

[0011] The present invention relates to a system for implementing the above method, comprising: an initialization unit, a convolution control unit, a shift unit, an encoding unit and an output unit, wherein: the initialization unit initializes a ring array A, an output buffer array B and a timer interrupt processing according to the convolution coding scheme (n, k, K) information, obtains a ring array with a length of k*K, an output buffer array with a length of n, defines the head p of the ring array as the encoder input position and sets the frequency of the timing interrupt to match the rate of the input and output data streams; the convolution control unit counts the number of timer interrupt triggers and controls the convolution encoder to encode or output within an appropriate trigger round; the shift unit generates a timer interrupt according to the input information and the convolution control unit. The encoding unit is controlled by the convolution control unit, and when the timer interrupt satisfies m=n, the round is triggered to perform bit operations to complete the parallel-to-serial conversion, input k information bits to be encoded into the circular array, and complete the shift process of the shift register; the encoding unit is controlled by the encoder connection vector or the generator polynomial information of the convolution coding scheme and the convolution control unit, and when m=n, the round is triggered to perform continuous XOR operations on the bit values ​​of the corresponding positions to realize modulo 2 addition, and generate n output bits, which are stored in the output buffer array B[0]~B[n-1] to obtain the output bit result; the output unit outputs according to the output buffer array B[0]~B[n-1] and the control of the B unit each time the timer interrupt is triggered. Technical Effects

[0012] Compared with the prior art, the present invention occupies less cache space: only one group of the encoded output data stream is stored, saving memory space. Improved operating speed: a circular array is used to simulate a linear shift register, and the parallel-to-serial conversion is completed through bit operations, which reduces the number of instructions in the encoding process and improves the operating speed. Adapt to a variety of encoding rates: by adjusting the timing interrupt frequency and the length of the circular array, different encoding rates can be matched and adapted. Easy to expand: supports the addition of multiple block encodings (before parallel-to-serial conversion) and serial encodings (after parallel-to-serial conversion), such as RS encoding, CRC, pseudo-randomization and NRZ-M conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the flow chart of the method;

[0014] Figure 2 Schematic diagram of the convolutional encoder of embodiment (2,1,7). DETAILED DESCRIPTION

[0015] This embodiment relates to a convolutional coding method based on timed interruption. Figure 2 Taking the (2,1,7) convolutional encoder shown as an example, it includes:

[0016] Step 1: Initialize the ring array A[7], output buffer array B[2], timer interrupt, and define the head p of the ring array, which is initialized to 0. Set the output data stream rate to 2kbps, and the timer interrupt frequency to 2kHz.

[0017] Step 2: The timer interrupt is triggered twice as one round, and m represents the number of times the timer interrupt has been triggered in one round. Each time the timer interrupt is triggered, the convolutional coding result B[m-1] is output. When m=2, execute steps 3 and 4 to perform the next round of coding, otherwise skip steps 3 and 4.

[0018] Step 3: Based on the encoding result output in step 2, right shift and AND operation are performed on the input information bytes to realize parallel-to-serial conversion. Each time one information bit to be encoded is input, the value A[p] at position p of the circular array A is replaced, and the pointer is shifted, that is, the head position is moved back one position, that is, p=(p+6)mod 7.

[0019] Step 4: Figure 2 As shown, according to the encoder connection vector and the inverter of the convolutional coding scheme, continuous XOR operations are performed on the bit values ​​at the corresponding positions to realize modulo 2 addition, and 2 output bits are generated and stored in the output buffer array, namely: B[0] = A[p]^A[(p+1)mod 7]^A[(p+2)mod 7]^A[(p+3)mod 7]^A[(p+4)mod 7]; B[1] = A[p]^A[(p+1)mod 7]^A[(p+3)mod 7]^A[(p+4)mod 7]^A[(p+6)mod 7]^1.

[0020] After specific practical experiments, the input information byte is set to 0x1ACFFC1D, that is, the input information bit is: 00011010110011111111110000011101. The B[0] and B[1] output by the method of the present invention are: 01010110000010000001110010010111000110101001110011110100111110.

[0021] Compared with the existing technology, this method adopts a ring array design to reduce the number of instructions in the encoding process; by setting different timing interrupt frequencies and ring array lengths, different encoding rates can be matched and adapted, and different encoding generation polynomials can be adapted through slight changes in the software, which has strong flexibility; this method implements low-speed convolution encoding on a microcontroller, and has lower power consumption than the existing technology.

[0022] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A convolutional coding method based on timed interruption, characterized in that: According to the convolutional coding scheme, the length of the circular array and the output buffer array are set and initialized, and the frequency of the timer interrupt is set to match the rate of the output data stream; each time the timer interrupt is triggered in a round, the result of the convolutional coding is output; when a round is completed, the parallel information of the input encoder is converted from parallel to serial through bit operations, the information bits to be encoded are input into the circular array, and the shift process of the shift register is completed; according to the encoder connection vector or the generating polynomial of the convolutional coding scheme, the bit values ​​at the corresponding positions are continuously XORed and then the output bits are generated.

2. The convolutional coding method based on timed interruption according to claim 1, characterized in that: The initialization refers to: initializing the circular array A, the output buffer array B and the timer interrupt: according to the convolutional coding scheme (n, k, K), setting the length of the circular array to k*K, the length of the output buffer array to n, and initializing them to all 0s; defining the head p of the circular array as the encoder input position, initializing it to 0, and setting the frequency of the timer interrupt to match the rate of the output data stream.

3. The convolutional coding method based on timed interruption according to claim 1, characterized in that: The interrupt triggering means: the timer interrupt is triggered n times as one round, m represents the number of times the timer interrupt has been triggered in one round, each time the timer interrupt is triggered, the convolution coding result B[m-1] is output, when m=n, parallel-to-serial conversion and shifting process are performed and modulo 2 addition is performed before outputting the calculation result.

4. The convolutional coding method based on timed interruption according to claim 3 is characterized in that: The parallel-to-serial conversion and shifting process refers to: completing the parallel-to-serial conversion through bit operations, inputting k information bits to be encoded into the circular array, and performing the shifting process of the shift register: replacing the value A[p] at position p of the array A with each input information bit, and performing pointer shifting, that is, moving the head position backward by one position, that is, p=(p+k*K-1)mod(K*k), repeating k times to input k information bits to be encoded.

5. The convolutional coding method based on timed interruption according to claim 3 is characterized in that: The modulo 2 addition is implemented by performing continuous XOR operations on the bit values ​​at corresponding positions according to the encoder connection vector or generating polynomial of the convolutional coding scheme, and generates n output bits, which are stored in the output buffer array B[0]~B[n-1].

6. The convolutional coding method based on timed interruption according to any one of claims 1 to 5, characterized in that: include: Step 1: Initialize the ring array A[7], output buffer array B[2], timer interrupt, and define the head p of the ring array, initialize it to 0, set the output data stream rate to 2kbps, and the timer interrupt frequency to 2kHz; Step 2: The timer interrupt is triggered twice as one round, m represents the number of times the timer interrupt has been triggered in one round, and each time the timer interrupt is triggered, the convolution coding result B[m-1] is output. When m=2, execute steps 3 and 4 to perform the next round of encoding, otherwise skip steps 3 and 4; Step 3: Based on the encoding result output in step 2, right shift and AND operation are performed on the input information bytes to realize parallel-to-serial conversion. Each time one information bit to be encoded is input, the value A[p] at position p of the circular array A is replaced, and the pointer is shifted, that is, the head position is moved back one position, that is, p=(p+6)mod 7; Step 4: According to the encoder connection vector and the inverter of the convolutional coding scheme, continuous XOR operations are performed on the bit values ​​at the corresponding positions to realize modulo 2 addition, and 2 output bits are generated and stored in the output buffer array, that is: B[0] = A[p]^A[(p+1)mod 7]^A[(p+2)mod 7]^A[(p+3)mod 7]^A[(p+4)mod 7]; B[1] = A[p]^A[(p+1)mod7]^A[(p+3)mod 7]^A[(p+4)mod 7]^A[(p+6)mod 7]^1.

7. A convolutional coding system based on timed interruption for implementing the method of any one of claims 1 to 6, characterized in that: include: An initialization unit, a convolution control unit, a shift unit, an encoding unit and an output unit, wherein: the initialization unit initializes the ring array A, the output buffer array B and the timer interrupt processing according to the convolution coding scheme (n, k, K) information, obtains a ring array with a length of k*K, an output buffer array with a length of n, defines the head p of the ring array as the encoder input position and sets the frequency of the timing interrupt to match the rate of the input and output data streams; the convolution control unit counts the number of timer interrupt triggers, and controls the convolution encoder to encode or output within an appropriate trigger round; The shift unit triggers a round of bit operation to complete parallel-to-serial conversion when the timer interrupt satisfies m=n according to the input information and the control of the convolution control unit, inputs k information bits to be encoded into the circular array, and completes the shift process of the shift register; the encoding unit triggers a round of continuous XOR operation on the bit value at the corresponding position when m=n according to the encoder connection vector or generating polynomial information of the convolution encoding scheme and the control of the convolution control unit to realize modulo 2 addition, and generates n output bits, which are stored in the output buffer array B[0]~B[n-1] to obtain the output bit result; the output unit outputs each time the timer interrupt is triggered according to the output buffer array B[0]~B[n-1] and the control of the B unit.

Images