Access instruction processing method and communication equipment

Abstract

The embodiment of the invention provides a memory access instruction processing method and communication equipment, and the method comprises the steps: obtaining a memory access instruction, and analyzing the memory access instruction to obtain an analysis result; according to the instruction type information of the memory access instruction in the analysis result, allocating an instruction processing queue adapted to the memory access instruction for the memory access instruction; determining a physical address corresponding to each memory access instruction in the instruction processing queue; and determining an address access sequence of the physical addresses corresponding to the memory access instructions in the instruction processing queue, and executing an instruction processing strategy on the memory access instructions corresponding to the access sequence conforming to a preset memory model. According to the memory access instruction processing method provided by the invention, efficient processing of the memory access instructions can be realized; therefore, the overall performance of the communication equipment in the memory access intensive application is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method for processing a memory access instruction and a communication device. Background Art

[0002] Due to the complexity of memory access behavior and the uncertainty of storage system access latency, the execution of memory access instructions by the processor will become a bottleneck for application performance in many application scenarios. For example, application scenarios such as DPDK network communication, where memory access time occupies most of the running time, are called memory-intensive applications. In such applications, the memory access performance of the processor will greatly affect the performance of the communication device, and ultimately affect the user experience of the communication device.

[0003] Therefore, how to improve the processing efficiency of the processor for memory access instructions to enhance the overall performance of communication equipment in memory access intensive applications has become a hot topic being studied by those skilled in the art. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to provide a method for processing memory access instructions and a communication device, aiming to improve the processing efficiency of the processor for memory access instructions, so as to improve the overall performance of the communication device in memory-intensive applications.

[0005] In a first aspect, an embodiment of the present application provides a method for processing a memory access instruction, characterized in that the method includes:

[0006] Obtaining a memory access instruction, and parsing the memory access instruction to obtain a parsing result;

[0007] Determine an instruction processing queue adapted to the memory access instruction according to instruction type information of the memory access instruction in the parsing result;

[0008] Determining the physical address corresponding to each of the memory access instructions in the instruction processing queue;

[0009] Determine the address access order of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and execute the instruction processing strategy for the memory access instructions corresponding to the access order that conforms to the preset memory model.

[0010] In a second aspect, an embodiment of the present application further provides a communication device, comprising: a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for realizing a connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of the aforementioned method for processing memory access instructions are implemented.

[0011] The embodiment of the present application provides a method for processing memory access instructions and a communication device, wherein the method for processing memory access instructions obtains memory access instructions and parses the memory access instructions to obtain parsing results; allocates an instruction processing queue adapted to the memory access instructions to the memory access instructions according to the instruction type information of the memory access instructions in the parsing results; determines the physical addresses corresponding to each of the memory access instructions in the instruction processing queue; determines the address access order of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and executes an instruction processing strategy for the memory access instructions corresponding to the access order that conforms to the preset memory model. The instruction processing queue is used to classify and parallelize different types of memory access instructions, thereby achieving efficient processing of memory access instructions, thereby improving the overall performance of communication equipment in memory access-intensive applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 It is a flowchart of a method for processing a memory access instruction provided by an embodiment of the present application;

[0014] Figure 2 It is a partial architecture diagram of a processor that executes a method for processing a memory access instruction provided in an embodiment of the present application;

[0015] Figure 3 It is an instruction recording and submission logic diagram in the method for processing memory access instructions provided in an embodiment of the present application;

[0016] Figure 4 It is an instruction management logic diagram in the method for processing memory access instructions provided in an embodiment of the present application;

[0017] Figure 5 It is an emission logic diagram in the method for processing memory access instructions provided in an embodiment of the present application;

[0018] Figure 6 A schematic diagram of the framework structure of a communication device provided in an embodiment of the present application;

[0019] Figure 7 A schematic diagram of the framework structure of a device for processing memory access instructions provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0022] It should be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0023] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0024] See also Figure 1 , Figure 1 A flowchart of the steps of a method for processing memory access instructions provided in an embodiment of the present application.

[0025] like Figure 1 As shown, the method for processing memory access instructions is applied to a communication device and is executed by a processor disposed in the communication device. The method for processing memory access instructions includes steps S101 to S104.

[0026] Step S101: Acquire a memory access instruction, and parse the memory access instruction to obtain a parsing result.

[0027] The memory access instructions include load instructions and store instructions. The load instructions are used to obtain data from the memory, and the store instructions are used to write data to the memory. The memory includes but is not limited to double data rate synchronous dynamic random access memory, also known as DDR memory.

[0028] The processor obtains data processing instructions from the instruction storage system of the communication device, and selects memory access instructions from the data processing instructions, and then parses the memory access instructions to determine whether the corresponding memory access instructions are storage instructions or load instructions.

[0029] like Figure 2As shown, for example, the processor includes an analysis unit 101, a sending unit 102, an execution unit 103 and a non-blocking cache unit 105. The analysis unit 101 includes an instruction fetch front end and a decoding unit. During the data processing of the communication device, the instruction fetch front end of the analysis unit 101 of the processor obtains data processing instructions from the instruction storage system of the communication device, and selects memory access instructions from the data processing instructions, and transmits the memory access instructions to the decoding unit for analysis and processing, wherein the decoding unit can be at least one, and optionally, the decoding unit is two, and the two decoding units work independently and in parallel, so that the decoding analysis of the memory access instructions can be efficiently realized. Optionally, the analysis unit 101 is also provided with a transmission cache unit, and the memory access instructions that have completed the analysis can be temporarily stored in the transmission cache unit.

[0030] The processor may determine, based on the parsing result of the decoding analysis by the decoding unit, that the analyzed data processing instruction is a storage instruction or a load instruction.

[0031] Step S102: allocating an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result.

[0032] Exemplarily, the processor sets different instruction processing queues for different types of data processing instructions. After determining the instruction type information of the memory access instruction according to the analysis results, the processor adapts the corresponding instruction processing queue for the memory access instruction according to the instruction type information, thereby utilizing the instruction processing queue to achieve effective management of each memory access instruction.

[0033] like Figure 2 As shown, for example, the execution unit 103 of the processor is provided with an instruction processing queue, and the instruction processing queue includes a load queue and a storage queue, wherein the load queue is used to manage the load instructions in the memory access instructions, such as the load queue is used to record the instruction attribute information corresponding to the load instruction, and the processor can obtain the execution status of the corresponding load instruction according to the instruction attribute information, thereby realizing effective management of the load instruction. The storage queue is used to manage the load instructions in the memory access instructions, such as the storage queue is used to record the instruction attribute information corresponding to the storage instruction, and the processor can obtain the execution status of the corresponding storage instruction according to the instruction attribute information, thereby realizing effective management of the storage instruction.

[0034] After the analysis unit 101 obtains the instruction type information through analysis, it determines whether each currently analyzed memory access instruction is a storage instruction or a load instruction according to the type information, and transmits the corresponding memory access instruction to the execution unit 103 through the emission unit 102, so that the instruction attribute corresponding to the memory access instruction is recorded in the load queue or storage queue adapted to the memory access instruction in the execution unit 103. Different types of memory access instructions are recorded and analyzed through different instruction processing queues, thereby ensuring that instructions of different types are executed in order.

[0035] Optionally, when transmitting instructions to the execution unit 103 , the emission unit 102 is further configured to analyze the dependency relationship between the memory access instructions to ensure that the execution unit 103 executes the memory access instructions in order.

[0036] In some implementations, allocating an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes:

[0037] Recording the memory access instruction to the instruction processing queue adapted to the memory access instruction;

[0038] The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction, and the instruction processing queue is updated.

[0039] Exemplarily, the instruction processing queue includes a loading queue and a storage queue. When the current memory access instruction is determined to be a storage instruction based on the instruction type information of the parsed memory access instruction, the instruction name corresponding to the storage instruction is recorded in the storage queue. When the current memory access instruction is determined to be a loading instruction based on the instruction type information of the parsed memory access instruction, the instruction name corresponding to the loading instruction is recorded in the loading queue.

[0040] like Figure 3 As shown, for example, when the corresponding memory access instruction is determined to be a storage instruction according to the instruction type information, the storage instruction is recorded in the storage queue of the execution unit 103, and the position of the storage instruction in the storage queue is recorded through the head and tail pointers of the storage queue. Similarly, when the corresponding memory access instruction is determined to be a load instruction according to the instruction type information, the load instruction is recorded in the load queue of the execution unit 103, and the position of the load instruction in the load queue is recorded through the head and tail pointers of the load queue.

[0041] After the memory access instruction is added to the corresponding instruction processing queue, the instruction attribute information corresponding to the memory access instruction recorded in each instruction processing queue is obtained. Different instruction processing queues record different instruction attribute information. After the instruction attribute information corresponding to the memory access instruction recorded in the instruction processing queue is recorded in the corresponding instruction processing queue, the instruction processing queue is updated and the instruction processing queue that completes the instruction attribute information recording is used as the final instruction processing queue.

[0042] Optionally, the instruction attribute information includes but is not limited to the valid bit of the table entry (valid), the access address of the instruction (address), the valid bytes accessed (byte_vld), the virtual address bit (virtual), whether the load instruction is executed (exec), whether the load instruction violates the memory model (order), whether the load instruction is dependent on the storage instruction address (st_mask), the feedforward data valid bit (st_fw) and the index of the feedforward storage queue (st_idx), the data used for storage (data), the information indicating the submission of the storage instruction (commit), and the successful completion of the storage instruction (succ).

[0043] like Figure 4 As shown, the loadable queue is provided with a plurality of instruction attribute storage entries, each entry representing the instruction attribute of the load instruction stored in the load queue, wherein the instruction attributes recorded in the load queue include but are not limited to the entry valid bit (valid), the access address of the instruction (address), the valid byte accessed (byte_vld), the virtual address bit (virtual), whether the load instruction is executed (exec), whether the load instruction violates the memory model (order), whether the load instruction is dependent on the storage instruction address (st_mask), the feedforward data valid bit (st_fw) and the index of the feedforward storage queue (st_idx).

[0044] The storage queue is provided with a plurality of instruction attribute storage entries, each entry representing an instruction attribute of a storage instruction stored in the storage queue, wherein the instruction attributes recorded in the storage queue include but are not limited to an entry valid bit (valid), an access address of the instruction (address), a valid byte accessed (byte_vld), a virtual address bit (virtual), an entry valid bit (valid), an access address of the instruction (address), a valid byte accessed (byte_vld), and a virtual address bit (virtual).

[0045] In some implementations, recording each of the memory access instructions to the instruction processing queue adapted to each of the memory access instructions includes:

[0046] Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issuance channels within a unit cycle;

[0047] Detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition;

[0048] When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

[0049] Optionally, the detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition includes:

[0050] Determining a target instruction transmission channel from at least two of the instruction transmission channels according to the instruction transmission priorities of the instruction transmission channels;

[0051] Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with the historical memory access instruction, and detecting whether there is an idle execution pipeline;

[0052] When there is no data dependency between the memory access instruction in the target instruction issuance channel and the historical memory access instruction, and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel satisfies the instruction issuance condition.

[0053] Exemplarily, the instruction launch channel is also called the instruction launch slot. There are two instruction launch slots in the processor. Different instruction launch slots have different launch priorities. Therefore, before the storage instruction is launched, it is necessary to ensure that the memory access instruction in the launch slot with a higher launch priority is sent, and it is also necessary to detect whether there is a data dependency between the sent instruction and the historical memory access instruction. When there is a data dependency, it indicates that the current memory access instruction does not meet the instruction launch conditions, otherwise, it meets the conditions.

[0054] For example, the emission priority of emission slot 0 is greater than that of emission slot 1, that is, when there are memory access instructions to be emitted in both emission slot 0 and emission slot 1, the memory access instruction in emission slot 0 has the right to be emitted to the execution unit 103 first. When there is no instruction in emission slot 0, the memory access instruction in emission slot 1 can be emitted. Before the memory access instruction to be emitted in emission slot 0 or emission slot 1 is emitted, it is necessary to check whether the instruction in the corresponding emission slot has a data dependency relationship with the historical memory access instruction. According to the register busy table, it can be determined whether the current memory access instruction has a register dependency relationship with the previous memory access instruction. When the memory access instruction to be emitted in the corresponding emission slot has no data dependency relationship with the historical memory access instruction, the emission slot with a higher priority first sends the memory access instruction to the execution unit 103, and then the emission slot with a higher priority sends the cache instruction to the execution unit 103, so that the instruction attribute information corresponding to the cache instruction is recorded in the corresponding instruction processing queue in the execution unit 103.

[0055] In some implementations, the method further includes: when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, stopping parsing the acquired memory access instructions.

[0056] Exemplarily, each instruction processing queue has a limited instruction capacity. If the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, indicating that the current processor is in an overloaded state, the processor stops parsing the acquired memory access instructions.

[0057] Step S103: determining the physical address corresponding to each of the memory access instructions in the instruction processing queue.

[0058] Exemplarily, each memory access instruction corresponds to a physical address, and the physical address is used by the memory access instruction to access data. Therefore, during the execution of the memory access instruction, it is necessary to obtain the physical address corresponding to each memory access instruction in the instruction processing queue.

[0059] In some implementations, determining the physical address corresponding to each of the memory access instructions in the instruction processing queue includes:

[0060] Determining a virtual address of each of the memory access instructions according to instruction attribute information of each of the memory access instructions in the instruction processing queue;

[0061] The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

[0062] Exemplarily, the instruction attribute information corresponding to each memory access instruction includes the virtual address of the memory access instruction. After the memory access instruction is successfully recorded in the instruction processing queue, the virtual address of the memory access instruction is translated into a physical address and recorded in the queue item of the instruction processing queue.

[0063] Step S104: determining the address access order of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and executing an instruction processing strategy for the memory access instructions corresponding to the access order that complies with a preset memory model.

[0064] Exemplarily, after obtaining the physical address corresponding to each memory access instruction in the instruction processing queue, all the recorded memory access instructions in the instruction processing queue are subjected to the logic of physical address comparison, thereby checking whether the address access sequence of each memory access instruction violates the address access sequence of the memory model, and if the address access sequence of the memory access instruction does not violate the address access sequence of the memory model, the corresponding instruction processing strategy is executed according to the instruction type information of the memory access instruction. For example, when the memory access instruction is a load instruction, the processing strategy corresponding to the load instruction is executed, and when the memory access instruction is a store instruction, the processing strategy corresponding to the store instruction is executed.

[0065] In some implementations, executing the instruction processing strategy for the memory access instruction corresponding to the access sequence conforming to the preset memory model includes:

[0066] Determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction;

[0067] When it is determined according to the instruction type information that the memory access instruction is a load instruction, acquiring data adapted to the load instruction from a data cache unit according to the load instruction;

[0068] When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

[0069] Exemplarily, memory access instructions include load instructions and store instructions. Different types of memory access instructions have different functions. Therefore, it is necessary to perform corresponding operations according to different memory access instruction types in order for the communication device to operate normally. For example, when it is determined according to the instruction type information that the memory access instruction is a load instruction, the data cache unit is obtained according to the load instruction to adapt to the load instruction, thereby realizing reading the corresponding data from the data cache unit. When it is determined according to the instruction type information that the memory access instruction is a store instruction, it is necessary to wait for the instruction submission indication. When the instruction submission indication is obtained, the data storage operation is performed according to the instruction submission indication to store the data in the corresponding memory.

[0070] In some embodiments, the processor is provided with a non-blocking cache unit 105, and the method further includes: if a cache miss occurs in the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction, cache miss management is performed through the non-blocking cache unit, and the cache miss management is used to enable subsequent load instructions to access the data cache unit.

[0071] Exemplarily, when a load instruction sends a request to a data cache unit, if the corresponding data cannot be obtained, that is, a cache miss occurs in the sent request, the cache miss is managed by the non-blocking cache unit 105 to ensure that subsequent memory accesses can continue to access the data cache unit.

[0072] In some embodiments, the method further includes: obtaining the execution status of the memory access instructions in the instruction processing queue, and determining the memory access instructions that have been executed in the instruction processing queue based on the execution status; and performing instruction release operations on the memory access instructions in the instruction processing queue based on the time sequence in which the executed memory access instructions were recorded in the instruction processing queue.

[0073] Exemplarily, after the execution of the memory access instructions in the instruction processing queue is completed, the write back submission unit 104 obtains the execution status of each memory access instruction in the instruction processing queue, determines the time order in which the memory access instructions that have been executed are recorded in the instruction processing queue according to the execution status, and then performs an instruction release operation on the earliest memory access instruction that has been executed and recorded in the instruction processing queue to delete the corresponding memory access instruction record from the instruction processing queue, so as to reduce the instruction recording pressure of the instruction processing queue.

[0074] like Figure 3 As shown, taking the instruction processing queue as the loading queue as an example, according to the execution status of the loading instructions in the loading queue, there are 3 loading instructions that have been executed in the loading queue, the first one was recorded in the loading queue 1 day ago, the second one was recorded in the loading queue 23 hours ago, and the third one was recorded in the loading queue 20 days ago, then the loading instruction with the longest recording time will be released from the loading queue first.

[0075] See also Figure 6 The present application also provides a communication device 20, which includes a processor 201 and a memory 202. The processor 201 and the memory 202 are connected via a bus 203, and the bus 203 is, for example, an I2C (Inter-integrated Circuit) bus.

[0076] Specifically, the processor 201 may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0077] The memory 202 may be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a mobile hard disk.

[0078] The processor 201 is used to run the computer program stored in the memory 202, and implement the following steps when executing the computer program:

[0079] Obtaining a memory access instruction, and parsing the memory access instruction to obtain a parsing result;

[0080] Allocate an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result;

[0081] Determining the physical address corresponding to each of the memory access instructions in the instruction processing queue;

[0082] Determine the address access order of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and execute the instruction processing strategy for the memory access instructions corresponding to the access order that conforms to the preset memory model.

[0083] In some implementations, allocating an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes:

[0084] Recording the memory access instruction to the instruction processing queue adapted to the memory access instruction;

[0085] The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction.

[0086] In some implementations, recording each of the memory access instructions to the instruction processing queue adapted to each of the memory access instructions includes:

[0087] Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issuance channels within a unit cycle;

[0088] Detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition;

[0089] When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

[0090] In some implementations, the detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition includes:

[0091] Determining a target instruction transmission channel from at least two of the instruction transmission channels according to the instruction transmission priorities of the instruction transmission channels;

[0092] Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with the historical memory access instruction, and detecting whether there is an idle execution pipeline;

[0093] When there is no data dependency between the memory access instruction in the target instruction issuance channel and the historical memory access instruction, and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel satisfies the instruction issuance condition.

[0094] In some implementations, the processor 201 is further configured to execute: when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, stop parsing the acquired memory access instructions.

[0095] In some implementations, determining the physical address corresponding to each of the memory access instructions in the instruction processing queue includes:

[0096] Determining a virtual address of each of the memory access instructions according to instruction attribute information of each of the memory access instructions in the instruction processing queue;

[0097] The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

[0098] In some implementations, executing the instruction processing strategy for the memory access instruction corresponding to the access sequence conforming to the preset memory model includes:

[0099] Determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction;

[0100] When it is determined according to the instruction type information that the memory access instruction is a load instruction, acquiring data adapted to the load instruction from a data cache unit according to the load instruction;

[0101] When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

[0102] In some implementations, the processor 201 is provided with a non-blocking cache unit, and the processor 201 is further configured to execute:

[0103] If a cache miss occurs during the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction, cache miss management is performed by the non-blocking cache unit, and the cache miss management is used to enable subsequent load instructions to access the data cache unit.

[0104] In some implementations, the processor 201 is further configured to execute:

[0105] Acquire the execution status of the memory access instruction in the instruction processing queue, and determine the memory access instruction that has been executed in the instruction processing queue according to the execution status;

[0106] The memory access instructions in the instruction processing queue are subjected to instruction release operations according to the time sequence in which the executed memory access instructions are recorded in the instruction processing queue.

[0107] It should be noted that technicians in the relevant field can clearly understand that for the convenience and simplicity of description, the specific working process of the processor of the communication device described above can refer to the corresponding process in the aforementioned corresponding memory access instruction processing method embodiment, and will not be repeated here.

[0108] See also Figure 7 An embodiment of the present application also provides a processing device for memory access instructions, which is applied to a communication device or a processor.

[0109] like Figure 7As shown, the processing device 300 for memory access instructions includes an instruction parsing module 301, an instruction management module 302, an address conversion module 303 and an instruction processing module 304. Among them, the instruction parsing module 301 is used to obtain the memory access instruction, and parse the memory access instruction to obtain the parsing result. The instruction management module 302 is used to allocate an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result. The address conversion module 303 is used to determine the physical address corresponding to each of the memory access instructions in the instruction processing queue. The instruction processing module 304 is used to determine the address access order of the physical address corresponding to each of the memory access instructions in the instruction processing queue, and execute the instruction processing strategy for the memory access instruction corresponding to the access order that conforms to the preset memory model.

[0110] In some implementations, allocating an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes:

[0111] Recording the memory access instruction to the instruction processing queue adapted to the memory access instruction;

[0112] The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction.

[0113] In some implementations, recording each of the memory access instructions to the instruction processing queue adapted to each of the memory access instructions includes:

[0114] Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issuance channels within a unit cycle;

[0115] Detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition;

[0116] When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

[0117] In some implementations, the detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition includes:

[0118] Determining a target instruction transmission channel from at least two of the instruction transmission channels according to the instruction transmission priorities of the instruction transmission channels;

[0119] Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with the historical memory access instruction, and detecting whether there is an idle execution pipeline;

[0120] When there is no data dependency between the memory access instruction in the target instruction issuance channel and the historical memory access instruction, and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel satisfies the instruction issuance condition.

[0121] In some implementations, the instruction parsing module 301 is further configured to: when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, stop parsing the acquired memory access instructions.

[0122] In some implementations, determining the physical address corresponding to each of the memory access instructions in the instruction processing queue includes:

[0123] Determining a virtual address of each of the memory access instructions according to instruction attribute information of each of the memory access instructions in the instruction processing queue;

[0124] The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

[0125] In some implementations, executing an instruction processing strategy for the memory access instruction corresponding to the access sequence conforming to the preset memory model includes:

[0126] Determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction;

[0127] When it is determined according to the instruction type information that the memory access instruction is a load instruction, acquiring data adapted to the load instruction from a data cache unit according to the load instruction;

[0128] When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

[0129] In some embodiments, the processor is provided with a non-blocking cache unit, and the instruction processing module 304 is also used to perform cache miss management through the non-blocking cache unit if a cache miss occurs in the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction. The cache miss management is used to enable subsequent load instructions to access the data cache unit.

[0130] In some implementations, the instruction management module 302 is further configured to:

[0131] Acquire the execution status of the memory access instruction in the instruction processing queue, and determine the memory access instruction that has been executed in the instruction processing queue according to the execution status;

[0132] The memory access instructions in the instruction processing queue are subjected to instruction release operations according to the time sequence in which the executed memory access instructions are recorded in the instruction processing queue.

[0133] An embodiment of the present application also provides a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the video data processing method of any embodiment provided in the specification of the embodiment of the present application.

[0134] The storage medium may be an internal storage unit of the aforementioned communication device 20, such as a hard disk or memory of the communication device 20. The storage medium may also be an external storage device of the communication device 20, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc., equipped on the communication device 20.

[0135] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware embodiment, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0136] It should be understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations. It should be noted that, in this article, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "including a..." does not exclude the presence of other identical elements in the process, method, article or system including the element.

[0137] The serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for processing a memory access instruction, characterized in that: The method comprises: Obtaining a memory access instruction, and parsing the memory access instruction to obtain a parsing result; Allocate an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result; Determining the physical address corresponding to each of the memory access instructions in the instruction processing queue; Determine the address access order of the physical addresses corresponding to each of the memory access instructions in the instruction processing queue, and execute the instruction processing strategy for the memory access instructions corresponding to the access order that conforms to the preset memory model.

2. The method according to claim 1, characterized in that The allocating an instruction processing queue adapted to the memory access instruction to the memory access instruction according to the instruction type information of the memory access instruction in the parsing result includes: Recording the memory access instruction to the instruction processing queue adapted to the memory access instruction; The instruction attribute information corresponding to each of the memory access instructions is recorded in the instruction processing queue adapted to the memory access instruction.

3. The method according to claim 2, characterized in that The step of recording each of the memory access instructions into the instruction processing queue adapted to each of the memory access instructions comprises: Dispatching at least two of the memory access instructions in parallel to at least two corresponding instruction issuance channels within a unit cycle; Detecting whether the memory access instruction in each of the instruction issuance channels satisfies an instruction issuance condition; When the instruction issuance condition is met, the memory access instruction in the instruction issuance channel is sent to the instruction processing queue, and the position information of the memory access instruction in the instruction processing queue is recorded.

4. The method according to claim 3, characterized in that The detecting whether the memory access instruction in each of the instruction issuance channels satisfies the instruction issuance condition comprises: Determining a target instruction transmission channel from at least two of the instruction transmission channels according to the instruction transmission priorities of the instruction transmission channels; Detecting whether the memory access instruction in the target instruction issuance channel has a data dependency relationship with the historical memory access instruction, and detecting whether there is an idle execution pipeline; When there is no data dependency between the memory access instruction in the target instruction issuance channel and the historical memory access instruction, and there is an idle execution pipeline, it is determined that the memory access instruction in the instruction issuance channel satisfies the instruction issuance condition.

5. The method according to claim 2, characterized in that: The method further includes: when the number of memory access instructions recorded in the instruction processing queue exceeds a preset value, stopping parsing the acquired memory access instructions.

6. The method according to claim 1, characterized in that The determining of the physical address corresponding to each of the memory access instructions in the instruction processing queue includes: Determining a virtual address of each of the memory access instructions according to instruction attribute information of each of the memory access instructions in the instruction processing queue; The virtual address is converted to obtain the physical address corresponding to each memory access instruction.

7. The method according to claim 1, characterized in that The executing instruction processing strategy for the memory access instruction corresponding to the access sequence conforming to the preset memory model includes: Determining, according to the instruction type information, whether the memory access instruction is a load instruction or a store instruction; When it is determined according to the instruction type information that the memory access instruction is a load instruction, acquiring data adapted to the load instruction from a data cache unit according to the load instruction; When it is determined according to the instruction type information that the memory access instruction is a storage instruction, an instruction commit indication is obtained and a data storage operation is performed according to the instruction commit indication.

8. The method according to claim 7, characterized in that The processor is provided with a non-blocking cache unit, and the method further comprises: If a cache miss occurs during the process of obtaining data adapted to the load instruction from the data cache unit according to the load instruction, cache miss management is performed by the non-blocking cache unit, and the cache miss management is used to enable subsequent load instructions to access the data cache unit.

9. The method according to claim 1, characterized in that: The method further comprises: Acquire the execution status of the memory access instruction in the instruction processing queue, and determine the memory access instruction that has been executed in the instruction processing queue according to the execution status; The memory access instructions in the instruction processing queue are subjected to instruction release operations according to the time sequence in which the executed memory access instructions are recorded in the instruction processing queue.

10. A communication device, characterized in that: include: A processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of the method for processing memory access instructions as described in any one of claims 1 to 9 are realized.

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