Single-line multi-device tandem addressing system

Abstract

The invention discloses a single-line multi-device tandem addressing system. In the multi-device cascading addressing system, a plurality of devices are arranged in sequence and mutually connected in series, and the first device and the last device are connected with a controller. The first device addresses the first device according to the device identification address packet of the controller, and the adjusting device identification address packet outputs the adjusted device identification address packet to the next device. Each device other than the first device identifies the address packet received from the previous device for addressing. The first device and each device other than the last device adjust the device identification address packet received from the previous device and output the adjusted device identification address packet to the next device. The last device outputs the device identification address packet received from the previous device to the controller.

Description

Technical Field

[0001] The present invention relates to a multi-device serial connection system, and in particular to a single-line multi-device serial connection addressing system. Background Art

[0002] In a traditional multi-device serial connection system, multiple devices are arranged in sequence and connected in series. The controller needs to transmit frequency signals to multiple devices through multiple additional transmission lines to control the operation time of multiple devices, which increases additional line costs. In applications such as driving multiple devices with multiple light-emitting diodes (LEDs), the data transmitted between multiple devices includes command data and corresponding device data of each device. When transmitting command data between multiple devices, each device needs to transmit corresponding command data, so multiple devices need to transmit the same multiple command data in total, resulting in unnecessary bandwidth waste. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a single-line multi-device serial addressing system in view of the shortcomings of the prior art, comprising a controller and a plurality of devices. The plurality of devices are arranged in sequence. The first device in the plurality of devices is defined as a first device. The last device in the plurality of devices is defined as a last device. The input end of the first device is connected to the output end of the controller. The input ends of the other devices other than the first device are connected to the output end of the previous device. The output end of the last device is connected to the input end of the controller. The input end of the first device receives an addressing instruction packet from the output end of the controller. The first device sets a unique identification code of the first device according to a corresponding device identification address in the addressing instruction packet received from the controller. The first device adjusts the corresponding device identification address in the addressing instruction packet and outputs the adjusted addressing instruction packet to the next device. The input end of each of the other devices other than the first device receives the addressing instruction packet from the output end of the previous device, and each of the other devices other than the first device determines its own unique identification code according to the corresponding device identification address in the received addressing instruction packet. Each of the devices other than the first device and the last device adjusts the corresponding device identification address in the addressing instruction packet received from the last device, and outputs the adjusted addressing instruction packet to the next device. The last device directly outputs the addressing instruction packet received from the last device to the controller, or adjusts the addressing instruction packet and outputs the adjusted addressing instruction packet to the controller.

[0004] In an embodiment, the controller compares the addressing instruction packet output by the controller to the first device with the addressing instruction packet received by the controller from the last device to determine the corresponding device identification address of each of the multiple devices and the arrangement order and quantity of the multiple devices.

[0005] In an embodiment, the output terminal of each of the devices that is not outputting the addressed command packet to the next device or the controller is in a closed state.

[0006] In an embodiment, after each of the devices other than the last device adjusts the corresponding device identification address in the addressing instruction packet, the output end of each of the devices other than the last device is switched from a closed state to an open state to output the adjusted addressing instruction packet to the input end of the next device.

[0007] In an embodiment, after the last device adjusts the corresponding device identification address in the addressing instruction packet, the output end of the last device switches from a closed state to an open state to output the adjusted addressing instruction packet to the input end of the controller. The output ends of the plurality of devices are sequentially switched from a closed state to an open state according to the arrangement order of the plurality of devices.

[0008] In one embodiment, each of the devices sets its own unique identification code to be the same as the corresponding device identification address in the received addressing command packet.

[0009] In an embodiment, each of the devices counts up the corresponding device identification address in the received addressing command packet once to increase the corresponding device identification address once, and sets the counted corresponding device identification address as its own unique identification code.

[0010] In an embodiment, the addressing command packet received by each of the devices has N bit values, and M bit values ​​among the N bit values ​​in the addressing command packet represent the corresponding device identification address of the device, wherein N and M are appropriate integer values.

[0011] In an embodiment, the first device adjusts the M bit values ​​representing the unique identification code of the first device in the addressing command packet received from the controller, and outputs the adjusted addressing command packet to the next device.

[0012] In an embodiment, each of the devices other than the first device adjusts the M-bit value representing its own unique identification code of the addressing command packet received from the previous device. Each of the devices other than the first device and the last device outputs the addressing command packet with the adjusted M-bit value to the next device. The last device outputs the addressing command packet with the adjusted M-bit value to the controller.

[0013] In an embodiment, the first device counts up the M-bit value representing the unique identification code of the first device in the addressing instruction packet received from the controller to increase the size of the M-bit value of the unique identification code of the first device, and outputs the counted addressing instruction packet to the next device.

[0014] In an embodiment, each of the devices other than the first device counts up the M bit values ​​representing the unique identification code of the addressing instruction packet received from the previous device. Each of the devices other than the first device and the last device outputs the counted addressing instruction packet to the next device. The last device outputs the counted addressing instruction packet to the controller.

[0015] In an embodiment, the addressing instruction packet received by each of the devices has a pulse width modulation signal. The duty cycles of some of the waveforms of the pulse width modulation signal respectively represent the M bit values ​​of the corresponding device identification address. The duty cycle of each of the waveforms of the pulse width modulation signal is not greater than the first duty cycle, representing the bit value "0". The duty cycle of each of the waveforms of the pulse width modulation signal is not less than the second duty cycle, representing the bit value "1", where M is an appropriate integer value.

[0016] In an embodiment, the addressing instruction packet received by each of the devices has a pulse width modulation signal. The duty cycles of some of the waveforms of the pulse width modulation signal respectively represent the M bit values ​​of the corresponding device identification address. The duty cycle of each of the waveforms of the pulse width modulation signal falling into the first duty cycle range represents the bit value "0". The duty cycle of each of the waveforms of the pulse width modulation signal falling into the second duty cycle range represents the bit value "1", where M is an appropriate integer value.

[0017] In an embodiment, the addressing instruction packet received by each of the devices has a pulse width modulated signal. The duty cycles of some of the waveforms of the pulse width modulated signal respectively represent the M bit values ​​of the corresponding device identification address. The duty cycle of each of the waveforms of the pulse width modulated signal equal to the first duty cycle represents the bit value "0". The duty cycle of each of the waveforms of the pulse width modulated signal equal to the second duty cycle represents the bit value "1", where M is an appropriate integer value.

[0018] In an embodiment, before each of the devices receives the addressing command packet, the unique identification code of each of the devices is a default identification code.

[0019] After each of the devices receives the addressing command packet, each of the devices replaces the default identification code with the corresponding device identification address in the addressing command packet as its own unique identification code, thereby completing the reset of the unique identification code of each of the devices.

[0020] In an embodiment, each of the devices receives an identification code clearing instruction in addition to the corresponding device identification address in the addressing instruction packet. After each of the devices receives the addressing instruction packet, each of the devices clears the default identification code of each of the devices from the addressing instruction packet according to the identification code clearing instruction, and sets the corresponding device identification address in the addressing instruction packet as the unique identification code of each of the devices, thereby completing the reset of the unique identification code of each of the devices.

[0021] In an embodiment, the addressing command packet received by each of the devices has N bit values. Among the N bit values ​​in the addressing command packet, P bit values ​​represent the identification code clearing command of each of the devices, wherein N and P are appropriate integer values.

[0022] In an embodiment, the addressing instruction packet has a pulse width modulation signal. The duty cycles of some waveforms of the plurality of waveforms of the pulse width modulation signal respectively represent the P bit values ​​of the identification code clear instruction. The duty cycle of each of the waveforms of the pulse width modulation signal falling into the first duty cycle range represents the bit value "0". The duty cycle of each of the waveforms of the pulse width modulation signal falling into the second duty cycle range represents the bit value "1".

[0023] As described above, the present invention provides a single-line multi-device serial addressing system. The present invention provides a single-line multi-device serial addressing system. The single-line multi-device serial addressing system of the present invention does not set multiple frequency signal transmission lines between multiple devices and the controller, but only uses the original data transmission line. Under the condition of saving line costs, it can still effectively address each of the multiple devices connected in series. After effective addressing, the controller can issue instructions to the multiple devices by transmitting packets after addressing the multiple devices, and each device can actually operate according to the instructions issued to itself by the controller.

[0024] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 FIG. 4 is a block diagram of a single-line multi-device serial addressing system according to an embodiment of the present invention.

[0026] Figure 2 It is a schematic diagram of a single-line multi-device serial addressing system according to an embodiment of the present invention in which multiple devices have not yet been addressed.

[0027] Figure 3 It is a schematic diagram showing that only the first device among multiple devices of the single-line multi-device serial addressing system according to an embodiment of the present invention has been addressed.

[0028] Figure 4 It is a schematic diagram of an addressing command packet when only the first device among multiple devices of the single-line multi-device serial addressing system has been addressed according to an embodiment of the present invention.

[0029] Figure 5 It is a schematic diagram showing that a first device and a second device among a plurality of devices in a single-line multi-device serial addressing system according to an embodiment of the present invention have been addressed.

[0030] Figure 6 It is a schematic diagram of an addressing command packet when a first device and a second device among a plurality of devices of a single-line multi-device serial addressing system according to an embodiment of the present invention have been addressed.

[0031] Figure 7 It is a schematic diagram showing that multiple devices of the single-line multi-device serial addressing system according to an embodiment of the present invention have been addressed.

[0032] Figure 8 It is a schematic diagram of multiple bit values ​​in an addressing command packet transmitted between multiple devices in a single-line multi-device serial addressing system according to an embodiment of the present invention.

[0033] Fig. 9It is a schematic diagram of a working cycle of a pulse width modulation signal representing a corresponding device identification address in an addressing command packet transmitted between multiple devices in a single-line multi-device serial addressing system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following is an explanation of the embodiments of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0035] See also Figures 1 to 3 , Figure 5 and Figure 7 ,in Figure 2 This is a schematic diagram of a single-line multi-device serial addressing system according to an embodiment of the present invention, in which multiple devices have not yet been addressed. Figure 3 Schematic diagram of a single-line multi-device serial addressing system according to an embodiment of the present invention in which only the first device among multiple devices has been addressed. Figure 5 FIG. 1 is a schematic diagram showing that a first device and a second device among a plurality of devices in a single-line multi-device serial addressing system according to an embodiment of the present invention have been addressed. Figure 7 It is a schematic diagram showing that multiple devices of the single-line multi-device serial addressing system according to an embodiment of the present invention have been addressed.

[0036] The single-line multi-device serial addressing system of the embodiment of the present invention includes multiple devices (for example but not limited to Figure 1 Multiple devices 101 to 103) and a controller 900 are shown.

[0037] For example, each or any one or more of the multiple devices included in the single-line multi-device serial addressing system of the embodiment of the present invention may be a light-emitting device, and each light-emitting device may include one or more light-emitting components such as light-emitting diodes, but this is only an example and the present invention is not limited thereto. It should be understood that the number and type of devices and the number of (light-emitting) components in each device can be adjusted according to actual needs.

[0038] like Figure 1As shown, a plurality of devices 101 to 103 are arranged in sequence and connected in series. For the convenience of description, the first device in the plurality of devices 101 to 103 is defined as the first device 101 , and the last device in the plurality of devices 101 to 103 is defined as the last device 103 .

[0039] The input terminal DI of the first device 101 is connected to the output terminal of the controller 900. The input terminal DI of the device 102 is connected to the output terminal DO of the first device 101, and the input terminal DI of the last device 103 is connected to the output terminal DO of the device 102. The output terminal DO of the last device 103 is connected to the input terminal of the controller 900.

[0040] like Figure 1 and Figure 2 As shown, the plurality of devices 101 to 103 have not been addressed yet, and the unique ID or corresponding device address of each device 101 to 103 may be internally set to a default ID FF. The default ID FF of each of the plurality of devices 101 to 103 may be different from each other.

[0041] The output terminal DO of each device 101 to 103 that is not outputting an addressed command packet to the next device 101 to 103 or the controller 900 may be as follows: Figure 2 Shown in closed position.

[0042] If the controller 900 wants to address multiple devices 101 to 103 , the output terminal of the controller 900 can output an addressing command packet to the input terminal DI of the first device 101 .

[0043] When the input terminal DI of the first device 101 receives an addressing command packet from the output terminal of the controller 900 , the first device 101 sets the unique identification code ID of the first device 101 according to a corresponding device identification address in the addressing command packet received from the controller 900 .

[0044] In detail, the first device 101 can set the unique identification code ID of the first device 101 to be the same as a corresponding device identification address in the addressing command packet received from the controller 900. Alternatively, the first device 101 counts up a corresponding device identification address in the addressing command packet received from the controller 900 once to increase the corresponding device identification address once, and sets the counted corresponding device identification address as the unique identification code ID of the first device 101.

[0045] The first device 101 can adjust a corresponding device identification address in an addressing command packet received from the controller 900. After the first device 101 adjusts a corresponding device identification address in an addressing command packet, the output terminal DO of the first device 101 is as follows: Figures 2 to 3The state is switched from the off state to the on state to output an adjusted addressing instruction packet to the input terminal DI of the next device 102 .

[0046] For example, the first device 101 receives a corresponding device identification address in an addressing command packet from the controller 900, such as Figure 3 The "01" shown replaces Figure 2 The first device 101 is shown as having a default identification code FF set in it, which is used as the unique identification code ID of the first device 101, thereby completing the reset of the unique identification code ID of the first device 101. In addition, the first device 101 may count up a corresponding device identification address in an addressing instruction packet received from the controller 900 once to increase the value of the corresponding device identification address once, for example, by adding 1 to the corresponding device identification address value to form Figure 5 The “02” shown outputs an addressing command packet having a corresponding device identification address after counting to the next device 102 .

[0047] Alternatively, the first device 101 counts up a corresponding device identification address “00” in an addressing command packet received from the controller 900 once to increase the value of the corresponding device identification address once, for example, the corresponding device identification address value “00”+1 is formed into “01”, and the counted corresponding device identification address “01” is set as the unique identification code ID of the first device 101. Further, the first device 101 counts up the unique identification code ID of the first device 101 once to increase the value of the corresponding device identification address once, for example Figure 2 As shown, the unique identification code ID "01"+1 of the first device 101 is formed Figure 5 The “02” shown outputs an addressing instruction packet having a corresponding device identification address “02” after counting to the next device 102 .

[0048] When the input terminal DI of the second device 102 among the plurality of devices 101 to 103 receives an addressing command packet from the output terminal DO of the first device 101 , the device 102 sets the unique identification code ID of the device 102 according to a corresponding device identification address in the addressing command packet received from the first device 101 .

[0049] For example, the device 102 receives an address command packet from the first device 101 as follows: Figure 5 A corresponding device identification address “02” shown replaces a default identification code FF as the unique identification code ID of the device 102 , thereby completing the reset of the unique identification code ID of the device 102 .

[0050] The device 102 may adjust a corresponding device identification address in an addressing command packet received from the previous device 101. After the device 102 adjusts a corresponding device identification address in an addressing command packet received from the previous device 101, the output terminal DO of the device 102 is as follows: Figures 3 to 5 The state is switched from the off state to the on state to output an adjusted addressing instruction packet to the input terminal DI of the next device 103 .

[0051] For example, device 102 counts up the unique identification code ID of device 102 once to increase the value of the corresponding device identification address once, such as adding 1 to the unique identification code ID "02" of device 102 to form "03", and outputs an addressing instruction packet with a corresponding device identification address "03" after counting to the next device 103.

[0052] When the input terminal DI of the last device 103 among the multiple devices 101 to 103 receives an addressing command packet from the output terminal DO of the previous device 102, the last device 103 sets the unique identification code ID of the last device 103 according to a corresponding device identification address in an addressing command packet received from the previous device 102.

[0053] For example, the last device 103 receives an address command packet from the previous device 102 as follows: Figure 7 A corresponding device identification address “03” shown replaces a default identification code FF as the unique identification code ID of the last device 103 , thereby completing the reset of the unique identification code ID of the last device 103 .

[0054] After the last device 103 sets the unique identification code ID of the last device 103, the output terminal DO of the last device 103 can be as follows: Figures 5 to 7 As shown in FIG. 1 , the device 103 switches from the closed state to the open state to directly transmit an address instruction packet received from the device 102 to the controller 900. Alternatively, the last device 103 adjusts an address instruction packet received from the device 102, and the output terminal DO of the last device 103 can be as follows: Figures 5 to 7 The state is switched from the off state to the on state to output an adjusted addressing instruction packet to the input terminal DI of the controller 900 .

[0055] The output terminals DO of the plurality of devices 101 to 103 can be switched from the off state to the on state in sequence according to the arrangement sequence of the plurality of devices 101 to 103 as described above, and the plurality of devices 101 to 103 can complete addressing in sequence according to the arrangement sequence of the plurality of devices 101 to 103.

[0056] The controller 900 compares the value of a corresponding device identification address of an addressing instruction packet output by the controller 900 to the first device 101 with the value of a corresponding device identification address of an addressing instruction packet received by the controller 900 from the last device 103 to determine the corresponding device identification address of each of the multiple devices 101 to 103 and the arrangement order and quantity of the multiple devices 101 to 103.

[0057] See also Figures 1 to 7 ,in Figure 4 Schematic diagram of an addressing instruction packet when only the first device among multiple devices of a single-line multi-device serial addressing system according to an embodiment of the present invention has been addressed. Figure 6 It is a schematic diagram of an addressing command packet when a first device and a second device among a plurality of devices of a single-line multi-device serial addressing system according to an embodiment of the present invention have been addressed.

[0058] The input terminal DI of the first device 101 receives an address instruction packet from the controller 900. Figure 4 In addition to a corresponding device identification address having a unique identification code ID(1) representing the first device 101, there may also be an identification code clearing command CMD.

[0059] When the first device 101 receives an addressing command packet from the controller 900 with an identification code clearing command, the first device 101 clears a default identification code FF of the first device 101 from the addressing command packet according to the identification code clearing command. The first device 101 sets a corresponding device identification address (such as the value after the upward count) in the addressing command packet to the unique identification code ID(1) of the first device 101, thereby completing the reset of the unique identification code ID(1) of the first device 101.

[0060] The output terminal DO of the first device 101 is output to the input terminal DI of the next device 102 in an addressing instruction packet such as Figure 4 In addition to a corresponding device identification address representing the unique identification code ID(2) of the next device 102, there may also be an identification code clearing command CMD.

[0061] When the device 102 receives an addressing command packet from the first device 101 with an identification code clearing command, the device 102 clears a default identification code FF of the device 102 from the addressing command packet according to the identification code clearing command. The device 102 sets a corresponding device identification address (such as the value after the upward count) in the addressing command packet as the unique identification code ID (2) of the device 102, thereby completing the reset of the unique identification code ID (2) of the device 102.

[0062] The output terminal DO of the device 102 is output to the input terminal DI of the next device 103 in an addressing instruction packet such as Figure 6 In addition to a corresponding device identification address representing the unique identification code ID(3) of the next device 103, there may also be an identification code clearing command CMD.

[0063] When the device 103 receives an addressing command packet from the previous device 102 with an identification code clearing command, the device 103 clears a default identification code FF of the device 103 from the addressing command packet according to the identification code clearing command. The device 103 sets a corresponding device identification address (such as the value after the upward count) in the addressing command packet as the unique identification code ID (3) of the device 103, thereby completing the reset of the unique identification code ID (3) of the device 103.

[0064] See also Figures 1 to 8 ,in Figure 8 It is a schematic diagram of multiple bit values ​​in an addressing command packet transmitted between multiple devices in a single-line multi-device serial addressing system according to an embodiment of the present invention.

[0065] like Figure 7 The addressing instruction packet received by each of the plurality of devices 101 to 103 shown may have N bit values, such as but not limited to: Figure 8 The bit values ​​of bits b0 to b19 shown, where M of the N bit values ​​in the addressing instruction packet represent a corresponding device identification address of each of the plurality of devices 101 to 103, where N and M are appropriate integer values.

[0066] The first device 101 can set the unique identification code ID(1) of the first device 101 according to M bit values ​​among N bit values ​​in an addressing command packet received from the controller 900. In addition, the first device 101 adjusts M bit values ​​among N bit values ​​in an addressing command packet received from the controller 900, and outputs the addressing command packet having the adjusted M bit values ​​to the next device 102.

[0067] For example, the first device 101 sets the unique identifier ID(1) of the first device 101 (eg, bit value "01") to be the same as a corresponding device identification address (eg, Figure 8 In addition, the first device 101 counts up a corresponding device identification address (e.g., bit value "01") in an addressing command packet received from the controller 900 once to increase the value of the corresponding device identification address once, and outputs an addressing command packet having a counted corresponding device identification address (e.g., bit value "10") to the next device 102.

[0068] Alternatively, the first device 101 counts up a corresponding device identification address (e.g., bit value "00") in an addressing command packet received from the controller 900 once to increase the value of the corresponding device identification address once, and sets the counted corresponding device identification address (e.g., bit value "00") to Figure 8 The bit value "01" shown in FIG. 1 is set as the unique identification code ID(1) of the first device 101. Further, the first device 101 counts up the unique identification code ID(1) of the first device 101 once to increase the value of the corresponding device identification address once, for example Figure 2 As shown, the unique identification code ID (1) of the first device 101 is output to the next device 102 as an addressing command packet having a corresponding device identification address after counting (eg, bit value “10”).

[0069] The second device 102 in the plurality of devices 101 to 103 is arranged to set the unique identification code ID (2) of the device 102 according to M bit values ​​among the N bit values ​​in an addressing command packet received from the first device 101. In addition, the device 102 adjusts M bit values ​​among the N bit values ​​in an addressing command packet received from the first device 101, and outputs the addressing command packet having the adjusted M bit values ​​to the next device 103.

[0070] For example, the device 102 sets the unique identification code ID (2) of the device 102 to be the same as a corresponding device identification address (e.g., bit value "10") in an addressing command packet received from the first device 101. In addition, the device 102 counts up a corresponding device identification address in an addressing command packet received from the first device 101 once to increase the value of the corresponding device identification address once, and outputs an addressing command packet having a counted corresponding device identification address (e.g., bit value "11") to the next device 103.

[0071] The device 103 of the third device in the order of the plurality of devices 101 to 103 sets the unique identification code ID (3) of the device 103 according to M bit values ​​among the N bit values ​​in an addressing command packet received from the device 102 of the second device in the order of the plurality of devices 101 to 103. For example, the device 103 sets the unique identification code ID (3) of the device 103 to be the same as a corresponding device identification address (e.g., bit value "11") in an addressing command packet received from the previous device 102.

[0072] The device 103 adjusts M bit values ​​among the N bit values ​​in an addressing instruction packet received from the first device 101, and outputs the addressing instruction packet having the adjusted M bit values ​​to the controller 900. In practice, the device 103 may also directly output the addressing instruction packet received from the device 102 to the controller 900 without adjusting the M bit values ​​among the N bit values ​​in the addressing instruction packet received from the device 102.

[0073] The controller 900 may compare the multiple bit values ​​of a corresponding device identification address of an addressing command packet outputted by the controller 900 to the first device 101 with the multiple bit values ​​of a corresponding device identification address of an addressing command packet received by the controller 900 from the last device 103, so as to determine the corresponding device identification address of each of the multiple devices 101 to 103 and the arrangement order and number of the multiple devices 101 to 103. In this way, the multiple devices 101 to 103 are addressed.

[0074] After performing the above-mentioned addressing operation, the controller 900 can output a control instruction packet having a plurality of bit values ​​representing a unique identification code ID of each device 101 to 103, operation control data, and control instructions, etc., and sequentially transmit them to the plurality of devices 101 to 103. Each device 101 to 103 can identify a plurality of bit values ​​in a received control instruction packet to determine which device among the plurality of devices 101 to 103 the control instruction and operation control data in the control instruction packet are used to control the operation of. Each device 101 to 103 operates according to the control instruction and operation control data in the control instruction packet used to control its own operation.

[0075] See also Figures 1 to 9 ,in Fig. 9 It is a schematic diagram of a working cycle of a pulse width modulation signal representing a corresponding device identification address in an addressing command packet transmitted between multiple devices in a single-line multi-device serial addressing system according to an embodiment of the present invention.

[0076] An addressing command packet received by each of the plurality of devices 101 to 103 may have a pulse width modulation signal having a plurality of waveforms, wherein the duty cycle of at least some of the waveforms of the plurality of waveforms of the pulse width modulation signal respectively represents the M bit values ​​of the corresponding device identification address.

[0077] The duty cycles of the other ones of the plurality of waveforms of a pulse width modulation signal in the addressing command packet received by each of the plurality of devices 101 to 103 may respectively represent P bit values ​​of an identification code clearing command.

[0078] For example, Fig. 9As shown, the duty cycle of each waveform of the pulse width modulation signal is not greater than the first duty cycle (for example but not limited to 25%), representing the bit value "0", and the duty cycle of each waveform of the pulse width modulation signal is not less than the second duty cycle (for example but not limited to 75%), representing the bit value "1".

[0079] Alternatively, a duty cycle of each waveform of the pulse width modulated signal equal to a first duty cycle represents the bit value "0", and a duty cycle of each waveform of the pulse width modulated signal not less than a second duty cycle represents the bit value "1".

[0080] Alternatively, a duty cycle of each waveform of the pulse width modulation signal falling within a first duty cycle range represents the bit value "0", and a duty cycle of each waveform of the pulse width modulation signal not less than a second duty cycle range represents the bit value "1".

[0081] In summary, the present invention provides a single-line multi-device serial addressing system. The single-line multi-device serial addressing system of the present invention does not set multiple frequency signal transmission lines between multiple devices and the controller, but only uses the original data transmission line. Under the condition of saving line costs, it can still effectively address each of the multiple devices connected in series. After effective addressing, the controller can issue instructions to the multiple devices by transmitting packets after addressing the multiple devices, and each device can actually operate according to the instructions issued to itself by the controller.

[0082] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are included in the claims of the present invention.

Claims

1. A single-line multi-device serial addressing system, characterized in that: The single-line multi-device serial addressing system comprises: Controller; and A plurality of devices, wherein the plurality of devices are arranged in sequence, the first device in the plurality of devices is defined as a first device, and the last device in the plurality of devices is defined as a last device, an input end of the first device is connected to an output end of the controller, an input end of each of the devices other than the first device is connected to an output end of a previous device, and an output end of the last device is connected to an input end of the controller; wherein the input end of the first device receives an addressing instruction packet from the output end of the controller, the first device sets a unique identification code of the first device according to a corresponding device identification address in the addressing instruction packet received from the controller, the first device adjusts the corresponding device identification address in the addressing instruction packet, and outputs the adjusted addressing instruction packet to the next device; The input end of each of the devices other than the first device receives the addressing instruction packet from the output end of the previous device, and each of the devices other than the first device determines its own unique identification code according to the corresponding device identification address in the received addressing instruction packet; The first device and each of the devices other than the last device adjust the corresponding device identification address in the addressing instruction packet received from the previous device, and output the adjusted addressing instruction packet to the next device; The last device directly outputs the addressing instruction packet received from the last device to the controller, or adjusts the addressing instruction packet and outputs the adjusted addressing instruction packet to the controller.

2. The single-line multi-device serial addressing system according to claim 1, characterized in that: The controller compares the addressing instruction packet output by the controller to the first device with the addressing instruction packet received by the controller from the last device to determine the corresponding device identification address of each of the multiple devices and the arrangement order and quantity of the multiple devices.

3. The single-line multi-device serial addressing system according to claim 1, characterized in that: The output terminal of each of the devices that is not outputting the addressed command packet to the next device or the controller is in a closed state.

4. The single-line multi-device serial addressing system according to claim 3, characterized in that: After each of the devices other than the last device adjusts the corresponding device identification address in the addressing instruction packet, the output end of each of the devices other than the last device is switched from a closed state to an open state to output the adjusted addressing instruction packet to the input end of the next device.

5. The single-line multi-device serial addressing system according to claim 4, characterized in that: After the last device adjusts the corresponding device identification address in the addressing instruction packet, the output end of the last device switches from a closed state to an open state to output the adjusted addressing instruction packet to the input end of the controller; The output ends of the plurality of devices are switched from a closed state to an open state in sequence according to the arrangement order of the plurality of devices.

6. The single-line multi-device serial addressing system according to claim 1, characterized in that: Each of the devices sets its own unique identification code to be the same as the corresponding device identification address in the received addressing command packet.

7. The single-line multi-device serial addressing system according to claim 1, characterized in that: Each of the devices counts up the corresponding device identification address in the received addressing instruction packet once to increase the corresponding device identification address once, and sets the counted corresponding device identification address as its own unique identification code.

8. The single-line multi-device serial addressing system according to claim 1, characterized in that: The addressing instruction packet received by each of the devices has N bit values, and M bit values ​​among the N bit values ​​in the addressing instruction packet represent the corresponding device identification address of the device, wherein N and M are appropriate integer values.

9. The single-line multi-device serial addressing system according to claim 8, characterized in that: The first device adjusts the M bit values ​​representing the unique identification code of the first device in the addressing command packet received from the controller, and outputs the adjusted addressing command packet to the next device.

10. The single-line multi-device serial addressing system according to claim 9, characterized in that: Each of the devices other than the first device adjusts the M-bit value representing the unique identification code of the previous device itself in the addressing instruction packet received from the previous device, and each of the devices other than the first device and the last device outputs the addressing instruction packet with the adjusted M-bit value to the next device, and the last device outputs the addressing instruction packet with the adjusted M-bit value to the controller.

11. The single-line multi-device serial addressing system according to claim 8, characterized in that: The first device counts up the M-bit value representing the unique identification code of the first device in the addressing command packet received from the controller to increase the size of the M-bit value of the unique identification code of the first device, and outputs the counted addressing command packet to the next device.

12. The single-line multi-device serial addressing system according to claim 11, characterized in that: Each of the devices other than the first device counts up the M bits of the unique identification code of the previous device itself in the addressing instruction packet received from the previous device, and the first device and each of the devices other than the last device output the counted addressing instruction packets to the next device, and the last device outputs the counted addressing instruction packets to the controller.

13. The single-line multi-device serial addressing system according to claim 1, characterized in that: The addressing instruction packet received by each of the devices has a pulse width modulation signal, and the duty cycles of some of the multiple waveforms of the pulse width modulation signal respectively represent the M bit values ​​of the corresponding device identification address, and the duty cycle of each of the waveforms of the pulse width modulation signal is not greater than the first duty cycle, representing the bit value "0", and the duty cycle of each of the waveforms of the pulse width modulation signal is not less than the second duty cycle, representing the bit value "1", wherein M is an appropriate integer value.

14. The single-line multi-device serial addressing system according to claim 1, characterized in that: The addressing instruction packet received by each of the devices has a pulse width modulation signal, and the duty cycles of some waveforms among the multiple waveforms of the pulse width modulation signal respectively represent the M bit values ​​of the corresponding device identification address, and the duty cycle of each of the waveforms of the pulse width modulation signal falling into the first duty cycle range represents the bit value "0", and the duty cycle of each of the waveforms of the pulse width modulation signal falling into the second duty cycle range represents the bit value "1", wherein M is an appropriate integer value.

15. The single-line multi-device serial addressing system according to claim 1, characterized in that: The addressing instruction packet received by each of the devices has a pulse width modulation signal, and the duty cycles of some of the multiple waveforms of the pulse width modulation signal respectively represent the M bit values ​​of the corresponding device identification address, the duty cycle of each of the waveforms of the pulse width modulation signal equal to the first duty cycle represents the bit value "0", and the duty cycle of each of the waveforms of the pulse width modulation signal equal to the second duty cycle represents the bit value "1", wherein M is an appropriate integer value.

16. The single-line multi-device serial addressing system according to claim 1, characterized in that: Before each of the devices receives the addressing command packet, the unique identification code of each of the devices is a default identification code; After receiving the addressing command packet, each device replaces the default identification code with the corresponding device identification address in the addressing command packet as its own unique identification code, thereby completing the reset of the unique identification code of each device.

17. The single-line multiple-device serial addressing system according to claim 16, characterized in that: The addressing instruction packet received by each of the devices contains, in addition to the corresponding device identification address, an identification code clearing instruction; When each of the devices receives the addressing instruction packet, each of the devices clears the default identification code of each of the devices from the addressing instruction packet according to the identification code clearing instruction, and sets the corresponding device identification address in the addressing instruction packet to the unique identification code of each of the devices, thereby completing the resetting of the unique identification code of each of the devices.

18. The single-line multiple-device serial addressing system according to claim 17, characterized in that: The addressing instruction packet received by each of the devices has N bit values, and P bit values ​​among the N bit values ​​in the addressing instruction packet represent the identification code clearing instruction of each of the devices, wherein N and P are appropriate integer values.

19. The single-line multi-device serial addressing system according to claim 18, characterized in that: The addressing instruction packet has a pulse width modulation signal, and the duty cycles of some waveforms of the multiple waveforms of the pulse width modulation signal respectively represent the P bit values ​​of the identification code clearing instruction. The duty cycle of each waveform of the pulse width modulation signal falling into the first duty cycle range represents the bit value "0", and the duty cycle of each waveform of the pulse width modulation signal falling into the second duty cycle range represents the bit value "1".

20. The single-line multiple-device serial addressing system according to claim 1, characterized in that: Each of the devices comprises one or more light-emitting components.

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