3D memory, manufacturing method thereof and electronic equipment

Abstract

A 3D memory and a manufacturing method thereof, and an electronic device, the manufacturing method of the 3D memory comprising: forming a barrier layer on the inner wall of a trench by using an atomic deposition process, at least part of the barrier layer covering the exposed side walls of a plurality of branches; forming an insulating dielectric film on the barrier layer, adopting an oxidation process to enable the insulating dielectric film to form an oxidized insulating dielectric layer and enable the barrier layer to be oxidized to form an oxidized barrier layer, and enabling the oxidized insulating dielectric layer and the oxidized barrier layer to form an insulating dielectric layer; removing the insulating dielectric layer on one side, far away from the bit line, of the plurality of branches by adopting an etching process to form a first groove extending along the direction vertical to the substrate; depositing a supporting material film filling the first groove; respectively etching the support material film and the insulating dielectric layer by adopting different patterning etching processes, so that the support material film on one side, far away from the bit line, of each branch forms a support structure; the supporting structure is prevented from being etched, and the strength of the supporting structure is ensured.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a 3D memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0003] Taking DRAM as an example, the traditional known DRAM has multiple repeated "memory cells", each of which has a capacitor and a transistor. In the manufacturing process of DRAM, since the barrier layer that protects the transistor is made of the same material as the supporting structure, in the process of etching and removing the barrier layer, part of the supporting structure will be damaged, reducing the strength of the supporting structure and affecting the stability of the device support. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a method for manufacturing a 3D memory, including:

[0006] forming conductive layers and insulating layers alternately arranged in sequence on a substrate;

[0007] Performing patterned etching to form a plurality of grooves vertical to the substrate, so that each layer of the conductive layer forms a patterned structure stacked and distributed in sequence, each layer of the patterned structure comprises a bit line and a plurality of branches connected to the bit line, and the groove exposes the side walls of the plurality of branches;

[0008] Using an atomic deposition process, forming a barrier layer on the inner wall of the trench, wherein at least a portion of the barrier layer covers the exposed side walls of the plurality of branches;

[0009] forming an insulating dielectric film on the barrier layer, using an oxidation process to form an oxidized insulating dielectric layer from the insulating dielectric film, and oxidizing the barrier layer to form an oxidized barrier layer, wherein the oxidized insulating dielectric layer and the oxidized barrier layer form an insulating dielectric layer;

[0010] Using an etching process, the insulating dielectric layer on a side of the plurality of branches away from the bit line is removed to form a first groove extending in a direction perpendicular to the substrate;

[0011] Depositing a thin film of support material filling the first groove;

[0012] Using different patterned etching processes to etch the support material film and the insulating dielectric layer respectively, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure;

[0013] Performing patterned etching to expose one end of the plurality of branches away from the bit line, wherein the exposed one end of the plurality of branches forms a plurality of first capacitor electrodes, and the plurality of first capacitor electrodes are all connected to the support structure;

[0014] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the first capacitor electrode.

[0015] In an exemplary embodiment, the oxidized insulating dielectric layer and the oxidized blocking layer are made of the same material to form an insulating dielectric layer of an integrated structure.

[0016] In an exemplary embodiment, a first etching process is used to etch and remove a portion of the support material film between a plurality of adjacent branches in the same layer, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure;

[0017] Using a second etching process, a portion of the insulating dielectric layer between a plurality of adjacent branches in the same layer is etched away to form a second groove extending in a direction perpendicular to the substrate, wherein the second groove exposes a portion of the side wall of the insulating layer between the plurality of branches in different layers;

[0018] Patterned etching is used to etch the sidewall of the insulating layer exposed by the second groove in a direction parallel to the substrate to form a hole, wherein the hole and the second groove expose the multiple branches away from one end of the bit line, and the one end of the exposed multiple branches forms multiple first capacitor electrodes.

[0019] In an exemplary embodiment, the support structure and the insulating dielectric layer are made of different materials.

[0020] In an exemplary embodiment, the support structure is silicon nitride, and the insulating dielectric layer is silicon oxide.

[0021] In an exemplary embodiment, the barrier layer has a thickness of 3 nm to 15 nm.

[0022] In an exemplary embodiment, the barrier layer is polysilicon or amorphous silicon.

[0023] The embodiment of the present disclosure further provides a 3D memory, wherein the 3D memory is manufactured by the above-mentioned manufacturing method of the 3D memory.

[0024] In an exemplary embodiment, a plurality of memory cells, word lines, and bit lines are stacked in a direction perpendicular to a substrate. The word lines extend in a direction perpendicular to the substrate and penetrate the memory cells in different layers and are connected to the memory cells in different layers. The bit lines extend in a direction parallel to the substrate and are respectively connected to a plurality of memory cells in the same layer.

[0025] The storage unit includes: a transistor and a capacitor, the capacitor includes a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, and the first capacitor electrode is connected to the transistor.

[0026] An embodiment of the present disclosure further provides an electronic device, characterized in that it comprises the 3D memory as claimed in claim 8 or 9.

[0027] The manufacturing method of the 3D memory of the embodiment of the present disclosure blocks oxygen from oxidizing the multiple branches of the conductive layer through the barrier layer, thereby preventing the multiple branches of the conductive layer from being oxidized.

[0028] In the manufacturing method of the 3D memory of the embodiment disclosed in the present invention, the oxidation barrier layer formed after the oxygen in the barrier layer and the oxidation insulating dielectric layer use the same oxidation material, so that the oxidation barrier layer is used as a sacrificial layer. The same etching process can be used to etch and remove the oxidation insulating dielectric layer and the oxidation barrier layer, which simplifies the process flow and improves the controllability of the process, which is beneficial to the improvement of device performance and the improvement of structural stability.

[0029] The manufacturing method of the 3D memory of the embodiment of the present disclosure makes the materials of the oxidation barrier layer and the support structure different. In the process of etching the oxidation barrier layer, etching of the support structure can be avoided, thereby ensuring the strength of the support structure.

[0030] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0031] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0033] Figure 1 A schematic cross-sectional view of a 3D memory device provided by an exemplary embodiment along a direction parallel to a substrate;

[0034] Figure 2a for Figure 1 Schematic diagram in the a-a' direction after forming the insulating layer, the conductive layer and the barrier layer during the manufacturing process of the 3D memory;

[0035] Figure 2b for Figure 1 Schematic diagram in the b-b' direction after forming an insulating layer, a conductive layer and a barrier layer during the manufacturing process of a 3D memory;

[0036] Figure 2c for Figure 1 Schematic diagram of the d-d' direction after forming the insulating layer, the conductive layer and the barrier layer during the manufacturing process of the 3D memory;

[0037] Figure 3a for Figure 1 A schematic diagram in the a-a' direction after an oxide insulating dielectric layer is formed during the manufacturing process of a 3D memory;

[0038] Figure 3b for Figure 1 A schematic diagram in the b-b' direction after the oxide insulating dielectric layer is formed during the manufacturing process of the 3D memory;

[0039] Figure 3c for Figure 1 A schematic diagram of the d-d' direction after the oxide insulating dielectric layer is formed during the manufacturing process of the 3D memory;

[0040] Figure 4a for Figure 1 A schematic diagram of the a-a' direction after the first mask layer is formed during the manufacturing process of the 3D memory;

[0041] Figure 4b for Figure 1 A schematic diagram of the manufacturing process of the 3D memory in the direction of b-b' after the first mask layer is formed;

[0042] Figure 5a for Figure 1 A schematic diagram of the a-a' direction after the first groove is formed during the manufacturing process of the 3D memory;

[0043] Figure 5b for Figure 1 A schematic diagram of the bb' direction after the first groove is formed during the manufacturing process of the 3D memory;

[0044] Figure 6a for Figure 1 Schematic diagram in the a-a' direction after forming a supporting material film during the manufacturing process of the 3D memory;

[0045] Figure 6b for Figure 1Schematic diagram in the b-b' direction after forming a supporting material film during the manufacturing process of the 3D memory;

[0046] Figure 6c for Figure 1 Schematic diagram of the d-d' direction after forming a supporting material film during the manufacturing process of the 3D memory;

[0047] Figure 7a for Figure 1 A schematic diagram of the bb' direction after the second groove is formed during the manufacturing process of the 3D memory;

[0048] Figure 7b for Figure 1 A schematic diagram of the d-d' direction after the second groove is formed during the manufacturing process of the 3D memory;

[0049] Figure 8a for Figure 1 Schematic diagram of the a-a' direction after the holes are formed during the manufacturing process of the 3D memory;

[0050] Figure 8b for Figure 1 Schematic diagram of the 3D memory in the b-b' direction after the holes are formed during the manufacturing process;

[0051] Figure 8c for Figure 1 Schematic diagram of the d-d' direction after holes are formed during the manufacturing process of the 3D memory. DETAILED DESCRIPTION

[0052] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0053] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0054] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0055] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0056] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0057] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0058] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0059] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0060] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0061] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0062] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0063] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0064] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0065] The present disclosure provides a method for manufacturing a 3D memory, including:

[0066] forming conductive layers and insulating layers alternately arranged in sequence on a substrate;

[0067] Performing patterned etching to form a plurality of grooves vertical to the substrate, so that each layer of the conductive layer forms a patterned structure stacked and distributed in sequence, each layer of the patterned structure comprises a bit line and a plurality of branches connected to the bit line, and the groove exposes the side walls of the plurality of branches;

[0068] Using an atomic deposition process, forming a barrier layer on the inner wall of the trench, wherein at least a portion of the barrier layer covers the exposed side walls of the plurality of branches;

[0069] forming an insulating dielectric film on the barrier layer, using an oxidation process to form an oxidized insulating dielectric layer from the insulating dielectric film, and oxidizing the barrier layer to form an oxidized barrier layer, wherein the oxidized insulating dielectric layer and the oxidized barrier layer form an insulating dielectric layer;

[0070] Using an etching process, the insulating dielectric layer on a side of the plurality of branches away from the bit line is removed to form a first groove extending in a direction perpendicular to the substrate;

[0071] Depositing a thin film of support material filling the first groove;

[0072] Using different patterned etching processes to etch the support material film and the insulating dielectric layer respectively, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure;

[0073] Performing patterned etching to expose one end of the plurality of branches away from the bit line, wherein the exposed one end of the plurality of branches forms a plurality of first capacitor electrodes, and the plurality of first capacitor electrodes are all connected to the support structure;

[0074] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the first capacitor electrode.

[0075] The memory disclosed in the present invention is described below by way of some exemplary embodiments.

[0076] Figure 1 A schematic cross-sectional view of a 3D memory device provided in accordance with an exemplary embodiment along a direction parallel to the substrate. In an exemplary embodiment, Figure 1 As shown, the 3D memory provided in this embodiment may include: multiple layers of memory cells stacked in a direction perpendicular to the substrate, word lines, and bit lines 30. The word lines extend in a direction perpendicular to the substrate and penetrate the memory cells of different layers, and are connected to the gate electrodes of the transistors of the memory cells of different layers; the bit lines 30 extend in a direction parallel to the substrate, and are respectively connected to the source electrodes or drain electrodes of the transistors of multiple memory cells in the same layer.

[0077] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0078] In an exemplary embodiment, the memory cell may include: a transistor and a capacitor. In one embodiment, the memory cell only including the transistor and the capacitor forms a 1T1C structure; the transistor is connected to the bit line and the capacitor respectively. The capacitor in the present application may be understood as a capacitor.

[0079] In an exemplary embodiment, the transistor includes a first electrode 11, a second electrode 12, a gate electrode 14 extending in a direction perpendicular to the substrate, and a semiconductor layer 13 surrounding the gate electrode 14 and insulated from the gate electrode 14, wherein the semiconductor layer 13 extends on the side surface of the gate electrode 14 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate; wherein the channel between the first electrode 11 and the second electrode 12 is a horizontal channel; and the gate electrode 14 is connected to the word line 40.

[0080] A horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction. In practical applications, the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer. In other words, a horizontal channel does not mean that it must extend in one direction in the horizontal plane, and may extend in different directions. For example, when the semiconductor layer is annular, the source contact area and the drain contact area on the annular semiconductor layer are part of the ring. At this time, the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a certain direction locally. Of course, the carrier transmission direction in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate. The present application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.

[0081] In an exemplary embodiment, the gate electrode 14 extends only in a direction perpendicular to the substrate. The gate electrode 14 includes a side surface and end surfaces at the upper and lower ends, and the side surface is perpendicular to the substrate as a whole, or the side surface of the gate electrode 14 is the area corresponding to the semiconductor layer 13 that plays a gate electrode control role, and the film layer in this area is perpendicular to the substrate. In the actual process of manufacturing products, the side surface of the gate electrode 14 may have a curved area, which is also included in the above-mentioned situation of the present application.

[0082] In an exemplary embodiment, the material of the gate electrode 14 may include but is not limited to at least one of the following: indium tin oxide (ITO), metal tungsten, titanium nitride, titanium aluminum alloy, tantalum nitride, aluminum doped zinc oxide (AZO), indium zinc oxide (IZO).

[0083] In an exemplary embodiment, the semiconductor layer 13 surrounds the gate electrode 14 and is insulated from the gate electrode 14. The semiconductor layer 13 can be understood as a film layer. The semiconductor layer 13 extends along the side surface of the gate electrode 14. The thickness direction of the semiconductor layer 13 is parallel to the substrate. The length of the semiconductor layer 13 extending along the direction perpendicular to the substrate on the side surface of the gate electrode 14 is the height of the semiconductor layer 13.

[0084] In an exemplary embodiment, the semiconductor layer 13 extends on the side surface of the gate electrode 14 to form a ring extending in a direction perpendicular to the substrate, and the semiconductor layer 13 extends only in a direction perpendicular to the substrate, or the main part of the semiconductor layer 13 extends in a direction perpendicular to the substrate, and a horizontal part extending in a horizontal direction may exist at the end.

[0085] The term "surrounding" may be understood as partially or completely surrounding the gate electrode 14. In some embodiments, the surrounding may be completely surrounding as a whole, and the cross section of the semiconductor layer 13 after the surrounding is a closed ring. The interception direction of the cross section is intercepted along a direction parallel to the substrate. In some embodiments, the surrounding may be partially surrounding, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening.

[0086] In an exemplary embodiment, the semiconductor layer 13 may be a metal oxide, and the metal oxide may be indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, a metal oxide containing In and / or Sn, etc. When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the negative 15th power ampere, and 1E-10A refers to 10 to the negative 10th power ampere, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and the like, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0087] In an exemplary embodiment, the material composition of different regions of the word line extending in a direction perpendicular to the substrate is the same, which can be understood as being formed using the same film manufacturing process. The same material composition can be understood as the same main elements tested in the material, for example, they are all made of transparent conductive materials such as metal or ITO, but the atomic number ratio of different regions is not limited.

[0088] In an exemplary embodiment, stacked transistors in different layers may share a word line extending in a direction perpendicular to the substrate.

[0089] In an exemplary embodiment, the gate electrodes 14 of transistors in different layers are connected as one with the word lines 40. For example, the gate electrodes 14 of transistors in different layers and the word lines 40 are formed by using the same material and the same film manufacturing process, that is, the gate electrodes 14 of transistors in different layers are part of the word lines.

[0090] In an exemplary embodiment, the semiconductor layers 13 corresponding to transistors of different layers may be located on the sidewalls of the word line 40 and respectively located in different regions extending in a direction perpendicular to the substrate.

[0091] In an exemplary embodiment, the transistor may further include a gate insulating layer 15 surrounding the side surface of the gate electrode 14 , and the gate insulating layer 15 is disposed between the gate electrode 14 and the semiconductor layer 13 to separate the gate electrode 14 from the semiconductor layer 13 and insulate the gate electrode 14 from the semiconductor layer 13 .

[0092] In an exemplary embodiment, the gate insulating layer 15 may be made of a high-K dielectric material, that is, a dielectric material with a dielectric constant K≥3.9. The high-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0093] In an exemplary embodiment, the first electrode 11 and the second electrode 12 of the same transistor may be located in the same conductive film layer. It can be understood that the first electrode 11 and the second electrode 12 are located in the same metal film layer and are formed by patterning a conductive film layer, and the conductive film layer is approximately parallel to the upper surface of the substrate, but the embodiments of the present disclosure are not limited thereto, and the first electrode 11 and the second electrode 12 may be manufactured separately by different patterning processes.

[0094] In an exemplary embodiment, the first electrode 11 or the second electrode 12 of different transistors may be located in different conductive film layers.

[0095] In an exemplary embodiment, the first electrode 11 and the second electrode 12 are both extended along a direction parallel to the substrate and are arranged perpendicular to the word line 2. The first electrode 11 and the second electrode 12 are respectively located on opposite sides of the semiconductor layer 13 in a direction parallel to the substrate, and the first electrode 11 and the second electrode 12 are electrically connected through the semiconductor layer 13.

[0096] In an exemplary embodiment, the first electrode 11 and the second electrode 12 may be made of a metal material with low resistivity, such as titanium nitride (TiN), tungsten, molybdenum, and the like.

[0097] In an exemplary embodiment, the memory cells in the same layer form an array distributed along the first direction D1 and the second direction D2 respectively, and the bit line 30 is connected to the second electrode 12 of the transistors in the same layer and the same column. Figure 1, each layer includes four rows and two columns of memory cells, but the embodiments of the present disclosure are not limited thereto, and each layer may include memory cells of other numbers of rows and columns, for example, may include only one memory cell. The first direction D1 and the second direction D2 are both parallel to the substrate, and the first direction D1 and the second direction D2 intersect. In some embodiments, the first direction D1 and the second direction D2 may be perpendicular.

[0098] In an exemplary embodiment, the second electrodes 12 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30. The second electrodes 12 of the transistors in two adjacent columns of the same layer and the bit line 30 may be an integrated structure.

[0099] In an exemplary embodiment, the second electrode 12 of the transistor may be a portion of a bit line 30 to which the second electrode 12 is connected.

[0100] In an exemplary embodiment, the bit line 30 may extend along the second direction D2.

[0101] In an exemplary embodiment, the first electrode 11 and the second electrode 12 may both extend along the first direction D1 , perpendicular to the bit line 30 .

[0102] In an exemplary embodiment, the 3D memory may further include a data storage element.

[0103] In an exemplary embodiment, the data storage element is, for example, a capacitor, that is, a 1T1C storage structure is formed. However, the disclosed embodiment is not limited thereto, and other transistors may be combined to form a 2T0C storage structure, and so on.

[0104] In an exemplary embodiment, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode, and the first capacitor electrode 41 is connected to the first electrode 11 .

[0105] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 may be an integrated structure.

[0106] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 of the same transistor may be located in the same conductive film layer. It can be understood that the first capacitor electrode 41 and the first electrode 11 are located in the same metal film layer and are formed by patterning a conductive film layer, and the conductive film layer is approximately parallel to the upper surface of the substrate, but the embodiments of the present disclosure are not limited thereto, and the first capacitor electrode 41 and the first electrode 11 may be manufactured separately by different patterning processes.

[0107] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 of the same transistor are formed by using the same material and through the same film manufacturing process.

[0108] In an exemplary embodiment, the second capacitor electrodes of the capacitors in the same column of different layers may be connected into an integrated structure. The capacitors in the same column of different layers share the same capacitor electrode as the second capacitor electrode.

[0109] In an exemplary embodiment, the capacitor may further include a capacitor dielectric layer disposed between the first capacitor electrode 41 and the second capacitor electrode. The capacitor dielectric layer serves as a medium between the first capacitor electrode 41 and the second capacitor electrode.

[0110] In an exemplary embodiment, the 3D memory provided in this embodiment may also include: a support structure 20, the support structure 20 at least includes a sidewall extending in a direction perpendicular to the substrate, the sidewall of the support structure 20 is located on the side of the capacitor in the same column of different layers away from the bit line 30, and the first capacitor electrode 41 of the capacitor in the same column of different layers away from the bit line 30 is connected to the sidewall of the support structure 20 at one end, and the support structure 20 is configured to fix the first capacitor electrode 41 during the formation of the second capacitor electrode to prevent the first capacitor electrode 41 from deforming.

[0111] In an exemplary embodiment, the support structure 20 may be silicon nitride.

[0112] The technical solution of this embodiment is further explained below through the manufacturing process of the memory of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0113] In this embodiment, each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.

[0114] In an exemplary embodiment, the 3D memory may be any of the 3D memories described above, and the manufacturing process of the 3D memory may include:

[0115] Step 101, form an insulating layer, a conductive layer, and a barrier layer.

[0116] Forming the insulating layer, the conductive layer, and the barrier layer includes: forming the conductive layer 31 and the insulating layer 32 which are alternately arranged in sequence on the substrate 101, performing patterned etching on the conductive layer 31 and the insulating layer 32 through a mask plate to form trenches extending in a direction perpendicular to the substrate, each insulating layer 32 forms a first patterned structure that is stacked and distributed in sequence in a cyclic manner, each conductive layer 31 forms a second patterned structure that is stacked and distributed in sequence in a cyclic manner, and each second patterned structure includes bit lines and a plurality of branches extending in a direction perpendicular to the bit lines and connected to the bit lines; for example, the plurality of branches in the same layer and the bit lines form a "rich" character shape. The side walls of the trenches expose the side walls of the first patterned structure formed by each insulating layer 32 and the second patterned structure formed by the conductive layer 31.

[0117] Subsequently, using atomic layer deposition method, deposit the barrier layer 33 on the inner walls of the trenches and on the stacked structure formed by the first patterned structure and the second patterned structure. The barrier layer 33 covers at least the side walls of the first patterned structure and the second patterned structure, and at least a part of the barrier layer 33 covers the exposed side walls of the first patterned structure and the second patterned structure, as Figure 2a , Figure 2b and Figure 2c shown.

[0118] In an exemplary embodiment, the barrier layer 33 can be made of polysilicon or amorphous silicon. The barrier layer 33 is configured to block oxygen from oxidizing the conductive layer 31 during subsequent oxidation processes. For example, it blocks oxygen from oxidizing the plurality of branches of the conductive layer 31.

[0119] In an exemplary embodiment, the thickness of the barrier layer 33 can be 3nm - 15nm, which effectively blocks oxygen from entering the conductive layer 31 and can be completely oxidized during subsequent oxidation processes. When the thickness of the barrier layer 33 is greater than 15nm, in subsequent oxidation processes, the barrier layer 33 cannot be completely oxidized, resulting in the residue of the barrier layer 33 material (polysilicon or amorphous silicon) on the side walls of the conductive layer 31, increasing the risk of short - circuit of storage units in different layers; when the thickness of the barrier layer 33 is less than 3nm, it will cause the inability to effectively block oxygen from entering the conductive layer 31.

[0120] In an exemplary embodiment, the insulating layer and the conductive layer can be deposited using chemical vapor deposition method.

[0121] In an exemplary embodiment, the substrate can be a semiconductor substrate, such as a silicon substrate. Of course, it can be any substrate that plays a supporting role, not only the substrate, but also a substrate formed by peripheral circuits on the substrate, etc.

[0122] In an exemplary embodiment, the insulating layer serves to isolate devices and may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K≤3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) and the like.

[0123] Step 102: forming an oxidized insulating dielectric layer.

[0124] The formation of the oxidized insulating dielectric layer includes: on the basis of the substrate 101 formed with the aforementioned pattern, a spin-on dielectric (SOD) film is coated on the barrier layer 33, and the insulating dielectric film and the barrier layer 33 are both oxidized by a high temperature oxidation process to form an oxidized insulating dielectric layer 34 from the insulating dielectric film, and the barrier layer 33 is oxidized to form an oxidized barrier layer 33-1. The barrier layer 33 can block oxygen from entering the conductive layer 31 during the high temperature oxidation process to prevent the conductive layer 31 from being oxidized. Figure 3a , Figure 3b and Figure 3c shown.

[0125] In an exemplary embodiment, the oxidized insulating dielectric layer 34 is made of the same material as the oxidized blocking layer 33-1, and the oxidized insulating dielectric layer 34 and the oxidized blocking layer 33-1 form an integrally structured insulating dielectric layer 35. For example, the blocking layer 33 is made of polycrystalline silicon or amorphous silicon, and the oxidized blocking layer 33-1 is silicon oxide; the oxidized insulating dielectric layer 34 is silicon oxide; the oxidized insulating dielectric layer 34 is made of the same material as the oxidized blocking layer 33-1, and forms an integrally structured insulating dielectric layer 35, and the insulating dielectric layer 35 is silicon oxide.

[0126] Step 103: forming a first mask layer.

[0127] Forming the first mask layer includes: on the basis of the substrate 101 formed with the aforementioned pattern, forming a first mask layer 36 on the side of the insulating dielectric layer 35 away from the substrate 101, the first mask layer 36 overlaps with the bit line of the conductive layer 31 and the orthographic projection of the plurality of branches on the substrate 101, and does not overlap with the orthographic projection of the insulating dielectric layer 35 on the side of the plurality of branches away from the bit line on the substrate 101, and the first mask layer 36 exposes the insulating dielectric layer 35 on the side of the plurality of branches away from the bit line, such as Figure 4a and Figure 4b shown.

[0128] In an exemplary embodiment, the first mask layer 36 may include a hard mask layer 36-1, an anti-reflection layer 36-2 and an optical adhesive layer 36-3 stacked in sequence along a direction perpendicular to the substrate 101, wherein the hard mask layer 36-1 may be titanium or titanium nitride, and the anti-reflection layer 36-2 may be silicon oxynitride.

[0129] Step 104: forming a first groove.

[0130] The first groove is formed by etching away the insulating dielectric layer 35 on the side of the exposed multiple branches away from the bit line on the basis of the substrate 101 formed with the aforementioned pattern, so as to form a first groove 51 extending in a direction perpendicular to the substrate 101, the first groove 51 is located on the side of the multiple branches away from the bit line, and the first groove 51 is used to accommodate the support structure formed subsequently; then, the first mask layer 36 is removed by etching, such as Figure 5a and Figure 5b shown.

[0131] Step 105: forming a supporting material film.

[0132] The forming of the supporting material film comprises: on the basis of the substrate 101 formed with the aforementioned pattern, using an atomic deposition process, depositing a supporting material film 21 in the first groove 51 and on the stacked structure formed by the first patterned structure and the second patterned structure, the supporting material film 21 filling the first groove 51; then, using a grinding process, flattening the surface of the supporting material film 21, such as Figure 6a , Figure 6b and Figure 6c shown.

[0133] In an exemplary embodiment, the support material film 21 is made of different materials from the insulating dielectric layer 35. For example, the support material film 21 may be silicon nitride, and the insulating dielectric layer 35 (including the oxidized insulating dielectric layer 34 and the oxidation barrier layer 33-1) may be silicon oxide.

[0134] Step 106: forming a second groove.

[0135] The second groove is formed by: forming a second mask layer on the side of the support material film 21 away from the substrate 101 on the basis of the substrate 101 formed with the aforementioned pattern, and etching away a portion of the support material film between the multiple adjacent branches in the same layer by a first etching process; etching away a portion of the insulating dielectric layer 35 between the multiple adjacent branches in the same layer by a second etching process, so as to form a second groove 52 extending in a direction perpendicular to the substrate 101, wherein the second groove 52 exposes a portion of the sidewall of the insulating layer 32 between the multiple branches of different layers and a portion of the sidewall of the insulating dielectric layer 35, so that the support material film located on the side of the multiple branches away from the bit line forms a support structure 20, and the support structure 20 is connected to one end of the multiple branches away from the bit line, such as Figure 7a and Figure 7b shown.

[0136] In an exemplary embodiment, the oxidized insulating dielectric layer 34 and the oxidized blocking layer 33-1 in the insulating dielectric layer 35 are both made of silicon oxide. The oxidized blocking layer 33-1 can also serve as a sacrificial layer. During the etching of the insulating dielectric layer 35, the same etching process can be used to etch and remove the oxidized insulating dielectric layer 34 and the oxidized blocking layer 33-1, which simplifies the process flow and improves the controllability of the process, which is beneficial to improving device performance and improving structural stability.

[0137] In an exemplary embodiment, since the material of the insulating dielectric layer 35 is different from that of the supporting material film, etching of the supporting material film can be avoided during etching of the insulating dielectric layer 35, thereby ensuring the strength of the supporting structure 20 formed by the supporting material film.

[0138] Step 106: forming holes.

[0139] The hole formation includes: on the basis of the substrate 101 formed with the aforementioned pattern, using patterned etching, etching the side wall of the insulating layer 32 exposed by the second groove 52 and the side wall of the insulating dielectric layer 35 along a direction parallel to the substrate, so as to form a hole 53, wherein the hole 53 and the second groove 52 expose a plurality of branches away from one end of the bit line, and the exposed plurality of branches away from one end of the bit line form a plurality of first capacitor electrodes 41, and the ends of the plurality of first capacitor electrodes 41 away from the bit line are all connected to the support structure 20 and fixed by the support structure 20, such as Figure 8a , Figure 8b and Figure 8c As shown;

[0140] Subsequently, a capacitor dielectric layer and a second capacitor electrode are sequentially formed on one end of the exposed multiple branches away from the bit line. The second capacitor electrode is connected to the first capacitor electrode 41 through the capacitor dielectric layer. The first capacitor electrode 41, the capacitor dielectric layer and the second capacitor electrode form a capacitor of the 3D memory.

[0141] In the manufacturing process of the 3D memory of the embodiment of the present disclosure, the barrier layer 33 blocks oxygen from oxidizing the multiple branches of the conductive layer 31 , thereby preventing the multiple branches of the conductive layer 31 from being oxidized.

[0142] In the manufacturing process of the 3D memory of the embodiment of the present disclosure, the oxidation barrier layer 33-1 formed after the oxygen in the barrier layer 33 is removed and the oxidation insulating dielectric layer 34 uses the same oxidation material, so that the oxidation barrier layer 33-1 is used as a sacrificial layer. The same etching process can be used to etch and remove the oxidation insulating dielectric layer 34 and the oxidation barrier layer 33-1, which simplifies the process flow and improves the controllability of the process, which is beneficial to the improvement of device performance and the improvement of structural stability.

[0143] In the manufacturing process of the 3D memory of the embodiment of the present disclosure, by making the oxidation blocking layer 33 - 1 and the supporting structure of different materials, etching of the supporting structure can be avoided during etching of the oxidation blocking layer 33 - 1 , thereby ensuring the strength of the supporting structure.

[0144] The present disclosure also provides an electronic device, including the 3D memory described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0145] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A method for manufacturing a 3D memory, characterized in that: include: forming conductive layers and insulating layers alternately arranged in sequence on a substrate; Performing patterned etching to form a plurality of grooves vertical to the substrate, so that each layer of the conductive layer forms a patterned structure stacked and distributed in sequence, each layer of the patterned structure comprises a bit line and a plurality of branches connected to the bit line, and the groove exposes the side walls of the plurality of branches; Using an atomic deposition process, forming a barrier layer on the inner wall of the trench, wherein at least a portion of the barrier layer covers the exposed side walls of the plurality of branches; forming an insulating dielectric film on the barrier layer, using an oxidation process to form an oxidized insulating dielectric layer from the insulating dielectric film, and oxidizing the barrier layer to form an oxidized barrier layer, wherein the oxidized insulating dielectric layer and the oxidized barrier layer form an insulating dielectric layer; Using an etching process, the insulating dielectric layer on a side of the plurality of branches away from the bit line is removed to form a first groove extending in a direction perpendicular to the substrate; Depositing a thin film of support material filling the first groove; Using different patterned etching processes to etch the support material film and the insulating dielectric layer respectively, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure; Performing patterned etching to expose one end of the plurality of branches away from the bit line, wherein the exposed one end of the plurality of branches forms a plurality of first capacitor electrodes, and the plurality of first capacitor electrodes are all connected to the support structure; A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the first capacitor electrode.

2. The method for manufacturing a 3D memory according to claim 1, characterized in that: The oxidized insulating dielectric layer and the oxidized blocking layer are made of the same material to form an insulating dielectric layer with an integrated structure.

3. The method for manufacturing a 3D memory according to claim 1, characterized in that: Using a first etching process, a portion of the support material film between a plurality of adjacent branches in the same layer is etched away, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure; Using a second etching process, a portion of the insulating dielectric layer between a plurality of adjacent branches in the same layer is etched away to form a second groove extending in a direction perpendicular to the substrate, wherein the second groove exposes a portion of the side wall of the insulating layer between the plurality of branches in different layers; Patterned etching is used to etch the sidewall of the insulating layer exposed by the second groove in a direction parallel to the substrate to form a hole, wherein the hole and the second groove expose the multiple branches away from one end of the bit line, and the one end of the exposed multiple branches forms multiple first capacitor electrodes.

4. The method for manufacturing a 3D memory according to claim 1, characterized in that: The support structure and the insulating medium layer are made of different materials.

5. The method for manufacturing a 3D memory according to claim 4, characterized in that: The supporting structure is silicon nitride, and the insulating dielectric layer is silicon oxide.

6. The method for manufacturing a 3D memory according to claim 1, characterized in that: The thickness of the barrier layer is 3nm-15nm.

7. The method for manufacturing a 3D memory according to claim 1, characterized in that: The barrier layer is polysilicon or amorphous silicon.

8. A 3D memory, characterized in that: The 3D memory is manufactured by the manufacturing method of the 3D memory according to any one of claims 1 to 7.

9. The 3D memory according to claim 8, characterized in that: The invention comprises a plurality of memory cells stacked in a direction perpendicular to a substrate, a word line, and a bit line, wherein the word line extends in a direction perpendicular to the substrate and penetrates through the memory cells in different layers and is connected to the memory cells in different layers, and the bit line extends in a direction parallel to the substrate and is respectively connected to a plurality of memory cells in the same layer; The storage unit includes: a transistor and a capacitor, the capacitor includes a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, and the first capacitor electrode is connected to the transistor.

10. An electronic device, characterized in that: Comprising the 3D memory as claimed in claim 8 or 9.

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