Semiconductor device and method for manufacturing the same

Abstract

The invention relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a lower structure; a plurality of horizontal layers horizontally oriented above the substructure; a first conductive line commonly coupled to a first end of the horizontal layer and extending in a direction perpendicular to the lower structure; a plurality of second conductive lines crossing the horizontal layers, respectively; a plurality of data storage elements respectively coupled to second ends of the horizontal layers and stacked in a direction perpendicular to the lower structure; a capping layer disposed between the second conductive line and the first conductive line; and a barrier layer disposed between the capping layer and the first conductive line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0085304 filed in the Korean Intellectual Property Office on June 30, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensional memory cell and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, in order to cope with the capacity increase and miniaturization of memory devices, a technology for providing a three-dimensional (3D) memory device in which a plurality of memory cells are stacked is being suggested. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device including a highly integrated memory cell and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a lower structure; a plurality of horizontal layers horizontally oriented above the lower structure; a first conductive line commonly coupled to the first ends of the plurality of horizontal layers and extending in a direction perpendicular to the lower structure; a plurality of second conductive lines respectively crossing the plurality of horizontal layers; a plurality of data storage elements respectively coupled to the second ends of the plurality of horizontal layers and stacked in a direction perpendicular to the lower structure; a covering layer disposed between the second conductive lines and the first conductive lines; and a blocking layer disposed between the covering layer and the first conductive lines.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a horizontal layer above a lower structure; forming a horizontal conductive line crossing the horizontal layer; forming a covering layer on the side surface of the horizontal conductive line; forming a blocking layer above the covering layer; forming a vertically oriented vertical conductive line above the blocking layer to couple to a first end of the horizontal layer; and forming a data storage element coupled to a second end of the horizontal layer.

[0008] According to various embodiments of the present invention, bridging between horizontal conductive lines and vertical conductive lines may be prevented by forming a barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention.

[0010] Figure 1B It is shown Figure 1AA schematic cross-sectional view of a memory cell is shown.

[0011] Figure 1C It is shown Figure 1A A plan view of the switching element shown.

[0012] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

[0013] Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown.

[0014] Figure 3B It is shown Figure 2 A schematic cross-sectional view of a first memory cell array MCA1 is shown.

[0015] Figures 4 to 24 A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0016] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be more thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, similar reference numerals refer to similar parts in multiple figures and embodiments of the present invention.

[0017] The drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is formed directly on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0018] The embodiments described below relate to vertically stacked three-dimensional memory cells for increasing memory cell density and for reducing parasitic capacitance.

[0019] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention. Figure 1B It is shown Figure 1A A schematic cross-sectional view of a memory cell is shown. Figure 1C It is shown Figure 1A A plan view of the switching element shown.

[0020] refer to Figures 1A to 1C, the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second conductive line DWL. The data storage element CAP may include a storage element such as, for example, a container. The first conductive line BL may include, for example, a bit line. The second conductive line DWL may include, for example, a word line, and the horizontal layer HL may include, for example, an active layer. The data storage element CAP may include a first electrode SN, a dielectric layer DE, and a second electrode PN. The switching element TR may include, for example, a transistor, and the second conductive line DWL may be used as a gate electrode of the transistor. The switching element TR may also be referred to as a transistor, a cell transistor, an access element, or a selection element.

[0021] The first conductive line BL may extend vertically in the first direction D1. The horizontal layer HL may extend in the second direction D2 intersecting the first direction D1. The second conductive line DWL may extend in the third direction D3 intersecting the first direction D1 and the second direction D2. The second direction and the third direction may extend parallel to the lower structure LS (see Figure 3A ). The second direction D2 may be referred to as a first horizontal direction, and the third direction D3 may be referred to as a second horizontal direction.

[0022] The first conductive line BL may be vertically oriented in the first direction D1. The first conductive line BL may also be referred to as a vertically oriented bit line, a vertically extended bit line, a vertical conductive line, or a columnar bit line. The first conductive line BL may include a conductive material. The first conductive line BL may include a silicon-based material, a metal-based material, or a combination thereof. The first conductive line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductive line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The first conductive line BL may include a stack of titanium nitride and tungsten (TiN / W).

[0023] The switching element TR may include a transistor, and thus the second conductive line DWL may be referred to as a horizontal gate line or a horizontal word line.

[0024] The second conductive line DWL may extend in the third direction D3, and the horizontal layer HL may extend from the first conductive line BL to the data storage element CAP in the second direction D2. The second conductive line DWL may be referred to as a horizontal conductive line. The second conductive line DWL may have a double structure (may be referred to as a double horizontal conductive line) including a first horizontal conductive line G1 and a second horizontal conductive line G2, the first horizontal conductive line G1 and the second horizontal conductive line G2 facing each other and the horizontal layer HL interposed therebetween. The first horizontal conductive line G1 may be disposed above the horizontal layer HL. The second horizontal conductive line G2 may be disposed below the horizontal layer HL. The first horizontal conductive line G1 and the second horizontal conductive line G2 may form a pair of conductive lines coupled to one memory cell MC. A conductive pad (not shown) may be formed between the end of the first horizontal conductive line G1 and the end of the second horizontal conductive line G2 so as to apply the same voltage to the first horizontal conductive line G1 and the second horizontal conductive line G2. A pair of the first horizontal conductive line G1 and the second horizontal conductive line G2 may be separated from each other by the horizontal layer HL and the interlayer dielectric layer GD formed on the upper and lower surfaces of the horizontal layer HL.

[0025] According to another embodiment of the present invention, different voltages may be applied to the first horizontal conductive line G1 and the second horizontal conductive line G2. For example, a driving voltage may be applied to the first horizontal conductive line G1, and the second horizontal conductive line G2 may be grounded.

[0026] In each of the first horizontal conductive line G1 and the second horizontal conductive line G2, the width of the overlapping portion overlapping the horizontal layer HL (the width in the second direction) may be greater than the width of the non-overlapping portion not overlapping the horizontal layer HL. Due to this difference in width, the second conductive line DWL may have a notch-shaped sidewall. Return to reference Figure 1C , the second conductive line DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may refer to a portion overlapping with the channel CH of the horizontal layer HL, and the channel non-overlap portion NOL may refer to a portion not overlapping with the horizontal layer HL. The channel overlap portion WLP may have a cross shape or a diamond shape.

[0027] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polycrystalline silicon, single crystal silicon, germanium, or silicon-germanium. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0028] The horizontal layer HL may include a flat upper surface (also referred to as a top surface) and a lower surface (also referred to as a bottom surface). The upper surface and the lower surface of the horizontal layer HL may both extend in the second direction and be parallel to each other.

[0029] The horizontal layer HL may include a channel CH, a first doping region SR disposed between the channel CH and the first conductive line BL, and a second doping region DR disposed between the channel CH and the data storage element CAP. In some embodiments, the horizontal layer HL may be formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doping region SR and the second doping region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body layer, or simply a thin body. The channel overlap portion WLP of the second conductive line DWL and the channel CH may overlap each other. The channel CH may have a Figure 1A Or the cross shape shown in 1C. However, the shape of the channel CH may vary, and in some embodiments, for example, the channel may have a diamond shape. The size of the channel overlap portion WLP of the second conductive line DWL may be larger than the size of the channel CH. The channel overlap portion WLP of the second conductive line DWL may completely overlap with the channel CH.

[0030] The first doping region SR and the second doping region DR may be doped with impurities. These impurities may have the same conductivity type. For example, the first doping region SR and the second doping region DR may be doped with N-type impurities or P-type impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In) and a combination thereof. The first doping region SR may be coupled to the first conductive line BL. The second doping region DR may be coupled to the first electrode SN of the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as a first source / drain region and a second source / drain region.

[0031] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second conductive line DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0032] The second conductive line DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductive line DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second conductive line DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The second conductive line DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, while the P-type work function material may have a high work function greater than 4.5 eV. The second conductive line DWL may include a combination of a work function material and a metal-based material.

[0033] The horizontal layer HL of the switching element TR may extend from the top of the lower structure LS in the first horizontal direction D2, and may include a first doping region SR, a channel CH, and a second doping region DR sequentially disposed in the first horizontal direction D2. The second conductive line DWL may extend in a second horizontal direction D3 orthogonal to the first horizontal direction D2, and may cover the upper and lower surfaces of the channel CH.

[0034] The data storage element CAP may be horizontally disposed from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN horizontally extending from the horizontal layer HL in the second direction D2. The data storage element CAP may include a second electrode PN disposed on the first electrode SN, and a dielectric layer DE is disposed between the first electrode SN and the second electrode PN to electrically separate the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally arranged in the second direction D2.

[0035] From a top view, the first electrode SN may have a rectangular "C" or left bracket "[" shape, wherein the top bar and the bottom bar extend horizontally in the second direction D2 from the body of the bracket "[" or the rectangle "C". The top bar and the bottom bar together with the body define an internal space and a plurality of external surfaces. The internal space of the first electrode SN may include a vertical inner surface and two horizontal inner surfaces facing each other. The outer surface of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically in the first direction D1 and may be covered with the second contact node SNC (see Figure 1B ). The horizontal outer surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner surface of the first electrode SN. The second electrode PN may be disposed on the dielectric layer DE to fill the space inside the first electrode SN. At least a portion of the outer surface of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL via the second contact node SNC.

[0036] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a 3D structure, and the first electrode SN of the 3D structure may have a horizontal 3D structure oriented in the second direction D2. As an example of a 3D structure, the first electrode SN may have a barrel shape. The barrel shape of the first electrode SN may include a barrel inner surface and a barrel outer surface. Some of the barrel outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the barrel inner surface of the first electrode SN.

[0037] According to another embodiment of the present invention, the first electrode SN may have a pillar shape or a pylinder shape. The pylinder shape may refer to a structure in which a pillar shape and a pylinder shape are combined.

[0038] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, or tungsten nitride / tungsten (WN / W) stack. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the tube of the first electrode SN, titanium nitride (TiN) may be used as a second electrode PN of the capacitor CAP, and tungsten nitride may be a low resistance material.

[0039] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The dielectric constant of the high-k material may be higher than that of silicon oxide. The dielectric constant of silicon oxide (SiO2) may be approximately 3.9. The dielectric constant of the high-k material may be approximately 20 or higher. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or titanium strontium oxide (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed by a composite layer including two or more layers of the above-mentioned high-k materials.

[0040] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacking structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may be referred to as layers based on zirconium oxide (ZrO2). According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacking structure including hafnium oxide (HfO2). The dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked in sequence. The HA stack and the HAH stack may be referred to as layers based on hafnium oxide (HfO2). In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, the band gap energy of aluminum oxide (Al2O3) may be larger than the band gap energy of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) may be lower than the dielectric constant of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material, and the band gap energy of the high-bandgap material is greater than the band gap energy of the high-k material. The dielectric layer DE may include silicon oxide (SiO2) as a high bandgap material instead of aluminum oxide (Al2O3). Because the dielectric layer DE may include the high bandgap material, leakage current may be suppressed. The high bandgap material may be thinner than the high-k material.

[0041] According to another embodiment of the present invention, the dielectric layer DE may include a laminated structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above laminated structure, aluminum oxide (Al2O3) may be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0042] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0043] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5) or niobium oxide (Nb2O5). The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0044] The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The first electrode SN and the second electrode PN may include a metal-based material.

[0045] The data storage element CAP may be replaced by other data storage materials, such as phase change materials, magnetic tunnel junctions (MTJs), or variable resistance materials.

[0046] Reference again Figure 1A and Figure 1B , the memory cell MC may further include a first contact node BLC, a second contact node SNC, a first cover layer BC, and a second cover layer CC.

[0047] The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first cover layer BC may be disposed between the first contact node BLC and the second conductive line DWL. The second cover layer CC may be disposed between the second conductive line DWL and the first electrode SN. The first cover layer BC may have a stacked structure of a first pad L1 and a second pad L2. The first pad L1 may include silicon oxide, and the second pad L2 may include silicon nitride. The second cover layer CC may include silicon oxide, silicon nitride, or a combination thereof. The first cover layer BC and the second cover layer CC may be formed of the same material.

[0048] The memory cell MC may further include an extension portion BE disposed between the first contact node BLC and the horizontal layer HL. The extension portion BE may include a semiconductor material. The extension portion BE may include undoped polysilicon or doped polysilicon. The extension portion BE may include a conductive material. The extension portion BE and the first doping region SR may include impurities diffused from the first contact node BLC. According to another embodiment of the present invention, the extension portion BE may be referred to as a contact node extension portion.

[0049] The memory cell MC may further include a barrier layer BR disposed between the first contact node BLC and the first capping layer BC. The barrier layer BR may selectively grow from the surface of the first capping layer BC. The barrier layer BR may include a dielectric material. The barrier layer BR may include silicon carbide oxide (SiCO). The barrier layer BR may selectively grow from the surface of the second pad L2 of the first capping layer BC. As will be described later, the barrier layer BR may be grown by an area selective deposition (ASD) method. The barrier layer BR may include ASD-SiCO. ASD-SiCO may refer to silicon carbide oxide (SiCO) deposited by an ASD method.

[0050] As described above, when the barrier layer BR is formed, a bridge may be prevented from being formed between the second conductive line DWL and the first conductive line BL.

[0051] According to the comparative example, when the barrier layer BR is omitted, the second conductive line DWL and the first conductive line BL may be electrically bridged due to fume from the second conductive line DWL and a seam from the first cover layer BC.

[0052] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention. Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown in FIG. Figure 3B It is shown Figure 2 Schematic cross-sectional view of the first memory cell array MCA1 shown in FIG.

[0053] refer to Figure 2 , Figure 3A and Figure 3B , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. For a description of a single memory cell MC, reference may be made to Figures 1A to 1C .

[0054] The memory cell array MCA may include a three-dimensional array of memory cells MC. The 3D array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. In the column array of memory cells MC, a plurality of memory cells MC may be stacked in a first direction D1, and in the row array of memory cells MC, a plurality of memory cells MC may be horizontally arranged in a second direction D2 and a third direction D3. The memory cell array MCA may include a first memory cell array MCA1 and a second memory cell array MCA2 adjacent to each other in the second direction D2. The first memory cell array MCA1 may have a mirror-type structure in which two memory cells MC share a first conductive line BL. The second memory cell array MCA2 may have a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of first memory cell arrays MCA1 and a plurality of second memory cell arrays MCA2.

[0055] According to some embodiments of the present invention, an inter-cell dielectric layer IL may be disposed between memory cells MC stacked in the first direction D1. Cell isolation layers ISOA and ISOB may be disposed between adjacent memory cells MC in the third direction D3. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon carbide oxide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately and repeatedly disposed in the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP in the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL in the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2.

[0056] The memory cell array MCA may be disposed on the lower structure LS.

[0057] Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second conductive line DWL. The data storage element CAP may include a storage element such as, for example, a capacitor. The first conductive line BL may include a bit line. The second conductive line DWL may include a word line, and the horizontal layer HL may include an active layer. The data storage element CAP may include a first electrode SN, a dielectric layer DE, and a second electrode PN. The switching element TR may include a transistor, and in this case, the second conductive line DWL may be used as a gate electrode. The switching element TR may also be referred to as a cell transistor, an access element, or a selection element.

[0058] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1.

[0059] A plurality of first buffer layers BF1 may be disposed between the lower structure LS and the lowest second conductive line DWL among the second conductive lines DWL. An inter-cell dielectric layer IL may be disposed between the lowest second conductive line DWL and the first buffer layers BF1.

[0060] The second buffer layer BF2 may be disposed between the first conductive line BL and the lower structure LS. The third buffer layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third buffer layers BF1, BF2, and BF3 may include a dielectric material. For example, the first to third buffer layers BF1, BF2, and BF3 may include silicon oxide. The first conductive line BL, the second conductive line DWL, and the first to third buffer layers BF1, BF2, and BF3 may electrically disconnect the data storage element CAP from the lower structure LS. The first conductive line BL may extend into the lower structure LS. The dielectric layer DE and the second electrode PN of the data storage element CAP may extend into the lower structure LS.

[0061] The first conductive line BL may extend vertically from the top of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 crossing the first direction D1. The second conductive line DWL may extend in the third direction D3 crossing the first direction D1 and the second direction D2.

[0062] like Figure 1CAs shown, each second conductive line DWL may include a channel overlap portion WLP. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductive line DWL extending in the third direction D3 may include a plurality of channel overlap portions WLP, and the second conductive line DWL may have a notched sidewall due to the channel overlap portion WLP. The channel overlap portion WLP and the channel non-overlap portion may be alternately arranged in the third direction D3. The channel overlap portion WLP may have a cross shape or a diamond shape.

[0063] From a top view, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present invention, the side of the horizontal layer HL may have a curved shape or a round shape. The horizontal level spacer HLS may be disposed on the sidewall of the horizontal layer HL. The horizontal layer HL disposed in the third direction may be electrically disconnected by the horizontal level spacer HLS. The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP. The channel CH may have a cross shape or a diamond shape.

[0064] The first cover layer BC may be disposed between the second conductive line DWL and the first conductive line BL. The second cover layer CC may be disposed between the second conductive line DWL and the first electrode SN of the data storage element. The first cover layer BC may be disposed between the first horizontal conductive line G1 and the first conductive line BL, and the first cover layer BC may be disposed between the second horizontal conductive line G2 and the first conductive line BL. The second cover layer CC may be disposed between the first horizontal conductive line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC may be disposed between the second horizontal conductive line G2 and the first electrode SN of the data storage element CAP.

[0065] The first cover layer BC and the second cover layer CC may include a dielectric material. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, an air gap or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride.

[0066] refer to Figure 1B , the first capping layer BC may have a stack structure of a first liner L1 and a second liner L2. The first liner L1 may include silicon oxide, and the second liner L2 may include silicon nitride.

[0067] Each memory cell MC may further include an extension portion BE disposed between the first contact node BLC and the horizontal layer HL. The extension portion BE may include a semiconductor material. For example, the extension portion BE may include undoped polysilicon or doped polysilicon. The extension portion BE may include a conductive material. The extension portion BE and the first doping region SR may include impurities diffused from the first contact node BLC.

[0068] Each memory cell MC may further include a barrier layer BR disposed between the first contact node BLC and the first capping layer BC. The barrier layer BR may be selectively grown from the surface of the first capping layer BC. The barrier layer BR may include a dielectric material. The barrier layer BR may include silicon carbide oxide (SiCO). The barrier layer BR may be selectively grown from the surface of the second pad L2 of the first capping layer BC. As will be described later, the barrier layer BR may be grown by an area selective deposition (ASD) method. The barrier layer BR may include ASD-SiCO. ASD-SiCO may refer to silicon carbide oxide (SiCO) deposited by an ASD method.

[0069] The memory cell array MCA may have a mirror type structure sharing the first conductive lines BL.

[0070] The second electrode PN of the data storage element CAP may be coupled to the common plate PL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second conductive line DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be coupled to different first conductive lines BL. The switching elements TR stacked in the first direction D1 may share one first conductive line BL. The switching elements TR horizontally arranged in the third direction D3 may share one second conductive line DWL.

[0071] The lower structure LS may include a semiconductor substrate, a metal line structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit unit.

[0072] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal line structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the lower structure LS may be coupled by wafer bonding.

[0073] The peripheral circuit unit of the lower structure LS may be arranged at a level lower than the memory cell array MCA. This may be referred to as a Cell-Over-Peripheral (COP) structure. The peripheral circuit unit may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, a write circuit, and the like. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.

[0074] For example, the peripheral circuit unit may include a sub word line driver and a sense amplifier. The second conductive line DWL may be coupled to the sub word line driver. The first conductive line BL may be coupled to the sense amplifier.

[0075] According to another embodiment of the present invention, the peripheral circuit unit may be arranged at a higher level than the memory cell array MCA. This may be referred to as a peripheral-over-cell (POC) structure.

[0076] According to another embodiment of the present invention, the memory cell array MCA may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND memory, a ferroelectric RAM (FeRAM), a spin transfer torque RAM (STTRAM), a phase change RAM (PCRAM) or a resistive RAM (ReRAM).

[0077] according to Figure 2 , Figure 3A and Figure 3B, the semiconductor device 100 may include: a lower structure LS; a plurality of horizontal layers HL, which are horizontally oriented in a second direction D2 parallel to the surface of the lower structure LS; a first conductive line BL, which is commonly coupled to the first end of the horizontal layer HL and extends in a first direction D1 perpendicular to the surface of the lower structure LS; a plurality of second conductive lines DWL, which cross the horizontal layer HL; a plurality of data storage elements CAP, which are respectively coupled to the second end of the horizontal layer HL and are vertically stacked on the lower layer structure LS; a first capping layer BC, which is disposed between the second conductive line DWL and the first conductive line BL; and a barrier layer BR, which is disposed between the first capping layer BC and the first conductive line BL. The first capping layer BC may include a first pad L1 and a second pad L2 partially surrounded by the first pad L1, and the barrier layer BR may include a material selectively deposited from the surface of the second pad L2. For example, the first pad L1 may include silicon oxide, the second pad L2 may include silicon nitride, and the barrier layer BR may include silicon carbide oxide. When the barrier layer BR is formed, a bridge may be prevented from being formed between the second conductive line DWL and the first conductive line BL.

[0078] Figures 4 to 24 An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0079] refer to Figure 4 , a stacked body SB may be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate. In the stacked body SB, a plurality of sub-stacks may be alternately stacked. Each sub-stack may include a first layer 12A, a second layer 13, a third layer 12B, and a semiconductor layer 14 stacked in the order mentioned. The first layer 12A and the third layer 12B may be formed of the same material. The first layer 12A, the second layer 13, and the third layer 12B may include a sacrificial material that is removed in a subsequent process. Hereinafter, the first layer 12A and the third layer 12B may be simply referred to as the first sacrificial layer 12A and the second sacrificial layer 12B, and the second layer 13 may be simply referred to as the sacrificial semiconductor layer 13.

[0080] Each sub-stack may include a first sacrificial layer 12A, a sacrificial semiconductor layer 13, a second sacrificial layer 12B, and a semiconductor layer 14 stacked in the order mentioned. The first sacrificial layer 12A and the second sacrificial layer 12B may include silicon germanium, and the sacrificial semiconductor layer 13 may include single crystal silicon. The semiconductor layer 14 may include single crystal silicon. The first sacrificial layer 12A, the sacrificial semiconductor layer 13, the second sacrificial layer 12B, and the semiconductor layer 14 may be formed by an epitaxial growth process. The first sacrificial layer 12A and the second sacrificial layer 12B may be thinner than the sacrificial semiconductor layer 13, and the semiconductor layer 14 may be thicker than the sacrificial semiconductor layer 13.

[0081] The stacked body SB may include a plurality of semiconductor layers 14, a first sacrificial layer structure SB1, a second sacrificial layer structure SB2, and a third sacrificial layer structure SB3. In the stacked body SB, the first sacrificial layer structure SB1, the semiconductor layer 14, the second sacrificial layer structure SB2, the semiconductor layer 14, and the third sacrificial layer structure SB3 may be stacked in the order mentioned. The sacrificial semiconductor layer 13 may be disposed at the uppermost layer of the stacked body SB. Each of the first sacrificial layer structure SB1, the second sacrificial layer structure SB2, and the third sacrificial layer structure SB3 may include a three-layer stack of a first sacrificial layer 12A / sacrificial semiconductor layer 13 / a second sacrificial layer 12B. The sacrificial semiconductor layer 13 may be disposed at the uppermost layer of the third sacrificial layer structure SB3. For example, when the first sacrificial layer 12A and the second sacrificial layer 12B include a silicon germanium layer, and the sacrificial semiconductor layer 13 includes a single crystal silicon layer, each of the first sacrificial layer structure SB1, the second sacrificial layer structure SB2, and the third sacrificial layer structure SB3 may include a stack (SiGe / Si / SiGe) of a first silicon germanium layer / single crystal silicon layer / a second silicon germanium layer.

[0082] The sacrificial semiconductor layer 13 may include a first single crystal silicon layer, and the semiconductor layer 14 may include a second single crystal silicon layer. Therefore, in the stacked body SB, the first sacrificial layer structure SB1 may be disposed below the second single crystal silicon layer, and the second sacrificial layer structure SB2 may be disposed above the second single crystal silicon layer. Each of the first sacrificial layer structure SB1 and the second sacrificial layer structure SB2 may include a stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0083] According to the above-described embodiments of the present invention, when stacking memory cells, the first sacrificial layer structure SB1 , the semiconductor layer 14 , the second sacrificial layer structure SB2 , the semiconductor layer 14 , and the third sacrificial layer structure SB3 may be alternately stacked several times.

[0084] According to another embodiment of the present invention, in the stacked body SB, the first sacrificial layer 12A and the semiconductor layer 14 may be alternately stacked. For example, in the stacked body SB, a plurality of silicon germanium layers and a plurality of single crystal silicon layers may be alternately stacked. The silicon germanium layer and the single crystal silicon layer may be formed by an epitaxial growth process, and the silicon germanium layer and the single crystal silicon layer may have the same thickness. The stacked body SB may include a SiGe / Si / SiGe / Si stack.

[0085] Then, if Figures 2 to 3A and Figure 3B As shown, cell isolation layers ISOA and ISOB may be formed. Cell isolation layers ISOA and ISOB may be formed in the stacked body SB.

[0086] refer to Figure 5 , a hard mask layer 15 may be formed on the stacked body SB. The hard mask layer 15 may include silicon nitride.

[0087] Subsequently, a plurality of vertical openings 16 and 17 penetrating the stacked body SB may be formed. The stacked body SB may be etched to form the vertical openings 16 and 17. The vertical openings 16 and 17 may include a first vertical opening 16 and a second vertical opening 17. The vertical openings 16 and 17 may be hole-shaped openings. From a top view, the cross-section of the vertical openings 16 and 17 may be circular, rectangular, or polygonal.

[0088] refer to Figure 6 , a portion of the hard mask layer 15 may be trimmed (refer to reference numeral 15T).

[0089] Subsequently, the first sacrificial layer 12A and the second sacrificial layer 12B may be selectively removed through the vertical openings 16 and 17. In order to selectively remove the first sacrificial layer 12A and the second sacrificial layer 12B, the difference in etching selectivity between the sacrificial semiconductor layer 13 and the first sacrificial layer 12A and the second sacrificial layer 12B may be utilized. In addition, in order to selectively remove the first sacrificial layer 12A and the second sacrificial layer 12B, the difference in etching selectivity between the semiconductor layer 14 and the first sacrificial layer 12A and the second sacrificial layer 12B may be utilized. The first sacrificial layer 12A and the second sacrificial layer 12B may be removed by a wet etching process or a dry etching process. For example, when the first sacrificial layer 12A and the second sacrificial layer 12B include a silicon germanium layer, and the sacrificial semiconductor layer 13 and the semiconductor layer 14 include a silicon layer, an etchant or an etching gas having selectivity with respect to the silicon layer may be used to etch the silicon germanium layer.

[0090] Subsequently, the sacrificial semiconductor layer 13 and the semiconductor layer 14 may be recessed. In order to recess the sacrificial semiconductor layer 13 and the semiconductor layer 14, a wet etching process or a dry etching process may be used. According to this embodiment of the present invention, the sacrificial semiconductor layer 13 may be removed, and the semiconductor layer 14 may be partially etched. Since the sacrificial semiconductor layer 13 and the semiconductor layer 14 are formed of the same material, the semiconductor layer 14 may be thinned as shown in the reference numeral 14A, and the sacrificial semiconductor layer 13 is removed. The recessing process for forming the thin semiconductor layer 14A (i.e., the semiconductor layer pattern 14A) may be referred to as a thinning process or a trimming process for the semiconductor layer 14. The semiconductor layer pattern 14A may be referred to as a thin body active layer. The semiconductor layer pattern 14A may include a single crystal silicon layer. When the semiconductor layer pattern 14A is formed, the surface of the lower structure 11 may be recessed to a predetermined depth.

[0091] Through the above-described recess process, the semiconductor layer patterns 14A may be formed, and the horizontal recessed portion 18 may be defined between the semiconductor layer patterns 14A. Each of the upper and lower surfaces of the semiconductor layer patterns 14A may include a flat surface.

[0092] The semiconductor layer pattern 14A may have a cross shape from a top view perspective. A side of the semiconductor layer pattern 14A may have a curved shape or a round shape.

[0093] refer to Figure 7 A sacrificial dielectric layer 19 may be formed to surround or completely cover the semiconductor layer pattern 14A. The sacrificial dielectric layer 19 may include silicon nitride.

[0094] When forming the sacrificial dielectric layer 19, a dummy sacrificial dielectric layer 19D may be formed on the surface of the lower structure 11. The dummy sacrificial dielectric layer 19D and the sacrificial dielectric layer 19 may be formed of the same material. The dummy sacrificial dielectric layer 19D may include silicon nitride.

[0095] refer to Figure 8 , an inter-cell dielectric layer 20 may be formed on the sacrificial dielectric layer 19. The inter-cell dielectric layer 20 may fill between the sacrificial dielectric layers 19 adjacent to each other in the vertical direction. The inter-cell dielectric layer 20 may include silicon oxide. Portions of the inter-cell dielectric layer 20 may be conformally formed on the surfaces of the vertical openings 16 and 17.

[0096] Subsequently, a sacrificial column 21 may be formed on the inter-cell dielectric layer 20 disposed in the vertical openings 16 and 17. The sacrificial column 21 may include amorphous carbon. According to another embodiment of the present invention, a column cover layer may be further formed on the sacrificial column 21. The column cover layer may include a metal-based material. For example, the column cover layer may include titanium nitride.

[0097] The inter-cell dielectric layer 20 and the sacrificial pillar 21 may form a sacrificial pillar structure filling the vertical openings 16 and 17. The sacrificial pillar 21 may not be formed between the vertically stacked sacrificial dielectric layers 19. The sacrificial pillar structure may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. The sacrificial pillar structure may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0098] refer to Fig. 9 , a hard mask level opening 22 ′ may be formed by removing the hard mask layer 15 and the uppermost sacrificial dielectric layer 19 .

[0099] refer to Fig.10 , a top dielectric layer 22 filling the hard mask level opening 22' may be formed. The top dielectric layer 22 may be formed by a silicon oxide deposition process and a chemical mechanical polishing (CMP) process.

[0100] Subsequently, in order to expose the second vertical opening 17 among the first vertical opening 16 and the second vertical opening 17 , the inter-cell dielectric layer 20 and the sacrificial pillar 21 may be removed.

[0101] The sacrificial dielectric layer 19 and the dummy sacrificial dielectric layer 19D may be exposed through the second vertical opening 17 .

[0102] refer to Fig.11 The sacrificial dielectric layer 19 and the dummy sacrificial dielectric layer 19D may be selectively recessed horizontally. Thus, a sacrificial dielectric layer-level recess 19R may be formed. Portions of the semiconductor layer pattern 14A may be exposed through the sacrificial dielectric layer-level recess 19R.

[0103] refer to Fig.12 , a vertical level sacrificial structure 23 filling the second vertical opening 17 may be formed. The vertical level sacrificial structure 23 may include a dielectric material. The vertical level sacrificial structure 23 may include silicon oxide, silicon nitride, or a combination thereof. For example, the vertical level sacrificial structure 23 may have a stacked structure of a silicon oxide liner and a silicon nitride liner.

[0104] refer to Fig.13 In order to form the first hole-shaped opening 24 , the sacrificial pillar 21 filling the first vertical opening 16 may be removed.

[0105] Subsequently, in order to form the lower gap 19D′, the dummy sacrificial dielectric layer 19D below the first hole-type opening 24 may be removed.

[0106] refer to Fig.14 In order to enlarge the first hole-type opening 24, the inter-cell dielectric layer 20 may be cut (see 25).

[0107] Subsequently, a first buffer layer BF1 filling the lower gap 19D' may be formed. The first buffer layer BF1 may include silicon oxide. Forming the first buffer layer BF1 may include depositing silicon oxide filling the lower gap 19D' and etching the silicon oxide. Subsequently, the surface of the lower structure 11 may be oxidized to form a second buffer layer BF2. The second buffer layer BF2 may include silicon oxide.

[0108] refer to Fig.15 To form the horizontal level recess 26 , the sacrificial dielectric layer 19 may be removed. Portions of the semiconductor layer 14A may be exposed through the horizontal level recess 26 .

[0109] refer to Fig.16 , an interlayer dielectric layer 27 may be formed on the exposed portion of the semiconductor layer pattern 14A. The interlayer dielectric layer 27 may be formed by oxidizing the surface of the semiconductor layer pattern 14A. According to another embodiment of the present invention, the interlayer dielectric layer 27 may be formed by a process of depositing silicon oxide.

[0110] The interlayer dielectric layer 27 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. The interlayer dielectric layer 27 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON or a combination thereof.

[0111] Subsequently, a horizontal conductive line 28 filling the horizontal level recess 26 may be formed on the interlayer dielectric layer 27. Forming the horizontal conductive line 28 may include depositing a conductive material filling the horizontal level recess 26 on the interlayer dielectric layer 27, and performing an etch-back process on the conductive material. The horizontal conductive line 28 may include a pair of first horizontal conductive lines 28A and second horizontal conductive lines 28B facing each other, with a semiconductor layer pattern 14A therebetween. The first horizontal conductive line 28A and the second horizontal conductive line 28B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductive line 28A and the second horizontal conductive line 28B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductive line 28A and the second horizontal conductive line 28B may include a TiN / W stack, in which titanium nitride and tungsten are stacked in sequence. The first horizontal conductive line 28A and the second horizontal conductive line 28B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more.

[0112] refer to Fig.17 , a first capping layer 29 may be formed on a first side of the horizontal conductive line 28. The first capping layer 29 may include silicon oxide, silicon nitride, or a combination thereof. A capping material may be deposited and etched back to form the first capping layer 29. When or after forming the first capping layer 29, a portion of the interlayer dielectric layer 27 may be removed to expose a first edge portion of each semiconductor layer pattern 14A.

[0113] The first capping layer 29 may include a stack of a first liner 30 and a second liner 31. The first liner 30 may include silicon oxide, and the second liner 31 may include silicon nitride. The first liner 30 may be conformally formed, and the second liner 31 may be thicker than the first liner 30.

[0114] refer to Fig.18 , a barrier layer 32 may be formed on the first capping layer 29, respectively. The barrier layer 32 may be formed by an area selective deposition (ASD) process. For example, when the ASD method is applied, the barrier layer 32 may be selectively deposited on the second liner 31, and the barrier layer 32 may not be formed on the first liner 30, the inter-cell dielectric layer 20, and the semiconductor layer pattern 14A. The barrier layer 32 may not be formed on the first buffer layer BF1 and the second buffer layer BF2.

[0115] The barrier layer 32 may include silicon carbide oxide (SiCO) deposited by an ASD process, i.e., ASD-SiCO. Since the second liner 31 is silicon nitride, ASD-SiCO may be selectively deposited on the silicon nitride. The ASD process is a method of reducing the deposition rate only on a specific surface by using an inhibitor. For example, when silicon carbide oxide is deposited by an ASD process, the deposition on the surfaces of the first liner 30, the inter-cell dielectric layer 20, and the semiconductor layer pattern 14A may be suppressed, and silicon carbide oxide may be deposited on the surface of the second liner 31.

[0116] An example of a method for depositing silicon carbide by an ASD process may include selectively forming silicon carbide on silicon nitride among silicon oxide and silicon nitride by using an aminosilyl inhibitor. The aminosilyl inhibitor may be selectively adsorbed on the surface of silicon oxide among silicon oxide and silicon nitride. The aminosilyl inhibitor may include diisopropylaminosilane (DIPAS). The deposition of silicon carbide may be suppressed on silicon oxide to which the aminosilyl inhibitor is adsorbed, and the silicon carbide may be selectively deposited only on silicon nitride to which the aminosilyl inhibitor is not adsorbed.

[0117] According to another embodiment of the present invention, the barrier layer 32 may be formed by repeating the deposition and etching of silicon carbide multiple times. First, silicon carbide may be thinly deposited on silicon oxide to which the aminosilyl inhibitor is adsorbed, and silicon carbide may be thickly deposited on silicon nitride to which the aminosilyl inhibitor is not adsorbed. Subsequently, an etching process for etching silicon carbide may be performed. During the etching process of silicon carbide, thin silicon carbide may be removed from the upper portion of silicon oxide, and thin silicon carbide may remain on silicon oxide.

[0118] The thickness of the second liner 31 may be reinforced by the barrier layer 32. The thickness of the barrier layer 32 is approximately 15 to 20 nm.

[0119] refer to Fig.19 , an extension portion 33 may be formed between the vertically disposed barrier layers 32. To form the extension portion 33, a deposition process and an etch-back process of polysilicon may be performed. The extension portion 33 may be disposed on a first side of the semiconductor layer pattern 14A and a first side of the inter-cell dielectric layer 20. The extension portion 33 may also include undoped polysilicon.

[0120] refer to Fig. 20 , a vertical conductive line 35 coupled to the first edge portion of each semiconductor layer pattern 14A may be formed. The vertical conductive line 35 may fill the first hole-type opening 24. The vertical conductive line 35 may be commonly coupled to the semiconductor layer pattern 14A. The vertical conductive line 35 may include titanium nitride, tungsten, or a combination thereof. The vertical conductive line 35 may include a bit line.

[0121] Before forming the vertical conductive line 35, the first contact node 34 may be conformally formed above the first hole-shaped opening 24. The first contact node 34 may include doped polysilicon. After forming the first contact node 34, an annealing process may be performed subsequently. Therefore, the extension portion 33 may include impurities diffused from the first contact node 34.

[0122] According to another embodiment of the present invention, referring to Figure 1B , a first doping region SR may be formed in a first edge portion of the semiconductor layer pattern 14A. Forming the first doping region SR may include depositing polysilicon doped with N-type impurities, performing a heat treatment process, and removing the doped polysilicon. The first doping region SR may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the first doping region SR may be formed by a process of doping impurities. The first doping region SR may include impurities diffused from the first contact node 34.

[0123] As described above, when the barrier layer 32 is formed, the formation of bridges of the horizontal conductive lines 28 and the vertical conductive lines 35 can be prevented.

[0124] refer to Fig.21 , a portion of the vertical level sacrificial structure 23 may be removed to form a second hole-type opening 36A and a second capping layer 36. The second hole-type opening 36A may extend vertically from the surface of the lower structure 11. The remaining vertical level sacrificial structure, i.e., the second capping layer 36, may be disposed between the inter-cell dielectric layers 20. The second capping layer 36 may be disposed on a second side of the horizontal conductive line 28.

[0125] A second edge portion of the semiconductor layer pattern 14A may be exposed through the second hole-type opening 36A and the second capping layer 36 .

[0126] Subsequently, the semiconductor layer pattern 14A may be horizontally recessed. Thus, a horizontal layer HL may be formed. When the second capping layer 36 and the horizontal layer HL are formed, a storage opening 37 may be formed. The second end of the horizontal layer HL may be exposed through the storage opening 37. The storage opening 37 may be disposed between the inter-cell dielectric layers 20.

[0127] refer to Fig. 22 , a second contact node 38 may be formed on the second side of the horizontal layer HL. The second contact node 38 may include doped polysilicon. After forming the second contact node 38, an annealing process may then be performed.

[0128] According to another embodiment of the present invention, referring to Figure 1B, a second doping region DR may be formed in a second edge portion of the semiconductor layer pattern 14A. Forming the second doping region DR may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doping region DR may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the second doping region DR may be formed by a process of doping impurities. The second doping region DR may include impurities to be diffused from the second contact node 38.

[0129] Subsequently, a first electrode 39 of the data storage element may be formed on the second contact node 38. The first electrode 39 may have a horizontally oriented cylindrical shape.

[0130] refer to Fig.23 , the inter-cell dielectric layer 20 may be horizontally recessed (see reference numeral 40 ). Thus, the outer wall of the first electrode 39 may be exposed.

[0131] refer to Fig.24 , a dielectric layer 41 and a second electrode 42 may be sequentially formed on the first electrode 39. The first electrode 39, the dielectric layer 41 and the second electrode 42 may become a data storage element CAP.

[0132] The first electrode 39 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 39 may include a plurality of inner surfaces. The outer surface of the first electrode 39 may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 39 may contact the second contact node 38, and the horizontal outer surface of the first electrode 39 may contact the dielectric layer 41.

[0133] The inner space of the first electrode 39 may be a three-dimensional space. The dielectric layer 41 may conformally cover the inner and outer surfaces of the first electrode 39 .

[0134] The second electrode 42 may be disposed in a space inside the first electrode 39 over the dielectric layer 41 .

[0135] The first electrode 39 may have a cylindrical shape. The cylindrical shape of the first electrode 39 may include a cylindrical inner surface and a cylindrical outer surface. The dielectric layer 41 and the second electrode 42 may be disposed on the cylindrical inner surface of the first electrode 39.

[0136] The first electrode 39 and the second electrode 42 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 39 and the second electrode 42 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 42 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 42 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inner space of the first electrode 39, titanium nitride (TiN) may be used as the second electrode 42 of the capacitor CAP, and tungsten nitride may be a low-resistance material.

[0137] The dielectric layer 41 may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer 41 may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 41 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or titanium strontium oxide (SrTiO3). The dielectric layer 41 may include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HA (HfO2 / Al2O3) stack, a HAH (HfO2 / Al2O3 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0138] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode 39 and the dielectric layer 41. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN) or a combination thereof. The interface control layer may also be formed between the second electrode 42 and the dielectric layer 41.

[0139] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor device, comprising: Substructure; a plurality of horizontal layers oriented horizontally above the substructure; first conductive lines commonly coupled to first ends of the plurality of horizontal layers and extending in a direction perpendicular to the lower structure; a plurality of second conductive lines respectively crossing the plurality of horizontal layers; a plurality of data storage elements, which are respectively coupled to the second ends of the plurality of horizontal layers and are stacked in the direction perpendicular to the lower structure; a plurality of cover layers disposed between the plurality of second conductive lines and the first conductive line; as well as A plurality of barrier layers are disposed between the plurality of cover layers and the first conductive line.

2. The semiconductor device according to claim 1, wherein The barrier layer includes a dielectric material selectively grown from the capping layer.

3. The semiconductor device according to claim 1, wherein The barrier layer includes silicon oxycarbide.

4. The semiconductor device according to claim 1, wherein: The capping layer includes silicon oxide, silicon nitride or a combination thereof.

5. The semiconductor device according to claim 1, wherein Each of the cover layers includes a first liner and a second liner, the second liner being partially surrounded by the first liner, and Each of the barrier layers includes a material selectively deposited from a surface of the second liner.

6. The semiconductor device according to claim 5, wherein: The first liner includes silicon oxide, and The second liner includes silicon nitride, and The barrier layer includes silicon oxycarbide.

7. The semiconductor device according to claim 1, wherein The capping layer includes silicon nitride, and the barrier layer includes silicon oxycarbide.

8. The semiconductor device according to claim 1, further comprising: a first contact node surrounding an outer wall of the first conductive line; an extension portion disposed between the first contact node and the horizontal layer; as well as A second contact node is disposed between the data storage element and the horizontal layer.

9. The semiconductor device according to claim 8, wherein: The first contact node, the second contact node, and the extension portion include polysilicon.

10. The semiconductor device according to claim 8, wherein Each of the horizontal layers comprises: a first doped region coupled to the extension portion; a second doped region coupled to the second contact node; and A channel region is disposed between the first doping region and the second doping region.

11. The semiconductor device according to claim 10, wherein: Each of the first contact node and the second contact node includes doped polysilicon, and The first doped region includes impurities diffused from the first contact node, and The second doping region includes impurities diffused from the second contact node.

12. The semiconductor device according to claim 1, wherein The horizontal layer includes single crystal silicon.

13. The semiconductor device according to claim 1, wherein Each of the second conductive lines comprises: The double second conductive lines face each other in the vertical direction with the horizontal layer interposed therebetween.

14. The semiconductor device according to claim 1, wherein The data storage element includes a capacitor.

15. The semiconductor device according to claim 1, wherein Each of the data storage elements comprises: a first electrode coupled to each of the horizontal layers; a dielectric layer located on the first electrode; and a second electrode located on the dielectric layer, and Wherein, the first electrode has a horizontally oriented cylindrical shape.

16. A method for manufacturing a semiconductor device, comprising: Forming a horizontal layer above the substructure; forming horizontal conductive lines crossing the horizontal layers; forming a covering layer on the side surface of the horizontal conductive line; forming a barrier layer on the cover layer; forming a vertically oriented vertical conductive line over the barrier layer to couple to a first end of the horizontal layer; as well as A data storage element is formed coupled to the second end of the horizontal layer.

17. The method according to claim 16, wherein: Forming the barrier layer comprises: The barrier layer is selectively grown from a surface of the capping layer.

18. The method according to claim 17, wherein: In the step of selectively forming the barrier layer from the surface of the cover layer, The barrier layer is formed by an ASD method which is an area selective deposition method.

19. The method according to claim 16, wherein: The capping layer includes silicon nitride, and The barrier layer includes silicon oxycarbide.

20. The method according to claim 16, wherein: The capping layer comprises a stack of silicon oxide and silicon nitride, and The barrier layer includes silicon oxycarbide selectively deposited from a surface of the silicon nitride.

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