Memory structure and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a memory structure and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate, forming storage region stacking structures on the semiconductor substrate, and forming a spacer region between two adjacent storage region stacking structures; manufacturing an inter-gate isolation layer covering the side wall of the storage region stacking structure and a selection gate oxide layer covering the semiconductor substrate; manufacturing and forming selection gate polycrystalline silicon on the selection gate oxide layer, wherein the selection gate polycrystalline silicon is positioned on one side of the storage region stacking structure far away from the spacer region; a first interlayer dielectric layer is formed through deposition, and the storage area stacking structure and the selection gate polycrystalline silicon are located in the first interlayer dielectric layer; etching to remove the control gate polycrystalline silicon in the storage region stack structure to form an accommodating cavity; filling metal into the accommodating cavity to form a metal gate; and depositing to form a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the metal gate and the first interlayer dielectric layer.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a memory structure and a manufacturing method thereof. Background Art

[0002] SONOS is the acronym for Silicon-Oxide-Nitride-Oxide-Silicon, which is a non-volatile memory that is closely related to flash memory. It differs from mainstream flash memory in that it uses silicon nitride instead of polysilicon as the storage material. One of its offshoots is SHINOS (Silicon-High Dielectric-Nitride-Oxide-Silicon). SONOS allows lower programming voltage and higher program-erase cycles than polysilicon flash memory, and is a relatively active development and research hotspot.

[0003] The SONOS memory cell in the related art includes a control gate (CG) and a select gate (SG), wherein the control gate is used to store information and the select gate is used as a switch tube.

[0004] As chip area continues to shrink, the key dimensions of the active area and control gate of SONOS memory cells are also shrinking to improve product competitiveness. However, the reduction in control gate width will lead to a decrease in the threshold voltage window, and product reliability cannot be guaranteed. Summary of the invention

[0005] The present application provides a memory structure and a manufacturing method thereof, which can solve the problem in the related art that the reduction of the control gate width will lead to a decrease in the threshold voltage window.

[0006] In order to solve the technical problem in the background technology, the first aspect of the present application provides a method for manufacturing a memory structure, the method for manufacturing a memory structure comprising the following steps:

[0007] Providing a semiconductor substrate, on which a storage area stacking structure is formed, and a spacing area is formed between two adjacent storage area stacking structures;

[0008] Manufacturing an inter-gate isolation layer covering the sidewalls of the stacked structure in the storage area and a selection gate oxide layer covering the semiconductor substrate;

[0009] Forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located at a side of the storage area stack structure away from the spacer area;

[0010] Depositing to form a first interlayer dielectric layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer;

[0011] Etching and removing the control gate polysilicon in the storage area stack structure to form an accommodating cavity;

[0012] Filling metal into the accommodating cavity to form a metal grid;

[0013] A second interlayer dielectric layer is formed by deposition, wherein the second interlayer dielectric layer covers the metal gate and the first interlayer dielectric layer.

[0014] Optionally, the step of providing a semiconductor substrate and forming a storage area stacking structure on the semiconductor substrate includes:

[0015] providing a semiconductor substrate;

[0016] removing the pad oxide layer on the upper surface of the semiconductor substrate;

[0017] Depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer in sequence on the upper surface of the semiconductor substrate;

[0018] Defining a storage area photolithography pattern on the control gate mask layer;

[0019] The ONO layer, the control gate polysilicon layer and the control gate mask layer are etched based on the storage area photolithography pattern to form a storage area stacking structure, and a spacing area is formed between two adjacent storage area stacking structures.

[0020] Optionally, the step of manufacturing an inter-gate isolation layer covering the sidewalls of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate includes:

[0021] According to the morphology of the semiconductor substrate with the storage area stacking structure, sequentially depositing an isolation oxide layer and an isolation nitride layer on the semiconductor substrate;

[0022] Using the isolation oxide layer as an etching stop layer, dry etching the isolation nitride layer, and the remaining isolation nitride layer covers the sidewalls of the storage area stack structure;

[0023] removing the exposed isolation oxide layer by a wet process;

[0024] A select gate oxide layer is formed by deposition, and the select gate oxide layer covers the exposed upper surface of the semiconductor substrate and the side surface of the isolation nitride layer.

[0025] Optionally, the step of forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located on a side of the storage area stack structure away from the spacer area, comprises:

[0026] Depositing select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon wraps the storage area stack structure;

[0027] Depositing a select gate mask layer on the select gate polysilicon;

[0028] Performing a first self-aligned dry etching on the select gate polysilicon with the select gate mask layer, removing the select gate mask layer vertically and thinning the select gate polysilicon, so that the remaining select gate polysilicon is flush with the storage area stacking structure in the vertical direction;

[0029] removing the remaining select gate mask layer covering the side of the select gate polysilicon by wet etching;

[0030] Performing a second self-aligned dry etching on the remaining selection gate polysilicon to thin the selection gate polysilicon in the vertical direction, so that the height of the remaining selection gate polysilicon in the vertical direction is lower than the stacked structure with the storage area;

[0031] The select gate polysilicon located at the spacer region is removed, and the remaining select gate polysilicon is located at a sidewall position of the storage region stack structure away from the spacer region.

[0032] Optionally, after the step of forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located on a side of the storage area stack structure away from the spacer, and before the step of depositing to form a first interlayer dielectric layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer, the following steps are further performed:

[0033] Forming sidewalls on the exposed sidewalls of the storage area stack structure and the exposed sidewalls of the select gate polysilicon;

[0034] Forming a metal silicide barrier layer on the upper surface of the select gate polysilicon and the exposed upper surface of the semiconductor substrate;

[0035] A platinum-nickel alloy layer is blanket deposited.

[0036] Optionally, the step of depositing to form a first interlayer dielectric layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer, comprises:

[0037] Depositing a first interlayer dielectric layer on the nickel-platinum alloy layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer;

[0038] The upper surface of the first interlayer dielectric layer is planarized by a chemical mechanical polishing process until the upper surface of the storage area stack structure is exposed.

[0039] In order to solve the technical problem in the background technology, the second aspect of the present application provides a memory structure, and the memory structure is manufactured by the manufacturing method of the memory structure described in the first aspect of the present application.

[0040] The technical solution of the present application includes at least the following advantages: the manufacturing method of the memory structure provided by the present application and the memory structure manufactured thereby can eliminate the control gate polysilicon loss effect, increase the electric field strength during voltage operation and the control gate polysilicon threshold voltage window, and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A flow chart of a method for manufacturing a memory structure provided by an embodiment of the present application is shown;

[0043] Figure 2 A schematic diagram of a semiconductor substrate structure with a stacked storage area structure is shown;

[0044] Figure 3 A schematic diagram of a cross-sectional structure of the device after step S21 is completed is shown;

[0045] Figure 4 A schematic diagram of a cross-sectional structure of the device after step S22 is completed is shown;

[0046] Figure 5 A schematic diagram of a cross-sectional structure of the device after step S24 is completed is shown;

[0047] Figure 6 A schematic diagram of a cross-sectional structure of the device after step S32 is completed is shown;

[0048] Figure 7 A schematic diagram of the cross-sectional structure of the device after step S33 is completed is shown;

[0049] Figure 8 A schematic diagram of the cross-sectional structure of the device after step S35 is completed is shown;

[0050] Fig. 9 A schematic diagram of the cross-sectional structure of the device after step S36 is completed is shown;

[0051] Fig.10 A schematic diagram of the cross-sectional structure of the device after step S4 is completed is shown;

[0052] Fig.11 A schematic diagram of the cross-sectional structure of the device after step S5 is completed is shown;

[0053] Fig.12 A schematic diagram of the cross-sectional structure of the device after step S6 is completed is shown;

[0054] Fig.13 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S7 is completed. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0057] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0058] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0059] Figure 1 A flow chart of a method for manufacturing a memory structure provided by an embodiment of the present application is shown.

[0060] from Figure 1 As can be seen from the figure, the manufacturing method of the memory structure includes the following steps:

[0061] Step S1: providing a semiconductor substrate, on which a storage area stacking structure is formed, and a spacing area is formed between two adjacent storage area stacking structures.

[0062] Reference Figure 2 , which shows a schematic diagram of a semiconductor substrate structure with a stacked storage area structure. Figure 2 It can be seen from the figure that the semiconductor substrate 100 is formed with storage region stacking structures CG spaced apart from each other, and a spacing region is formed between two adjacent storage region stacking structures CG.

[0063] Exemplarily, step S1 may be implemented according to the following steps S11 to S15.

[0064] Step S11: providing a semiconductor substrate.

[0065] The semiconductor substrate includes a bulk semiconductor substrate or a silicon on insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloy, compound semiconductor (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or its alloy (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductor (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or a combination thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed orientation substrates.

[0066] Step S12: removing the pad oxide layer on the upper surface of the semiconductor substrate.

[0067] Generally, a pad oxide layer is formed on the semiconductor substrate provided, and before manufacturing the storage area stack structure CG on the semiconductor substrate, the pad oxide layer needs to be removed first. Exemplarily, the pad oxide layer can be removed by a wet process.

[0068] Step S13: depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer in sequence on the upper surface of the semiconductor substrate.

[0069] The ONO layer includes a bottom oxide layer, a nitride layer and an upper oxide layer sequentially covering the semiconductor substrate from bottom to top, and the control gate mask layer can be made of PESiN. The thickness of the control gate mask layer is 400A.

[0070] Step S14: defining a storage area photolithography pattern on the control gate mask layer.

[0071] Step S15: etching the ONO layer, the control gate polysilicon layer and the control gate mask layer based on the storage area photolithography pattern to form a storage area stacking structure, and forming a spacer area between two adjacent storage area stacking structures.

[0072] After step S15 is completed, Figure 2 The device structure shown.

[0073] Step S2: manufacturing an inter-gate isolation layer covering the sidewalls of the stacked structure in the storage area and a selection gate oxide layer covering the semiconductor substrate.

[0074] The inter-gate isolation layer covering the side wall of the storage area stack structure is a structure formed by an oxide layer-nitride layer-oxide layer.

[0075] The step S2 can be implemented according to the following steps S21 to S24:

[0076] Step S21: according to the morphology of the semiconductor substrate with the storage area stacking structure, an isolation oxide layer and an isolation nitride layer are sequentially deposited on the semiconductor substrate.

[0077] Reference Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after step S21 is completed. Figure 3 It can be seen that the formed isolation oxide layer 210 and isolation nitride layer 220 are covered on the semiconductor substrate 100 according to the morphology of the semiconductor substrate 100 with the storage area stacking structure CG. That is, the isolation oxide layer 210 is located at the lower layer of the isolation nitride layer 220, and the isolation oxide layer 210 covers the exposed upper surface of the semiconductor substrate 100 and covers the side and upper surface of the storage area stacking structure CG. The isolation oxide layer 210 covering the exposed upper surface of the semiconductor substrate 100 covers the spacer between two adjacent storage area stacking structures CG.

[0078] Step S22: using the isolation oxide layer as an etching stop layer, dry-etching the isolation nitride layer, and the remaining isolation nitride layer covers the sidewalls of the storage area stack structure.

[0079] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S22 is completed. Figure 4 It can be seen that due to the anisotropy of dry etching, the etching rate on the front side of the isolation nitride layer 220 is greater than the etching rate on the side of the isolation nitride layer 220. Therefore, after the dry etching is completed, the isolation nitride layer 220 covering the exposed upper surface of the semiconductor substrate 100 and the upper surface of the storage area stack structure CG is etched away, and the isolation nitride layer 220 covering the side of the storage area stack structure CG is retained.

[0080] Step S23: removing the exposed isolation oxide layer by a wet process.

[0081] During the wet process, since the isolation nitride layer 220 covering the side of the storage area stack structure CG is retained, the retained isolation nitride layer 220 protects the isolation oxide layer 210 thereunder, so that the wet process removes the isolation oxide layer 210 covering the exposed upper surface of the semiconductor substrate 100 and the upper surface of the storage area stack structure CG. The remaining isolation oxide layer 210 and isolation nitride layer 220 cover the side of the storage area stack structure CG.

[0082] Step S24: depositing and forming a select gate oxide layer, wherein the select gate oxide layer covers the exposed upper surface of the semiconductor substrate and the side surfaces of the isolation nitride layer.

[0083] Exemplarily, the select gate oxide layer may be formed by deposition through an ISSG process.

[0084] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S24 is completed. Figure 5 It can be seen that the side surfaces of the storage area stack structure CG are sequentially covered with the isolation oxide layer 210 , the isolation nitride layer 220 and the selection gate oxide layer 230 , and the exposed upper surface of the semiconductor substrate 100 is covered with the selection gate oxide layer 230 .

[0085] Step S3: forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located at a side of the storage area stack structure away from the spacer area.

[0086] Exemplarily, step S3 may be implemented according to the following steps S31 to S36:

[0087] Step S31: depositing select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon wraps the storage area stack structure.

[0088] Step S32: depositing a select gate mask layer on the select gate polysilicon.

[0089] Reference Figure 6 , which shows a schematic diagram of the cross-sectional structure of the device after step S32 is completed. Figure 6 It can be seen that the selection gate polysilicon 310 deposited in step S32 covers and wraps the storage area stacking structure CG, that is, the selection gate polysilicon 310 fills the spacing area formed between two adjacent storage area stacking structures CG, and the selection gate mask layer 320 covers the selection gate polysilicon 310.

[0090] Step S33: performing a first self-aligned dry etching on the select gate polysilicon with the select gate mask layer, removing the select gate mask layer vertically and thinning the select gate polysilicon, so that the remaining select gate polysilicon is flush with the storage area stacking structure in the vertical direction.

[0091] Reference Figure 7 , which shows a schematic diagram of the cross-sectional structure of the device after step S33 is completed. Figure 7 It can be seen that, by utilizing the anisotropy of dry etching, the etching rate on the front side is greater than the etching rate on the side side, and the selection gate mask layer 320 is removed longitudinally and the selection gate polysilicon 310 is thinned by the first self-aligned dry etching, so that the selection gate polysilicon 310 covering the storage area stack structure CG is flush with the storage area stack structure CG, and the selection gate polysilicon 310 covering the exposed upper surface of the semiconductor substrate 100 is thinned. The remaining selection gate mask layer 320 covers the outside of the selection gate polysilicon 310 on the side of the storage area stack structure CG.

[0092] Step S34: removing the remaining select gate mask layer covering the side of the select gate polysilicon by wet etching.

[0093] Exemplarily, the select gate mask layer covering the side of the select gate polysilicon may be removed by phosphoric acid etching.

[0094] Step S35: performing a second self-aligned dry etching on the remaining select gate polysilicon to thin the select gate polysilicon in the longitudinal direction, so that the height of the remaining select gate polysilicon in the longitudinal direction is lower than the stacked structure with the storage area.

[0095] Due to the etching blocking effect of the control gate mask layer at the top of the storage area stacking structure CG on the second self-aligned dry etching, the second self-aligned dry etching continues to thin the selection gate polysilicon in the vertical direction, so that the remaining selection gate polysilicon is lower in the vertical direction than the storage area stacking structure.

[0096] Reference Figure 8 , which shows a schematic diagram of the cross-sectional structure of the device after step S35 is completed. Figure 8 It can be seen that after the second self-aligned dry etching is completed, the selection gate polysilicon 310 located in the spacing area between two adjacent storage area stacking structures CG and the selection gate polysilicon 310 located on one side of the storage area stacking structure CG away from the spacing area are retained, and the remaining selection gate polysilicon 310 is lower than the height of the storage area stacking structure CG.

[0097] Step S36: removing the select gate polysilicon located at the spacer region, and the remaining select gate polysilicon is located at the sidewall of the storage region stack structure away from the spacer region.

[0098] For example, the select gate polysilicon at the spacer region may be removed by a photolithography and etching process.

[0099] Reference Fig. 9 , which shows a schematic diagram of the cross-sectional structure of the device after step S36 is completed, from Fig. 9 It can be seen that after step S36 is completed, the remaining selection gate polysilicon 310 is located at the side wall position of the storage area stack structure CG away from the spacer area.

[0100] Step S4: depositing to form a first interlayer dielectric layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer.

[0101] Exemplarily, a first interlayer dielectric layer may be deposited first, the first interlayer dielectric layer wrapping the storage area stack structure and the select gate polysilicon, and then a chemical mechanical polishing process is used to flatten the upper surface of the first interlayer dielectric layer until the upper surface of the storage area stack structure is exposed.

[0102] Reference Fig.10 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed. Fig.10 It can be seen that the first interlayer dielectric layer 410 wraps the storage region stack structure CG and the selection gate polysilicon 310 , and the upper surface of the storage region stack structure CG is exposed from the first interlayer dielectric layer 410 .

[0103] Optionally, after step S3 is completed, the following steps S41 to S43 may be performed before step S4 is performed:

[0104] Step S41: forming sidewalls on the exposed sidewalls of the storage area stack structure and the exposed sidewalls of the select gate polysilicon.

[0105] For example, deposition and etching processes may be used to form sidewalls covering the exposed sidewalls of the storage area stack structure and the exposed sidewalls of the select gate polysilicon. The sidewalls may be made of silicon nitride.

[0106] Step S42: forming a metal silicide barrier layer on the upper surface of the select gate polysilicon and the exposed upper surface of the semiconductor substrate.

[0107] Step S43: blanket depositing a platinum-nickel alloy layer.

[0108] Exemplarily, the platinum-nickel alloy layer covers the exposed surface of the select gate polysilicon, the exposed surface of the storage area stack structure, and the exposed surface of the semiconductor base layer.

[0109] Step S5: etching and removing the control gate polysilicon in the storage area stack structure to form an accommodating cavity.

[0110] Exemplarily, the control gate polysilicon in the storage area stack structure may be etched away by a photolithography and etching process to form the accommodating cavity.

[0111] Reference Fig.11 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed. Fig.11 It can be seen from the figure that after the control gate polysilicon is removed, an accommodation cavity 510 is formed at the original position of the control gate polysilicon.

[0112] Step S6: filling metal into the accommodating cavity to form a metal gate.

[0113] Illustratively, in the process of manufacturing the metal gate, metal may be deposited to fill the accommodating cavity, and then a chemical mechanical polishing process is performed to planarize the upper surface of the metal gate.

[0114] Reference Fig.12 , which shows a schematic diagram of the cross-sectional structure of the device after step S6 is completed. Fig.12 As can be seen from the figure, the accommodating cavity 510 is filled with a metal gate 520 .

[0115] Step S7: depositing to form a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the metal gate and the first interlayer dielectric layer.

[0116] Reference Fig.13 , which shows a schematic diagram of the cross-sectional structure of the device after step S7 is completed. Fig.13 As can be seen in FIG. 4 , the second interlayer dielectric layer 420 covers the metal gate 520 and the first interlayer dielectric layer 410 .

[0117] In subsequent processes, a contact hole structure may be fabricated.

[0118] The present application also provides a memory structure, which has Figure 1 The memory structure shown is manufactured by the manufacturing method.

[0119] The manufacturing method of the memory structure provided in the present application and the memory structure manufactured thereby can eliminate the control gate polysilicon loss effect, increase the electric field strength during voltage operation and the control gate polysilicon threshold voltage window, and improve the reliability of the device.

[0120] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a memory structure, characterized in that: The manufacturing method of the memory structure comprises the following steps: Providing a semiconductor substrate, on which a storage area stacking structure is formed, and a spacing area is formed between two adjacent storage area stacking structures; Manufacturing an inter-gate isolation layer covering the sidewalls of the stacked structure in the storage area and a selection gate oxide layer covering the semiconductor substrate; Forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located at a side of the storage area stack structure away from the spacer area; Depositing to form a first interlayer dielectric layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer; Etching and removing the control gate polysilicon in the storage area stack structure to form an accommodating cavity; Filling metal into the accommodating cavity to form a metal grid; A second interlayer dielectric layer is formed by deposition, wherein the second interlayer dielectric layer covers the metal gate and the first interlayer dielectric layer.

2. The method for manufacturing a memory structure according to claim 1, wherein: The step of providing a semiconductor substrate and forming a storage area stacking structure on the semiconductor substrate comprises: providing a semiconductor substrate; removing the pad oxide layer on the upper surface of the semiconductor substrate; Depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer in sequence on the upper surface of the semiconductor substrate; Defining a storage area photolithography pattern on the control gate mask layer; The ONO layer, the control gate polysilicon layer and the control gate mask layer are etched based on the storage area photolithography pattern to form a storage area stacking structure, and a spacing area is formed between two adjacent storage area stacking structures.

3. The method for manufacturing a memory structure according to claim 1, wherein: The step of manufacturing an inter-gate isolation layer covering the sidewalls of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate comprises: According to the morphology of the semiconductor substrate with the storage area stacking structure, sequentially depositing an isolation oxide layer and an isolation nitride layer on the semiconductor substrate; Using the isolation oxide layer as an etching stop layer, dry etching the isolation nitride layer, and the remaining isolation nitride layer covers the sidewalls of the storage area stack structure; removing the exposed isolation oxide layer by a wet process; A select gate oxide layer is formed by deposition, and the select gate oxide layer covers the exposed upper surface of the semiconductor substrate and the side surface of the isolation nitride layer.

4. The method for manufacturing a memory structure according to claim 1, wherein: The step of forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located on a side of the storage area stack structure away from the spacer area, comprises: Depositing select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon wraps the storage area stack structure; Depositing a select gate mask layer on the select gate polysilicon; Performing a first self-aligned dry etching on the select gate polysilicon with the select gate mask layer, removing the select gate mask layer vertically and thinning the select gate polysilicon, so that the remaining select gate polysilicon is flush with the storage area stacking structure in the vertical direction; removing the remaining select gate mask layer covering the side of the select gate polysilicon by wet etching; Performing a second self-aligned dry etching on the remaining selection gate polysilicon to thin the selection gate polysilicon in the vertical direction, so that the height of the remaining selection gate polysilicon in the vertical direction is lower than the stacked structure with the storage area; The select gate polysilicon located at the spacer region is removed, and the remaining select gate polysilicon is located at a sidewall position of the storage region stack structure away from the spacer region.

5. The method for manufacturing a memory structure according to claim 1, wherein: After the step of forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located on a side of the storage area stack structure away from the spacer, the following steps are further performed before the step of depositing to form a first interlayer dielectric layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer: Forming sidewalls on the exposed sidewalls of the storage area stack structure and the exposed sidewalls of the select gate polysilicon; Forming a metal silicide barrier layer on the upper surface of the select gate polysilicon and the exposed upper surface of the semiconductor substrate; A platinum-nickel alloy layer is blanket deposited.

6. The method for manufacturing a memory structure according to claim 5, wherein: The step of depositing to form a first interlayer dielectric layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer, comprises: Depositing a first interlayer dielectric layer on the nickel-platinum alloy layer, wherein the storage area stack structure and the select gate polysilicon are located in the first interlayer dielectric layer; The upper surface of the first interlayer dielectric layer is planarized by a chemical mechanical polishing process until the upper surface of the storage area stack structure is exposed.

7. A memory structure, characterized in that: The memory structure is manufactured by the memory structure manufacturing method according to any one of claims 1 to 6.

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