Clock alignment method, device and system for digital and semi-physical real-time simulation

Abstract

The invention provides a clock alignment method, device and system for digital and semi-physical real-time simulation. The method comprises the following steps: generating a reference clock signal; whether a hardware model clock signal is aligned with a reference clock signal is detected, and if not, the hardware model clock signal is adjusted, so that the hardware model clock signal is aligned with the reference clock signal; whether the digital model clock signal is aligned with the reference clock signal is detected, and if not, the digital model clock signal is adjusted, so that the digital model clock signal is aligned with the reference clock signal. The method can be applied to a digital and semi-physical real-time simulation system, ensures accurate virtual and real synchronization of digital simulation and semi-physical hardware equipment, and improves the overall accuracy and stability of the system.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of clock alignment, and in particular to a clock alignment method, device and system for digital and semi-physical real-time simulation. Background Art

[0002] Clock alignment methods are widely used to achieve clock synchronization in distributed systems or multi-mode systems, aiming to ensure that the clock signals of various devices or processors remain synchronized so that they can work together and maintain consistent timing. Clock alignment methods usually include some protocols and algorithms for measuring and adjusting the clock signals of various devices or processors so that they can work together and maintain synchronization.

[0003] Traditional clock alignment methods are mainly aimed at two scenarios: all-digital and semi-physical. In the all-digital simulation scenario, the clock control of the digital simulation engine is mainly achieved by upper computer software coding, and the clock pace depends on the software running state. Specifically, the signals in different clock domains are processed by sampling and interpolation to achieve synchronization and alignment of clock signals. Digital processing provides higher accuracy and stability, but it is limited by the accuracy of digital signal processing and clock resolution, and it may not be possible to completely eliminate clock offset and phase difference. In addition, the complexity of the interpolation algorithm is high, which may increase the computational burden and delay of the system. For large-scale systems, additional hardware resources may be required to implement it, increasing the cost and complexity of the system.

[0004] In a semi-physical simulation scenario, the clock alignment algorithm synchronizes the clock signal of the virtual simulation system with the clock signal of the actual physical system through hardware devices or interface modules to achieve the transmission and processing of digital signals. Although it can provide a highly consistent simulation experience and high accuracy and stability, it requires additional hardware devices or interface modules for clock alignment, which increases the complexity and cost of the system and may be limited by hardware performance and communication delays.

[0005] With the continuous development of industrial level, in order to obtain a more realistic simulation environment and improve the reliability and stability of the system, a digital and semi-physical real-time simulation system has been proposed. The system involves both software and hardware. The software clock needs to be strictly consistent with the hardware clock. An additional synchronization controller or network protocol is required for clock alignment, which increases the complexity and cost of the system and may be affected by factors such as communication delays. In addition, the existing technology does not adequately handle the accuracy of clock synchronization and the uniformity of time intervals, and the time fidelity of the deduction process is not high. Summary of the invention

[0006] In view of the technical problems existing in the prior art, the present invention proposes a clock alignment method, device and system for digital and semi-physical real-time simulation.

[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0008] On the one hand, the present invention provides a clock alignment method for digital and semi-physical real-time simulation, comprising:

[0009] generating a reference clock signal;

[0010] By detecting the phase relationship between the hardware model clock signal and the reference clock signal, judging whether the hardware model clock signal is aligned with the reference clock signal based on the phase relationship between the hardware model clock signal and the reference clock signal, if the hardware model clock signal and the reference clock signal are not aligned, adjusting the hardware model clock signal so that the hardware model clock signal is aligned with the reference clock signal;

[0011] By detecting the phase relationship between the digital model clock signal and the reference clock signal, it is determined whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal. If the digital model clock signal and the reference clock signal are not aligned, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal.

[0012] On the other hand, the present invention provides a clock alignment device for digital and semi-physical real-time simulation, comprising:

[0013] A reference clock signal generating module, used for generating a reference clock signal;

[0014] A hardware model clock signal and reference clock signal alignment module, used to detect the phase relationship between the hardware model clock signal and the reference clock signal, and determine whether the hardware model clock signal is aligned with the reference clock signal based on the phase relationship between the hardware model clock signal and the reference clock signal. If the hardware model clock signal and the reference clock signal are not aligned, the hardware model clock signal is adjusted so that the hardware model clock signal is aligned with the reference clock signal.

[0015] The digital model clock signal and the reference clock signal alignment module is used to detect the phase relationship between the digital model clock signal and the reference clock signal, and determine whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal. If the digital model clock signal and the reference clock signal are not aligned, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal.

[0016] On the other hand, the present invention provides a digital and semi-physical real-time simulation system, which uses the above-mentioned clock alignment method for digital and semi-physical real-time simulation to achieve clock alignment of hardware model clock signals, digital model clock signals and reference clock signals.

[0017] Compared with the prior art, the technical effects of the present invention are:

[0018] The present invention can be applied to digital and semi-physical real-time simulation systems to ensure accurate virtual-real synchronization of digital simulation and semi-physical hardware devices, thereby improving the overall accuracy and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0020] Figure 1 It is a flow chart of a clock alignment method for digital and semi-physical real-time simulation provided by an embodiment;

[0021] Figure 2 It is a framework diagram of a digital and semi-physical real-time simulation system provided by an embodiment;

[0022] Figure 3 It is a schematic diagram of the structure of a hardware clock generator unit in one embodiment. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In one embodiment, a clock alignment method for digital and semi-physical real-time simulation is provided, comprising:

[0025] (1) Generate a reference clock signal;

[0026] (2) Align the hardware model clock signal with the reference clock signal;

[0027] In step (2), by detecting the phase relationship between the hardware model clock signal and the reference clock signal, it is determined whether the hardware model clock signal is aligned with the reference clock signal based on the phase relationship between the hardware model clock signal and the reference clock signal. If the hardware model clock signal and the reference clock signal are not aligned, the hardware model clock signal is adjusted so that the hardware model clock signal is aligned with the reference clock signal.

[0028] (3) Aligning the digital model clock signal with the reference clock signal;

[0029] Step (3) determines whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal by detecting the phase relationship between the digital model clock signal and the reference clock signal. If the digital model clock signal and the reference clock signal are not aligned, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal.

[0030] It can be understood that in the above embodiment, the hardware model clock signal is first aligned with the reference clock signal, and then the digital model clock signal is aligned with the reference clock signal. In actual applications, the digital model clock signal and the reference clock signal may be aligned first, and then the hardware model clock signal and the reference clock signal may be aligned. The present invention does not limit the specific order.

[0031] The present invention introduces a reference clock signal to align the clock signals of the hardware model and the digital model, thereby ensuring that the time intervals of the simulation details between the digital model and the hardware model are uniformly controlled. This means that in a real-time simulation parallel test system, the time deduction and synchronization of each simulation detail will be more accurate and consistent, thereby improving the simulation accuracy and reliability of the entire system.

[0032] In step (1), a reference clock signal can be generated by using a crystal oscillator, wherein the crystal oscillator includes a crystal resonator and a feedback loop, wherein a controller is provided in the feedback loop, and an electric field or mechanical stress is applied to the crystal resonator, and the crystal resonator vibrates at its natural frequency and outputs a signal, and a part of the output signal is input into the feedback loop, and the controller in the feedback loop generates an electric field or mechanical stress control signal applied to the crystal resonator according to the output signal, thereby enhancing the oscillation of the crystal, forming a closed-loop oscillation, and causing the crystal oscillator to output an oscillation signal of a predetermined frequency as the reference clock signal.

[0033] Specifically, the main principle of using a crystal oscillator to generate a reference clock signal in one embodiment is as follows:

[0034] Crystal resonance: A crystal oscillator contains a crystal resonator, usually a quartz crystal. The crystal resonator has a natural resonant frequency, and when an electric field or mechanical stress is applied to the crystal resonator, the crystal resonator will vibrate at its natural frequency.

[0035] Feedback loop: The crystal oscillator contains a feedback loop that feeds a portion of the output signal back to the crystal resonator. When the output signal passes through the feedback loop and is input to the crystal resonator again, the oscillation of the crystal is enhanced, forming a closed-loop oscillation.

[0036] The crystal oscillator satisfies the oscillation conditions by adjusting the gain and phase in the feedback loop, so that the system can stably generate an oscillation signal of a predetermined frequency. Due to the inherent characteristics of the crystal resonator and the adjustment of the feedback loop, the crystal oscillator can provide a very stable and accurate clock signal, which is suitable for application scenarios that require high-precision clocks.

[0037] In order to align the hardware model clock signal with the reference clock signal, the present invention synchronizes and calibrates the hardware model clock signal of the hardware model according to the reference clock signal and the hardware model clock signal, ensuring that the hardware model clock signal is aligned with the reference clock signal, and ensuring that the hardware model is consistent with the reference clock signal during the simulation process. This can be achieved by adjusting the clock frequency, delay and other parameters of the hardware model clock signal.

[0038] Regarding the method for judging whether the hardware model clock signal is aligned with the reference clock signal, an embodiment of the present invention proposes to compare the phase difference between the hardware model clock signal and the reference clock signal. If the phase difference approaches zero, the hardware model clock signal is aligned with the reference clock signal. In a specific implementation, a phase frequency detector (PFD) can be used to compare the phase difference between the hardware model clock signal output by the hardware model and the reference clock signal, and output a corresponding error signal. After the error signal is processed by a low-pass filter, a control voltage signal is generated to adjust the frequency of the hardware model clock signal output by the hardware model so that the output hardware model clock signal is aligned with the reference clock signal. By monitoring the error signal output by the phase frequency detector (PFD), when the error signal approaches zero, the hardware model clock signal is aligned with the reference clock signal. The judgment method of the error signal approaching zero can be judged by setting a threshold approaching zero, that is, if the error signal is less than the set threshold, it is considered that the output hardware model clock signal is aligned with the reference clock signal.

[0039] Regarding the method for determining whether the digital model clock signal is aligned with the reference clock signal, an embodiment of the present invention proposes to compare the phase relationship between the digital model clock signal output by the digital model and the reference clock signal. When the phase relationship approaches zero, the digital model clock signal of the digital model is aligned with the reference clock signal. When it is determined that the digital model clock signal of the digital model is not aligned with the reference clock signal, a digital frequency synthesizer can be used to adjust the frequency of the digital model clock signal output by the digital model through digital control, so that the digital model clock signal output by the digital model is aligned with the reference clock signal.

[0040] In one embodiment, a clock alignment method for digital and semi-physical real-time simulation is provided. In step (2), if the hardware model clock signal is not aligned with the reference clock signal, the hardware model clock signal is adjusted so that the hardware model clock signal is aligned with the reference clock signal. The method includes:

[0041] Generate a corresponding error signal according to the phase difference between the hardware model clock signal and the reference clock signal, so as to characterize the phase difference between the hardware model clock signal and the reference clock signal;

[0042] Performing low-pass filtering on the error signal to obtain a corresponding control voltage signal;

[0043] The hardware model clock signal is adjusted based on the control voltage signal so that the hardware model clock signal is aligned with the reference clock signal.

[0044] The error signal is usually a time series that reflects the difference between the actual phase value and the expected phase value. The error signal is input into a low-pass filter. A low-pass filter is a signal processor that allows low-frequency signals to pass through and blocks high-frequency signals. Through low-pass filtering, high-frequency noise and interference signals are filtered out to obtain a smooth control signal. The signal after low-pass filtering will be converted into a corresponding control voltage signal. This process can be achieved through a digital-to-analog converter (DAC) to convert the digital signal into an analog voltage signal. The size and polarity of the control voltage signal will be adjusted according to the error signal after low-pass filtering to achieve control of the system.

[0045] In one embodiment, a clock alignment method for digital and semi-physical real-time simulation is provided. In step (3), if the digital model clock signal is not aligned with the reference clock signal, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal. The method includes:

[0046] inputting a reference clock signal and a digital control word into a digital frequency synthesizer;

[0047] A digital model clock signal is generated by a digital frequency synthesizer, wherein the digital frequency synthesizer adjusts the frequency of the digital model clock signal according to the digital control word so that the generated digital model clock signal is aligned with the reference clock signal.

[0048] In one embodiment, a clock alignment method for digital and semi-physical real-time simulation is provided. In step (2), a phase relationship between a hardware model clock signal and a reference clock signal is detected. Based on the phase relationship between the hardware model clock signal and the reference clock signal, it is determined whether the hardware model clock signal is aligned with the reference clock signal. The method includes:

[0049] Capture the rising edge or falling edge of the hardware model clock signal and the reference clock signal respectively;

[0050] When the rising edge or falling edge of the hardware model clock signal or the reference clock signal is detected, an interrupt is triggered and the corresponding timestamp is recorded;

[0051] Calculate the time difference between the hardware model clock signal and the reference clock signal according to the timestamp corresponding to the interrupt triggered by the hardware model clock signal and the timestamp corresponding to the interrupt triggered by the reference clock signal;

[0052] The phase difference between the hardware model clock signal and the reference clock signal is characterized based on the time difference. When the time difference is less than a set threshold, the hardware model clock signal is aligned with the reference clock signal. When the time difference is greater than or equal to the set threshold, the hardware model clock signal is not aligned with the reference clock signal.

[0053] In one embodiment, a clock alignment method for digital and semi-physical real-time simulation is provided. In step (3), by detecting the phase relationship between the digital model clock signal and the reference clock signal, it is determined whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal. The method includes:

[0054] Capturing the rising edge or falling edge of the digital model clock signal and the reference clock signal respectively;

[0055] When a rising edge or falling edge of a digital model clock signal or a reference clock signal is detected, an interrupt is triggered and a corresponding timestamp is recorded;

[0056] Calculate the time difference between the digital model clock signal and the reference clock signal according to the timestamp corresponding to the interrupt triggered by the digital model clock signal and the timestamp corresponding to the interrupt triggered by the reference clock signal;

[0057] The phase difference between the digital model clock signal and the reference clock signal is characterized based on the time difference. When the time difference is less than a set threshold, the digital model clock signal is aligned with the reference clock signal. When the time difference is greater than or equal to the set threshold, the digital model clock signal is not aligned with the reference clock signal.

[0058] Furthermore, any of the above embodiments of the present invention may also include simultaneously monitoring the phase relationship between the hardware model clock signal, the digital model clock signal and the reference clock signal. When the phase differences between the monitored hardware model clock signal, the digital model clock signal and the reference clock signal are close to zero, the hardware model clock signal, the digital model clock signal and the reference clock signal are all aligned.

[0059] Specifically, the hardware model clock signal, the digital model clock signal and the reference clock signal are extracted at the same time. These clock signals are usually periodic signals used to synchronize the operation of each corresponding module. A phase comparison circuit is established to receive the hardware model clock signal, the digital model clock signal and the reference clock signal as input, and compare the phase relationship between the hardware model clock signal, the digital model clock signal and the reference clock signal. The phase comparison circuit can be implemented by a phase comparator or a digital signal processor. The phase comparison circuit will output a signal representing the phase difference between the hardware model clock signal, the digital model clock signal and the reference clock signal. This phase difference can be expressed as a time difference or an angle difference, which is used to describe the relative position relationship between the hardware model clock signal, the digital model clock signal and the reference clock signal. The phase difference signal is processed to calculate the specific phase difference value. These data can be output through a display or a data interface for users to monitor and analyze.

[0060] In another embodiment, a clock alignment device for digital and semi-physical real-time simulation is provided, comprising:

[0061] A reference clock signal generating module, used for generating a reference clock signal;

[0062] A hardware model clock signal and reference clock signal alignment module, used to detect the phase relationship between the hardware model clock signal and the reference clock signal, and determine whether the hardware model clock signal is aligned with the reference clock signal based on the phase relationship between the hardware model clock signal and the reference clock signal. If the hardware model clock signal and the reference clock signal are not aligned, the hardware model clock signal is adjusted so that the hardware model clock signal is aligned with the reference clock signal.

[0063] The digital model clock signal and the reference clock signal alignment module is used to detect the phase relationship between the digital model clock signal and the reference clock signal, and determine whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal. If the digital model clock signal and the reference clock signal are not aligned, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal.

[0064] Furthermore, it also includes an overall clock alignment module, which is used to simultaneously monitor the phase relationship between the hardware model clock signal, the digital model clock signal and the reference clock signal. When the phase differences between the monitored hardware model clock signal, the digital model clock signal and the reference clock signal are close to zero, the hardware model clock signal, the digital model clock signal and the reference clock signal are all aligned.

[0065] On the other hand, a digital and semi-physical real-time simulation system is provided, which uses the clock alignment method for digital and semi-physical real-time simulation described in any of the above embodiments to achieve clock alignment of the hardware model clock signal, the digital model clock signal and the reference clock signal. In the digital and semi-physical real-time simulation system, the hardware model can achieve clock alignment with the digital model, and the internal simulation engine is driven to perform simulation deduction by using the reference clock signal generated by an external device. This invention improves the time accuracy of the digital and semi-physical real-time simulation parallel test system, thereby ensuring the precise synchronization between the virtual and real between the digital simulation and the semi-physical hardware devices.

[0066] Reference Figure 2 , a framework diagram of a digital and semi-physical real-time simulation system provided by an embodiment, the system can achieve system clock synchronization and enhance the reliability and stability of the system under the premise of ensuring the stable operation of the simulation system. Specifically, the digital and semi-physical real-time simulation system includes a digital simulation unit and a real-time simulation control device. The digital simulation unit mainly completes the access to the reference clock signal, manages the device simulation model parameters, allocates the device simulation model parameters, and manages the started device simulation model parameters and device clock parameters. The digital simulation unit includes a basic clock access unit, a hardware model simulation management unit, a model time alignment management unit, and a digital model and hardware model engine unit. As a semi-physical real-time simulation parallel test system, the real-time simulation control device mainly completes the functions of reference clock signal generation, model startup, model management, etc., performs real-time simulation of the hardware system, and interacts with the mathematical simulation unit. The real-time simulation control device includes a hardware clock generator unit, a model management unit, and a model startup unit:

[0067] The hardware clock generator unit generates a reference clock signal and outputs it to the hardware model startup unit and the basic clock access unit in the digital simulation unit;

[0068] A basic clock access unit receives a reference clock signal and outputs it to a hardware model simulation management unit;

[0069] The hardware model simulation management unit is responsible for managing the hardware models of the real-time devices that need to be added, loading the hardware models into the simulation environment, realizing the clock alignment between the hardware models, ensuring the consistency of the hardware model clock signals between the hardware models, monitoring the running status of the hardware models, processing the communication and interaction between the hardware models and the simulation environment, and passing the reference clock signal and the hardware model clock signal to the model time alignment management unit;

[0070] The model time alignment management unit realizes the alignment of the hardware model clock signal with the reference clock signal, and the alignment of the digital model clock signal with the reference clock signal;

[0071] The digital model and hardware model engine unit realizes the conversion logic process of the hardware model and the digital model in the parallel experiment. After the conversion logic is completed, the digital model and hardware model engine unit will execute the simulation process to ensure that the digital model and the hardware model can interact and collaborate correctly after the conversion;

[0072] The model management unit is responsible for managing the hardware resource data required for model simulation. When the hardware model simulation management unit has added the hardware model parameters of the real-time device, the hardware model simulation management unit outputs the registered simulation model to the model management unit, and the hardware model parameters of the real-time device added by the model management unit are input to the model startup unit;

[0073] The model startup unit outputs the startup model instruction to the model time alignment management unit according to the reference clock signal generated by the hardware clock generator unit, ensuring that the hardware model can be initialized and configured in time according to the established process to achieve normal startup and operation of the system.

[0074] The model time alignment management unit takes the reference clock signal, the hardware model clock signal, and the digital model clock signal as input, and mainly completes the alignment of the hardware model clock signal with the reference clock signal, and the alignment of the digital model clock signal with the reference clock signal. Specifically, according to the reference clock signal and the hardware model clock signal, the hardware model clock signal is synchronized and calibrated, and according to the reference clock signal and the digital model clock signal, the digital model clock signal is synchronized and calibrated, to ensure that the hardware model clock signal and the reference clock signal are consistent during the simulation process of the hardware model, and to ensure that the digital model clock signal and the reference clock signal are consistent during the simulation process of the digital model. This can be achieved by adjusting the model's clock frequency, delay and other parameters, and can be achieved by using the alignment method of the hardware model clock signal and the reference clock signal provided in any of the above embodiments, and the alignment method of the digital model clock signal and the reference clock signal, which will not be repeated here.

[0075] Furthermore, during the model operation, the model time alignment management unit monitors the model status and output data in real time and associates these data with the simulation time so that the model output can be mapped to the actual time axis when necessary. This helps to analyze and verify the model behavior during the simulation process.

[0076] The clock alignment method for digital and semi-physical real-time simulation proposed in the present invention realizes the clock alignment of the hardware model clock signal, the digital model clock signal and the reference clock signal, which can ensure that they are coordinated according to the correct time step during the simulation process and ensure that the communication and interaction between different models can be carried out at the correct time point.

[0077] The digital model and hardware model engine unit will load the digital model and hardware model that need to be converted. It will implement the conversion logic process of the hardware model and the digital model in the parallel test. Specifically, it will adapt and convert the interface and data format between the digital model and the hardware model according to the pre-defined conversion logic, which mainly includes the following steps:

[0078] a. Define conversion rules: According to the differences and requirements between the digital model and the hardware model, formulate conversion rules, including conversion rules in signal format, interface protocol, etc.

[0079] b. Data analysis: Receive the digital model and hardware model data processed by the model time alignment management unit, analyze the data, and understand the structure, meaning, and format of the data.

[0080] c. Signal format conversion: According to the defined conversion rules, the signal format between the digital model and the hardware model is converted to ensure that the data can be correctly transmitted and interpreted.

[0081] d. Interface protocol conversion: If the digital model and the hardware model use different interface protocols, the conversion logic unit will convert the interface protocols according to the conversion rules to ensure that data is correctly transmitted and parsed between different interfaces.

[0082] e. Data adaptation: Adapt and adjust data to ensure compatibility and consistency between different models. This may involve operations such as adjusting data formats and converting units.

[0083] f. Error handling: handle possible data conversion errors or mismatches, such as data loss, data parsing errors, etc., to ensure that the converted data is accurate.

[0084] g. Output the converted data: The conversion logic unit outputs the converted digital model data and hardware model data so that the digital model and hardware model engine units can perform further simulation calculations and processing.

[0085] Once the conversion logic is completed, the digital model and hardware model engine unit will perform the simulation process to ensure that the digital model and the hardware model can interact and collaborate correctly after the conversion.

[0086] Through the above steps, the digital model and hardware model engine unit can realize the conversion of the device simulation model into a digital model or a hardware model, thereby realizing the conversion logic process of the device simulation model to the digital model in the parallel test.

[0087] The hardware clock generator unit in the real-time simulation control device generates a stable reference clock signal through a clock generator, and then performs clock signal control to ensure that it can operate according to the synchronized clock signal during the simulation process, thereby realizing the clock alignment process.

[0088] Reference Figure 3 , is a schematic diagram of the structure of a hardware clock generator unit in an embodiment, comprising:

[0089] The clock source generator is responsible for generating a basic clock signal. In the present invention, a crystal oscillator generates a stable frequency signal as the output of the clock source generator.

[0090] The offset analog unit is used to adjust the frequency or phase of the basic clock signal to generate the required time signal. It mainly controls the signal to make small frequency or phase adjustments to the clock signal, thereby achieving precise control of the time signal.

[0091] Clock signal control unit: responsible for managing and controlling the operation of the entire time generation unit, generating an accurate reference clock signal. First, multiple receiving timestamps are generated for the received time samples, multiple receiving timestamps are aligned based on the first receiving timestamp, and the generated multiple receiving timestamp signals are output to the model startup unit and the basic clock access unit.

[0092] Taking the second timestamp as an example, since it is a timestamp used to receive the second data block based on the alignment of the first receiving timestamp, it can ensure that the time information remains consistent after reaching the clock signal control unit between multiple data, and no skew occurs. When the reference clock signal is output to the basic clock access unit or the model startup unit, a clock synchronization message is generated based on the information of multiple data blocks, and the timestamp is written into the clock synchronization message. In this way, the clock information of each model data is synchronized and consistent.

[0093] In summary, the present invention achieves accurate synchronization of digital and semi-physical simulation models, and has certain application potential in other fields, including aerospace, automotive engineering, communication systems, etc. It is expected to provide a more reliable time synchronization mechanism for the integration of digital simulation systems and semi-physical hardware devices, thereby promoting technological development and innovation in related fields.

[0094] The implementation methods of the above modules and the construction of the model can adopt the methods described in any of the above embodiments, which will not be repeated here.

[0095] On the other hand, the present invention provides a computer device, including a memory and a processor, the memory storing a computer program, and the processor implementing the steps of the clock alignment method for digital and semi-physical real-time simulation provided in any of the above embodiments when executing the computer program. The computer device can be a server. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store sample data. The network interface of the computer device is used to communicate with an external terminal through a network connection.

[0096] On the other hand, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the clock alignment method for digital and semi-physical real-time simulation provided in any of the above embodiments.

[0097] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0098] Matters not covered by the present invention are known technologies.

[0099] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A clock alignment method for digital and semi-physical real-time simulation, characterized in that: include: generating a reference clock signal; By detecting the phase relationship between the hardware model clock signal and the reference clock signal, judging whether the hardware model clock signal is aligned with the reference clock signal based on the phase relationship between the hardware model clock signal and the reference clock signal, if the hardware model clock signal and the reference clock signal are not aligned, adjusting the hardware model clock signal so that the hardware model clock signal is aligned with the reference clock signal; By detecting the phase relationship between the digital model clock signal and the reference clock signal, it is determined whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal. If the digital model clock signal and the reference clock signal are not aligned, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal.

2. The clock alignment method for digital and semi-physical real-time simulation according to claim 1, characterized in that: A reference clock signal is generated by using a crystal oscillator, wherein the crystal oscillator includes a crystal resonator and a feedback loop, wherein a controller is provided in the feedback loop, and an electric field or mechanical stress is applied to the crystal resonator, and the crystal resonator vibrates at its natural frequency and outputs a signal, and a part of the output signal is input into the feedback loop, and the controller in the feedback loop generates an electric field or mechanical stress control signal applied to the crystal resonator according to the output signal, thereby enhancing the oscillation of the crystal, forming a closed-loop oscillation, and causing the crystal oscillator to output an oscillation signal of a predetermined frequency as a reference clock signal.

3. The clock alignment method for digital and semi-physical real-time simulation according to claim 1 or 2, characterized in that: If the hardware model clock signal is not aligned with the reference clock signal, the hardware model clock signal is adjusted so that the hardware model clock signal is aligned with the reference clock signal, the method comprising: Generate a corresponding error signal according to the phase difference between the hardware model clock signal and the reference clock signal, so as to characterize the phase difference between the hardware model clock signal and the reference clock signal; Performing low-pass filtering on the error signal to obtain a corresponding control voltage signal; The hardware model clock signal is adjusted based on the control voltage signal so that the hardware model clock signal is aligned with the reference clock signal.

4. The clock alignment method for digital and semi-physical real-time simulation according to claim 3, characterized in that: If the digital model clock signal is not aligned with the reference clock signal, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal, the method comprising: inputting a reference clock signal and a digital control word into a digital frequency synthesizer; A digital model clock signal is generated by a digital frequency synthesizer, wherein the digital frequency synthesizer adjusts the frequency of the digital model clock signal according to the digital control word so that the generated digital model clock signal is aligned with the reference clock signal.

5. The clock alignment method for digital and semi-physical real-time simulation according to claim 1, 2 or 4, characterized in that: Detecting a phase relationship between a hardware model clock signal and a reference clock signal, and determining whether the hardware model clock signal is aligned with the reference clock signal based on the phase relationship between the hardware model clock signal and the reference clock signal, the method comprising: Capture the rising edge or falling edge of the hardware model clock signal and the reference clock signal respectively; When the rising edge or falling edge of the hardware model clock signal or the reference clock signal is detected, an interrupt is triggered and the corresponding timestamp is recorded; Calculate the time difference between the hardware model clock signal and the reference clock signal according to the timestamp corresponding to the interrupt triggered by the hardware model clock signal and the timestamp corresponding to the interrupt triggered by the reference clock signal; The phase difference between the hardware model clock signal and the reference clock signal is characterized based on the time difference. When the time difference is less than a set threshold, the hardware model clock signal is aligned with the reference clock signal. When the time difference is greater than or equal to the set threshold, the hardware model clock signal is not aligned with the reference clock signal.

6. The clock alignment method for digital and semi-physical real-time simulation according to claim 5, characterized in that: By detecting the phase relationship between the digital model clock signal and the reference clock signal, judging whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal, the method includes: Capturing the rising edge or falling edge of the digital model clock signal and the reference clock signal respectively; When the rising edge or falling edge of the digital model clock signal or the reference clock signal is detected, an interrupt is triggered and the corresponding timestamp is recorded respectively; Calculate the time difference between the digital model clock signal and the reference clock signal according to the timestamp corresponding to the interrupt triggered by the digital model clock signal and the timestamp corresponding to the interrupt triggered by the reference clock signal; The phase difference between the digital model clock signal and the reference clock signal is characterized based on the time difference. When the time difference is less than a set threshold, the digital model clock signal is aligned with the reference clock signal. When the time difference is greater than or equal to the set threshold, the digital model clock signal is not aligned with the reference clock signal.

7. The clock alignment method for digital and semi-physical real-time simulation according to claim 1, 2, 4 or 6, characterized in that: It also includes simultaneously monitoring the phase relationship between the hardware model clock signal, the digital model clock signal and the reference clock signal. When the phase differences between the monitored hardware model clock signal, the digital model clock signal and the reference clock signal are close to zero, the hardware model clock signal, the digital model clock signal and the reference clock signal are all aligned.

8. A clock alignment device for digital and semi-physical real-time simulation, characterized in that: include: A reference clock signal generating module, used for generating a reference clock signal; A hardware model clock signal and reference clock signal alignment module, used to detect the phase relationship between the hardware model clock signal and the reference clock signal, and determine whether the hardware model clock signal is aligned with the reference clock signal based on the phase relationship between the hardware model clock signal and the reference clock signal. If the hardware model clock signal and the reference clock signal are not aligned, the hardware model clock signal is adjusted so that the hardware model clock signal is aligned with the reference clock signal. The digital model clock signal and the reference clock signal alignment module is used to detect the phase relationship between the digital model clock signal and the reference clock signal, and determine whether the digital model clock signal is aligned with the reference clock signal based on the phase relationship between the digital model clock signal and the reference clock signal. If the digital model clock signal and the reference clock signal are not aligned, the digital model clock signal is adjusted so that the digital model clock signal is aligned with the reference clock signal.

9. Digital and semi-physical real-time simulation system, characterized by: The clock alignment method for digital and semi-physical real-time simulation as claimed in claim 1 is used to realize the clock alignment of the hardware model clock signal, the digital model clock signal and the reference clock signal.

10. The digital and semi-physical real-time simulation system according to claim 9, characterized in that: It includes a digital simulation unit and a real-time simulation control device, wherein the digital simulation unit includes a basic clock access unit, a hardware model simulation management unit, a model time alignment management unit and a digital model and hardware model engine unit, and the real-time simulation control device includes a hardware clock generator unit, a model management unit and a model startup unit; The hardware clock generator unit generates a reference clock signal and outputs it to the hardware model startup unit and the basic clock access unit in the digital simulation unit; A basic clock access unit receives a reference clock signal and outputs it to a hardware model simulation management unit; The hardware model simulation management unit is responsible for managing the hardware models of the real-time devices that need to be added, loading the hardware models into the simulation environment, realizing the clock alignment between the hardware models, ensuring the consistency of the hardware model clock signals between the hardware models, monitoring the running status of the hardware models, processing the communication and interaction between the hardware models and the simulation environment, and passing the reference clock signal and the hardware model clock signal to the model time alignment management unit; The model time alignment management unit realizes the alignment of the hardware model clock signal with the reference clock signal, and the alignment of the digital model clock signal with the reference clock signal; The digital model and hardware model engine unit realizes the conversion logic process of the hardware model and the digital model in the parallel experiment. After the conversion logic is completed, the digital model and hardware model engine unit will execute the simulation process to ensure that the digital model and the hardware model can interact and collaborate correctly after the conversion; The model management unit is responsible for managing the hardware resource data required for model simulation. When the hardware model simulation management unit has added the hardware model parameters of the real-time device, the hardware model simulation management unit outputs the registered simulation model to the model management unit, and the hardware model parameters of the real-time device added by the model management unit are input to the model startup unit; The model startup unit outputs the startup model instruction to the model time alignment management unit according to the reference clock signal generated by the hardware clock generator unit, ensuring that the hardware model can be initialized and configured in time according to the established process to achieve normal startup and operation of the system.

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