Homologous clock system, communication link establishment method, equipment, device and medium

Abstract

The invention discloses a homologous clock system, a communication link establishment method, equipment, a device and a medium, and relates to the technical field of communication. A first clock interface and a second clock interface are respectively used for clock reference of link training of a switch and a communication protocol, so that the switch and equipment respectively correspond to different clocks, and clock signals of the first clock interface, the second clock interface and a third clock interface are the same. Therefore, the homologous clock function of the first controller, the switch and the back-end equipment is realized. And the second controller adopts the same time sequence setting, controls the switch to load the configuration information corresponding to the second controller, and ensures that the switch has longer time to load firmware and the configuration information through the de-reset signal with the preset delay time, thereby further ensuring that a communication link is normally established, and improving the communication efficiency. The time sequence control process performed by different first controllers does not need to be distinguished and corresponds to the hardware pull-up and pull-down setting of the board card, the dependency is reduced, and the hardware operation process of the board card is simplified.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a homologous clock system, a method for establishing a communication link, equipment, a device and a medium. Background Art

[0002] Peripheral Component Interconnect Express (PCIE) switches play a vital role in PCIE systems, allowing multiple devices to share a PCIE link. For the same switch under different types of CPUs, the link training time for establishing a connection between PCIE links is different, which corresponds to non-homologous clocks.

[0003] In order to be compatible with different types of central processing units to achieve the same source clock, it is necessary to distinguish the types of central processing units through the connection position of the motherboard connector, so as to control different timings to achieve the same source clock function. This leads to the dependence on the hardware pull-up and pull-down settings of the board during the timing control process, making the PCIE configuration process cumbersome, and further reducing the bandwidth between the central processing unit and the switch due to different hardware pull-up and pull-down settings.

[0004] Therefore, how to make different types of central processing units compatible and realize the same source clock to simplify the hardware operation process of the board and improve the transmission bandwidth is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a homologous clock system, a method, device, apparatus and medium for establishing a communication link, so as to solve the problem of cumbersome configuration process caused by the strong dependence of different types of controllers on hardware boards in realizing the timing control of the homologous clock.

[0006] In order to solve the above technical problems, the present invention provides a homologous clock system, comprising a first controller, a second controller, a clock buffer and a switch;

[0007] The first controller is connected to the clock buffer; the clock buffer is connected to the switch through the first clock interface and the second clock interface; the clock buffer is connected to the port device through the third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are used as clock references for link training of the switch and the communication protocol respectively;

[0008] The first controller is connected to the second controller via a reset interface and a reset release interface; the second controller is connected to the switch and the port device;

[0009] The second controller is used to receive the enable signal of the clock signal, control the reset interface to send the reset signal to the switch through a preset delay time, and synchronously output the second reset signal to the switch and the port device after receiving the first reset signal sent by the first controller to complete the establishment of the communication link.

[0010] In one aspect, it also includes a first connector and a second connector;

[0011] The first controller and the switch are connected through the first connector and the second connector; wherein the first communication port and the second communication port of the switch connected to the first connector and the second connector respectively support a single uplink or dual uplink mode transmission mode.

[0012] On the other hand, the first controller and the second controller are also connected via a first communication protocol interface;

[0013] The first controller is used to send a first communication protocol command to modify the configuration information corresponding to the second controller so as to modify the type of the first controller.

[0014] On the other hand, the configuration information of the second controller is stored in the non-volatile memory; the second controller and the switch are also connected via a startup configuration interface; wherein the level signal corresponding to the startup configuration interface is used to represent the configuration information of the second controller.

[0015] On the other hand, a mapping relationship is pre-established between the level signal corresponding to the startup configuration interface, the configuration information of the second controller, and the transmission mode supported by the communication port of the switch;

[0016] The specific mapping relationship includes at least one of the following relationship modes:

[0017] Mode 1: Establishing a mapping relationship between a first level signal corresponding to the startup configuration interface, first configuration information of the second controller, and a first transmission mode supported by the communication port; wherein the first transmission mode supports a dual uplink mode, and the first communication port and the second communication port serve as upstream ports;

[0018] Mode 2: A mapping relationship is established between a second level signal corresponding to the startup configuration interface, second configuration information of the second controller, and a second transmission mode supported by the communication port; wherein the second transmission mode supports a single uplink mode; the first communication port is used as an upstream port, and the remaining ports except the first communication port are used as downstream ports, and the port devices are connected;

[0019] Mode 3: A mapping relationship is established between a third level signal corresponding to the startup configuration interface, third configuration information of the second controller, and a third transmission mode supported by the communication port; wherein the third transmission mode supports a single uplink mode; the second communication port is used as an upstream port, and the remaining ports except the second communication port are used as downstream ports, and the port device is connected;

[0020] Mode 4: Establishing a mapping relationship between a fourth level signal corresponding to the startup configuration interface, fourth configuration information of the second controller, and a fourth transmission mode supported by the communication port; wherein the fourth transmission mode supports a single uplink mode; the third communication port serves as an upstream port, and the remaining ports except the third communication port serve as downstream ports;

[0021] Mode 5: Establishing a mapping relationship between the fifth level signal corresponding to the startup configuration interface, the fifth configuration information of the second controller, and the fifth transmission mode supported by the communication port; wherein the fifth transmission mode supports a dual uplink mode; the first communication port and the second communication port serve as upstream ports, and the first communication port and the third communication port are located in the same virtual switch;

[0022] Method six: Establish a mapping relationship between the sixth level signal corresponding to the startup configuration interface, the sixth configuration information of the second controller, and the sixth transmission mode supported by the communication port; wherein the sixth transmission mode supports a dual uplink mode; the first communication port and the second communication port serve as upstream ports, and the first communication port and the second communication port are located in the same virtual switch.

[0023] On the other hand, the signal type corresponding to the level signal of the startup configuration interface and the number of the startup configuration interfaces are determined by the number of configuration information of the second controller.

[0024] In order to solve the above technical problems, the present invention also provides a method for establishing a communication link, which is applied to a homologous clock system, comprising a first controller, a second controller, a clock buffer and a switch; the first controller is connected to the clock buffer; the clock buffer is connected to the switch through a first clock interface and a second clock interface; the clock buffer is connected to the port device through a third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used as clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller through a reset interface and a reset interface; the second controller is connected to the switch and the port device; the method comprises:

[0025] An enable signal for receiving a clock signal;

[0026] Control the reset interface to send a reset signal to the switch through a preset delay time;

[0027] After receiving the first reset signal sent by the first controller, a second reset signal is synchronously output to the switch and the port device to complete the establishment of the communication link.

[0028] In order to solve the above technical problems, the present invention also provides a communication link establishment device, which is applied to a homologous clock system, including a first controller, a second controller, a clock buffer and a switch; the first controller is connected to the clock buffer; the clock buffer is connected to the switch through a first clock interface and a second clock interface; the clock buffer is connected to the port device through a third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used as clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller through a reset interface and a reset interface; the second controller is connected to the switch and the port device; the device includes:

[0029] A receiving module, used for receiving an enable signal of a clock signal;

[0030] A control module, used for controlling the reset interface to send a reset signal to the switch through a preset delay time;

[0031] The output module is used to receive the first reset signal sent by the first controller and then synchronously output the second reset signal to the switch and the port device to complete the establishment of the communication link.

[0032] In order to solve the above technical problems, the present invention also provides a communication link establishment device, comprising:

[0033] Memory for storing computer programs;

[0034] A processor is used to implement the steps of the method for establishing a communication link as described above when executing the computer program.

[0035] In order to solve the above technical problem, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for establishing a communication link as described above are implemented.

[0036] The present invention provides a homologous clock system, wherein a first controller is connected to a clock buffer; the clock buffer is connected to a switch via a first clock interface and a second clock interface; the clock buffer is connected to a port device via a third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used as clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller; the first controller is connected to the switch via a reset interface and a de-reset interface; the second controller is connected to the port device; the second controller is used to receive an enable signal of the clock signal, control the de-reset interface to send a de-reset signal to the switch through a preset delay time, and synchronously output a second reset signal to the switch and the port device after receiving a first reset signal sent by the first controller, so as to complete the establishment of a communication link.

[0037] The beneficial effect of the present invention is that the first clock interface and the second clock interface are respectively used as the clock reference for the link training of the switch and the communication protocol, so that the switch and the device correspond to different clocks respectively, and the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, thereby realizing the homologous clock function of the first controller, the switch and the back-end device. Under the homologous clock function, the second controller adopts the same timing setting, and there is no need to distinguish the type of the first controller, such as the type of the central processing unit, to control the switch to load the configuration information corresponding to the second controller, and through the reset signal with a preset delay time, to ensure that the switch has a longer time to load the firmware and configuration information, further ensure that the communication link is established normally, and there is no need to distinguish the timing control process performed by different first controllers corresponding to the hardware pull-up and pull-down settings of the board, reduce dependence, and simplify the hardware operation process of the board. At the same time, in the homologous clock mode, the same timing setting is adopted to establish a normal connection of the communication link, avoiding the problem of bandwidth reduction and speed reduction.

[0038] Secondly, the uplink mode (single uplink mode or dual uplink mode) describes the direction of data transmission, fixes the data transmission mode, and implements the PCIE topology to switch, so as to realize data transmission while the switch is modularly designed. The storage configuration information of the UFM area of ​​the second controller is modified through the first communication protocol interface to realize the replacement of the hardware PCIE topology. For the PCIE topology composed of different configuration information and PCIE communication ports, there is no need to set the pull-up and pull-down of the hardware device, but through the configuration information stored in the UFM area, the switch loads different configuration information and adopts a unified method to realize the topology switching of the switch, that is, there is no need to distinguish between different platform types of first controllers to adapt to different server systems. In order to meet the different platform types of the first controller stored, it is necessary to control the startup configuration interface of the switch to avoid the cumbersome operation of hardware settings using the hardware pull-up and pull-down method, and simplify the operation process.

[0039] In addition, the present invention also provides a method, device, apparatus and medium for establishing a communication link, which has the same beneficial effects as the above-mentioned homologous clock system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 It is a schematic diagram of the structure of a conventional homologous clock system;

[0042] Figure 2 A schematic diagram of the structure of a homologous clock system provided by an embodiment of the present invention;

[0043] Figure 3 A flow chart of a method for establishing a communication link provided by an embodiment of the present invention;

[0044] Figure 4 A structural diagram of a communication link establishment device provided by an embodiment of the present invention;

[0045] Figure 5 A structural diagram of a device for establishing a communication link provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The core of the present invention is to provide a homologous clock system, a method, equipment, device and medium for establishing a communication link to solve the problem of cumbersome configuration process caused by the strong dependence of different types of controllers on hardware boards when implementing the timing control of the homologous clock.

[0048] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0049] The number of PCIE input and output (IO) ports of different processors is increasing, but it still cannot meet the needs of actual business corresponding to PCIE interfaces. For example, the application scenario of artificial intelligence (AI) server requires more PCIE IO ports for expansion of graphics processing unit (GPU), high-speed network interface (IB) card and non-volatile memory host controller interface (NVME) disk. At this time, PCIE Switch is particularly important. PCIE Switch is widely used to extend PCIE signals in servers, so that server systems can support more PCIE devices and are no longer limited by the number of PCIE IO ports of CPU.

[0050] In a server where the PCIE Switch extends the CPU PCIE IO port, in order to implement hardware modular design and ensure hardware reusability and stability, the server is generally divided into a motherboard, a PCIE Switch board, and a PCIE IO board. The PCIE signal is sent from the motherboard CPU, and after being extended by the PCIE Switch on the Switch board, it reaches PCIE devices such as GPU\Network Interface Card (NIC)\NVMe disks and other devices. The CPU can communicate with the PCIE device, and the devices under the PCIE Switch can also communicate peer to peer. The clock of the PCIE device can support homologous clocks and non-homologous clocks. Generally, the PCIE homologous clock solution makes the PCIE link more stable. However, different types of processors have non-homologous clocks in the same Switch. In order to achieve homologous clocks, Figure 1 This is a schematic diagram of the structure of a conventional homologous clock system, such as Figure 1 As shown, the switch board connects different positions on the connector through the hardware identifier (HW_ID0 / 1 / 2) signal to distinguish the hardware topology of the PCIE Switch. Figure 1 In the MCU, only two signals, HW_ID0 and HW_ID1, are used to connect the corresponding connector positions of the central processor. In the complex programmable logic device (CPLD), information interaction is carried out through the boot configuration interface (Boot_Strap0 and Boot_Strap1) signals. The clock signal of 100M clock is connected from the host side, passes through the 100M clockbuffer on the PCIE Switch board, and outputs 100M clock to connect the SYS_REF_CLK (system reference clock signal) of the Switch and the PCIE Slot (slot) connected to the PCIE device; the MB_TYPE signal (macroblock type signal) is used to distinguish the CPUs of different platform types on the motherboard side. When the CPU of the first platform type is connected, the CPLD first controls the power-on of the Switch board. Then, when the CPLD receives the RESET_PERST_N (reset release signal) sent by the host, the CPLD outputs RST_SW_1_N (reset signal controlled by the switch) to the SYS_PWR_ON_RST_N (system power on reset signal) pin of the PCIE Switch to control the PCIESwitch to load the firmware (Firmware, FW), and then initialize the PCIE link.

[0051] When the MB_TYPE signal is used to determine that the CPU on the motherboard is of the second platform type, the CPLD first controls the power-on of the Switch board, and then the CPLD delays for 2s to control the high RST_SW_1_N signal, because it takes time for the Switch FW to load. If the CPLD waits until the CPU of the second platform type sends PERST_N, and then pulls up the Switch's SYS_PWR_ON_RST_N, there will be a bandwidth reduction problem between the CPU and the PCIE Switch. Therefore, for CPUs of different platform types on the PCIE Switch board, it is necessary to first distinguish them through the MB_TYPE signal, and then the CPLD performs different logics to achieve the same source clock function before establishing the PCIE link. However, the CPLE on the PCIE Switch requires the GPIO HW_ID0 / 1 pins on the connector to connect to different locations to distinguish different PCIE topologies. Use MB_TYPE to distinguish the platform type of the CPU, control different timings, and delay the corresponding time to achieve the same source clock. Figure 1 Conventional homologous clock systems rely heavily on the hardware pull-up and pull-down settings of interconnected boards, and cannot achieve hardware module consistency settings, nor can they achieve compatibility with processors of different platform types. Therefore, the homologous clock system provided by the present invention can solve the above technical problems.

[0052] Figure 2 A schematic diagram of the structure of a homologous clock system provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, it includes a first controller 1, a second controller 2, a clock buffer 3 and a switch 4;

[0053] The first controller 1 is connected to the clock buffer 3; the clock buffer 3 is connected to the switch 4 through the first clock interface and the second clock interface; the clock buffer 3 is connected to the port device 5 through the third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are used as clock references for the link training of the switch 4 and the communication protocol respectively;

[0054] The first controller 1 is connected to the second controller 2 via a reset interface and a reset release interface; the second controller 2 is connected to a switch 4 and a port device 5;

[0055] The second controller 2 is used to receive the enable signal of the clock signal, control the reset interface to send the reset signal to the switch 4 through a preset delay time, and synchronously output the second reset signal to the switch 4 and the port device 5 after receiving the first reset signal sent by the first controller 1 to complete the establishment of the communication link.

[0056] Specifically, the number of first controllers is multiple, mainly corresponding to processors, which can be CPUs or other processors, which are not limited here. The type of the second controller is a programmable logic device, which can be a programmable logic device or other controllers, etc., which are not limited here. The programmable logic device is a digital integrated circuit that uses programming to implement specific logic functions. The specific type of device is not limited, and can be a programmable read-only memory, programmable array logic, general array logic, CPLD or field programmable gate array (Field-Programmable GateArray, FPGA), etc., which are not limited here and can be set according to actual conditions.

[0057] A clock buffer is a circuit used to improve the quality and stability of clock signals. Its main functions include clock signal replication, format conversion, and level conversion. The clock buffer can generate multiple clock signals from a clock signal source through frequency replication, and can also adjust the format and level of the clock signal to meet the needs of different electronic systems. The role of the clock buffer is very critical. It can improve the driving ability of the clock signal and reduce signal attenuation, thereby ensuring that the signal can be stably transmitted to various parts of the system. In addition, the clock buffer also has isolation and protection functions, which can prevent noise from interfering with the clock signal and maintain the purity of the clock signal.

[0058] The switch is a key component of the PCIE architecture, which plays the role of connecting and extending multiple PCIE devices. The PCIE switch can be regarded as the counterpart of the network switch in the PCIE bus, allowing multiple devices to communicate through point-to-point connections. These connections are high-speed serial, and each device has its own dedicated connection, so there is no need to share bandwidth with other devices.

[0059] The switch has an upstream port (Upstream Port) connected to the root complex (RC) or the downstream port of other switches, and multiple downstream ports (Downstream Ports), which can be connected to the terminal device (Endpoints) or to the upstream port of another switch. In this way, the PCIE switch can expand the connection capacity of PCIE and support more complex device topology.

[0060] The first controller is connected to the clock buffer. The first controller is located at the host end and is used to send a clock signal to the clock buffer. At this time, the clock buffer is connected to the switch through the first clock interface and the second clock interface. It should be noted that the first clock interface (SYS_REF_CLK signal) in this embodiment is used for the clock reference of the switch, and the second clock interface (S0_PCE_REF_CLK signal) is used for the clock reference of the link training of the communication protocol. All PCIE port Serdes clock references are set in the PCIE Switch SBR. The clock buffer is connected to the port device through the third clock interface, and is used to output the clock signal to connect the PCIE slot of the PCIE device. And Figure 1 compared to, Figure 1 The clock signal of the same clock interface is used as the clock signal of the switch and the clock signal of the link communication corresponding to the PCIE device. The present invention uses clock signals of different clock interfaces as the clock signal of the switch and the clock signal of the link communication corresponding to the PCIE device respectively, and the clock signals corresponding to the first clock interface, the second clock interface and the third clock interface are the same. The main board sends a 100Mclock homologous clock to the 100M clock buffer of the PCIE Switch exchange board, and the clock buffer outputs 100Mclock to connect the SYS_REF_CLK (first clock interface) and S0_PCE_REF_CLK (second clock interface) of the Switch chip. The PCIE Switch SBR sets all PCIE port Serdes clock reference S0_PCE_PERST_N (PCIE device reset signal when the system power is turned on), which is the same as the clock signal of the second clock interface. In addition, the clock buffer outputs 100M clock to connect the PCIE Slot of the PCIE device, so as to realize the homologous clock design of the CPU, PCIE Switch and back-end devices.

[0061] It should be noted that in this embodiment, the clock signal is set to be the same, which unifies the homologous clock settings of the first controller, switch and back-end device, and uses the same timing during the subsequent PCIE link initialization, without the need for different timing control for the first controllers of different platform types.

[0062] When the server starts, the second controller controls the switch to power on, and the clock buffer sends out an enable signal of 100M clock to control the output of the 100M clock clock signal to the first clock interface and the second clock interface of the switch. When the second controller receives the 100M clock signal sent after the switch is powered on, it controls the reset signal (RST_PWR_ON_RST_N) of the reset interface to the switch through a preset delay time to ensure that the switch loads the firmware and the preliminary configuration work, thereby ensuring that the switch has enough time to load the firmware and configuration information, and can work normally before link training.

[0063] After receiving the first reset signal (RST_HOST_PERST_N signal) sent by the mainboard (first controller), the second reset signal (RST_PERST_N) is synchronously output to the switch and the back-end Duanou device to establish subsequent communication links. The communication links can simultaneously enter the initialization state of link training, so that the PCIE link can establish a connection normally, avoiding the asynchrony of the reset process and the link bandwidth reduction and speed reduction problem.

[0064] This embodiment and Figure 1 The difference is that when the firmware is loaded, sufficient time (preset delay time) is required for de-resetting to avoid clock asynchrony during de-resetting and to separate it from the time of PCIE link initialization. Figure 1 When receiving the RESET_PERST_N signal sent by the host during the normal configuration process, the CPLD outputs the RST_SW_1_N signal to the SYS_PWR_ON_RST_N pin of the PCIE Switch to control the PCIE Switch to load the firmware. In this embodiment, after the reset is completed and the first reset signal sent by the host is received, the second reset signal (RESET_PERST_N) is output to separate the firmware loading and initialization.

[0065] The embodiment of the present invention provides a homologous clock system, wherein a first controller is connected to a clock buffer; the clock buffer is connected to a switch through a first clock interface and a second clock interface; the clock buffer is connected to a port device through a third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used as clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller; the first controller is connected to the switch through a reset interface and a de-reset interface; the second controller is connected to the port device; the second controller is used to receive an enable signal of the clock signal, control the de-reset interface to send a de-reset signal to the switch through a preset delay time, and synchronously output a second reset signal to the switch and the port device after receiving the first reset signal sent by the first controller, so as to complete the establishment of the communication link. By setting the first clock interface and the second clock interface as the clock references for link training of the switch and the communication protocol, respectively, the switch and the device correspond to different clocks, and the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, thereby realizing the homologous clock function of the first controller, the switch and the back-end device. Under the same source clock function, the second controller uses the same timing settings, and there is no need to distinguish the type of the first controller, such as the type of the central processing unit. The control switch loads the configuration information corresponding to the second controller, and the reset signal with a preset delay time is used to ensure that the switch has a longer time to load the firmware and configuration information, further ensuring that the communication link is established normally, without distinguishing the timing control process performed by different first controllers corresponding to the hardware pull-up and pull-down settings of the board, reducing dependence and simplifying the hardware operation process of the board. At the same time, in the same source clock mode, the same timing settings are used to establish a normal connection of the communication link to avoid bandwidth reduction and speed reduction problems.

[0066] In some embodiments, further comprising a first connector and a second connector;

[0067] The first controller and the switch are connected through the first connector and the second connector; wherein the first communication port and the second communication port of the switch connected to the first connector and the second connector respectively support a single uplink or dual uplink mode transmission mode.

[0068] like Figure 2As shown, it also includes a first connector (CONN1) and a second connector (CONN2), and the first controller and the switch are connected through the first connector and the second connector, and the first communication port and the second communication port of the corresponding switch support single uplink or dual uplink mode transmission. The single uplink mode is that one of the devices is connected to the root complex (RC) or switch (Switch) through a single uplink. This configuration is usually lower in cost and complexity than the dual uplink topology, but there is no redundancy in the event of a link failure. The dual uplink mode is that a device is connected to two different root complexes (RC) or switches (Switch) through two independent uplinks. This configuration can provide redundancy in case one link fails, and can also be used for load balancing to increase throughput. For example, in a server environment, dual uplinks allow the server to transmit data between two different PCIE switches to optimize performance and reliability.

[0069] The uplink mode (single uplink mode or dual uplink mode) in this embodiment describes the direction of data transmission, fixes the data transmission mode, and switches when the PCIE topology is implemented, so as to realize data transmission while the switch is modularly designed.

[0070] In some embodiments, the first controller and the second controller are further connected via a first communication protocol interface;

[0071] The first controller is used to send a first communication protocol command to modify the configuration information corresponding to the second controller so as to modify the type of the first controller.

[0072] It can be understood that the first communication protocol interface in this embodiment can be an Inter-Integrated Circuit (I2C) bus, or a PCIE bus, or other buses, which are not limited here and can be set according to actual conditions. The first communication protocol interface is convenient for the first controller to send a first communication protocol command to modify the configuration information corresponding to the second controller, thereby modifying the type of the first controller. The configuration information of the second controller here, such as config information, modifies the user-available Flash storage area (UserFlash Memory, UFM) area of ​​the second controller (such as CPLD). Only when the server is produced and tested, the first controller only needs to modify the UFM area of ​​the second controller once, and the subsequent hardware connection remains unchanged, and the server does not need to be modified when it is turned on.

[0073] Since the storage configuration information of the corresponding UFM area is different under different hardware topologies, it is necessary to modify the corresponding storage configuration information through the first communication protocol interface.

[0074] This embodiment provides a method for modifying the storage configuration information of the UFM area of ​​the second controller through the first communication protocol interface, thereby replacing the topology structure of the hardware PCIE.

[0075] In some embodiments, the configuration information of the second controller is stored in a non-volatile memory; the second controller and the switch are also connected via a startup configuration interface; wherein the level signal corresponding to the startup configuration interface is used to represent the configuration information of the second controller.

[0076] Specifically, if the second controller is a CPLD, there is a UFM area that will not be lost in the event of a power failure. It can store the second controllers of different platform types and connect to the boot configuration interface (Boot strap interface) of the corresponding control switch. The switch collects the pin level and loads the config area of ​​the SPI Flash to load the configuration firmware. The PCIE signal connector on the switch is connected to the motherboard or PCIE device slot through a cable to achieve the switching of the PCIE topology.

[0077] In some embodiments, a mapping relationship is pre-established between the level signal corresponding to the startup configuration interface, the configuration information of the second controller, and the transmission mode supported by the communication port of the switch;

[0078] The specific mapping relationship includes at least one of the following relationship modes:

[0079] Mode 1: Establishing a mapping relationship between a first level signal corresponding to the startup configuration interface, first configuration information of the second controller, and a first transmission mode supported by the communication port; wherein the first transmission mode supports a dual uplink mode, and the first communication port and the second communication port serve as upstream ports;

[0080] Mode 2: A mapping relationship is established between the second level signal corresponding to the startup configuration interface, the second configuration information of the second controller, and the second transmission mode supported by the communication port; wherein the second transmission mode supports a single uplink mode; the first communication port is used as an upstream port, and the remaining ports except the first communication port are used as downstream ports, and the port devices are connected;

[0081] Mode 3: A mapping relationship is established between a third level signal corresponding to the startup configuration interface, third configuration information of the second controller, and a third transmission mode supported by the communication port; wherein the third transmission mode supports a single uplink mode; the second communication port serves as an upstream port, and the remaining ports except the second communication port serve as downstream ports, and the port devices are connected;

[0082] Mode 4: Establishing a mapping relationship between a fourth level signal corresponding to the startup configuration interface, fourth configuration information of the second controller, and a fourth transmission mode supported by the communication port; wherein the fourth transmission mode supports a single uplink mode; the third communication port serves as an upstream port, and the remaining ports except the third communication port serve as downstream ports;

[0083] Mode 5: Establishing a mapping relationship between the fifth level signal corresponding to the startup configuration interface, the fifth configuration information of the second controller, and the fifth transmission mode supported by the communication port; wherein the fifth transmission mode supports a dual uplink mode; the first communication port and the second communication port serve as upstream ports, and the first communication port and the third communication port are located in the same virtual switch;

[0084] Method six: Establish a mapping relationship between the sixth level signal corresponding to the startup configuration interface, the sixth configuration information of the second controller, and the sixth transmission mode supported by the communication port; wherein the sixth transmission mode supports dual uplink mode; the first communication port and the second communication port serve as upstream ports, and the first communication port and the second communication port are located in the same virtual switch.

[0085] Specifically, Table 1 is a correspondence table of configuration information stored in the UFM area. As shown in Table 1, the level signals corresponding to the pins of the startup configuration interface of the UFM area of ​​the CPLD constitute the level signals of the actual startup configuration interface. For the above six implementation methods, the first level signal is in the default mode, the identifier of the Config of the PCIE switch is 1, and the corresponding PCIE topology structure, that is, the transmission mode supported by the communication port, establishes a mapping relationship.

[0086] Table 1 UFM area storage configuration information correspondence table

[0087]

[0088] It should be noted that there are multiple communication ports corresponding to the switch in this embodiment, corresponding to different topological structures. The upstream port is usually connected to the core or central node of the network, such as a switch. The downstream port is usually connected to the edge or branch node of the network, such as connected to an end-user device or a peripheral device. In the PCIE bus, the switch has a special port definition. The upstream port is a port connected to the root complex, which is used to receive signals from the root complex or send signals to the root complex. The downstream port is a port connected to other PCIE devices or switches, which is used to expand the PCIE bus and connect more devices.

[0089] Table 2 is a structural table of the configuration information stored in the Flash of the PCIE switch. As shown in Table 2, combined with Table 1, different configs correspond to different address information. At the same time, other configs can also be customized.

[0090] Table 2 Structure of the configuration information stored in the Flash of the PCIE switch

[0091]

[0092] In this embodiment, the PCIE topology structure composed of different configuration information and PCIE communication ports does not need to be set through the pull-up and pull-down settings of the hardware device, but through the configuration information stored in the UFM area, the switch loads different configuration information and adopts a unified method to realize the topology switching of the switch, that is, there is no need to distinguish the first controllers of different platform types to adapt to different server systems.

[0093] In some embodiments, the signal type corresponding to the level signal of the startup configuration interface and the number of the startup configuration interfaces are determined by the number of configuration information of the second controller.

[0094] It can be understood that the signal types of the level signal of the startup configuration interface are divided into 6 categories in combination with the above Table 1, and the corresponding startup configuration interface is implemented based on the three pins under each category. For example, the corresponding three pins use a high and low signal combination to achieve 2 to the power of 3 = 8 combinations, that is, a maximum of 8 categories are represented. The number of configuration information (config information) of the second controller determines the final signal type of the level signal of the startup configuration interface and the number of startup configuration interface settings.

[0095] The number of startup configuration interfaces provided in this embodiment is set to meet the needs of different platform types of the first controller stored. The startup configuration interface of the switch needs to be controlled to avoid the cumbersome operation of hardware setting using the hardware pull-up and pull-down method, thereby simplifying the operation process.

[0096] In some embodiments, the process of determining the preset delay time includes:

[0097] Obtaining the firmware loading time of the switches corresponding to each first controller;

[0098] The firmware loading time of the switches corresponding to each first controller is screened to obtain a maximum firmware loading time as the preset delay time.

[0099] It should be noted that the purpose of the preset delay time in this embodiment is to control the reset RST_PWR_ON_RST_N through the preset delay time. Therefore, it is currently necessary to combine the firmware loading time corresponding to the first controller of different platform types and take the maximum value to ensure the corresponding firmware loading time.

[0100] The preset delay time provided in this embodiment ensures that the PCIE Switch loads FW and pre-configuration work, which ensures that the PCIE Switch chip has enough time to load FW and Config information, and ensures that it can work normally before the PCIE link training.

[0101] Furthermore, the present invention also provides a method for establishing a communication link. Figure 3 A flow chart of a method for establishing a communication link provided by an embodiment of the present invention, such as Figure 3 As shown, it is applied to a homologous clock system, including a first controller, a second controller, a clock buffer and a switch; the first controller is connected to the clock buffer; the clock buffer is connected to the switch through a first clock interface and a second clock interface; the clock buffer is connected to a port device through a third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used as clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller through a reset interface and a reset interface; the second controller is connected to the switch and the port device; the method includes:

[0102] S11: an enable signal for receiving a clock signal;

[0103] S12: Control the reset interface to send a reset signal to the switch through a preset delay time;

[0104] S13: After receiving the first reset signal sent by the first controller, synchronously output a second reset signal to the switch and the port device to complete the establishment of the communication link.

[0105] When the server starts, the switch board and the second controller control the Strap pin level of the PCIE Switch according to the configuration information stored in the UFM area of ​​the second controller, and then the CPLD controls the PCIE Switch to power on, and sends out a 100MClock buffer enable signal (clock signal enable signal) to control the output of 100M clock to the SYS_REF_CLK and S0_PCE_REF_CLK pins of the Switch chip. After the CPLD receives the completion of the PCIE Switch power supply and sends out the 100M Clock enable, it delays 100ms to control the reset RST_PWR_ON_RST_N (reset signal) to ensure that the PCIE Switch loads FW and the previous configuration work. Then the switch board CPLD waits to receive the RST_HOST_PERST_N signal (first reset signal) sent by the mainboard Host, and synchronously outputs RST_PERST_N (second reset signal) to the PCIE Switch and the back-end PCIE Slot / NVME disk and other devices. After that, the PCIE protocol works, and the PCIE links between the CPU and the PCIE Switch, and the PCIE Switch and the back-end devices are initialized and the connection is established normally.

[0106] For an introduction to a method for establishing a communication link provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. The method has the same beneficial effects as the above homologous clock system.

[0107] The above describes in detail the various embodiments corresponding to the method for establishing a communication link. On this basis, the present invention also discloses a communication link establishment device corresponding to the above method. The device is applied to a homologous clock system, including a first controller, a second controller, a clock buffer and a switch; the first controller is connected to the clock buffer; the clock buffer is connected to the switch through a first clock interface and a second clock interface; the clock buffer is connected to the port device through a third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used for clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller through a reset interface and a reset interface; the second controller is connected to the switch and the port device. Figure 4 The structure diagram of a communication link establishment device provided by an embodiment of the present invention. Figure 4 As shown, the communication link establishment device includes:

[0108] A receiving module 11, used for receiving an enable signal of a clock signal;

[0109] A control module 12, configured to control the reset interface to send a reset signal to the switch through a preset delay time;

[0110] The output module 13 is used to receive the first reset signal sent by the first controller and then synchronously output a second reset signal to the switch and the port device to complete the establishment of the communication link.

[0111] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0112] For an introduction to a communication link establishment device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above communication link establishment method.

[0113] Figure 5 A structural diagram of a communication link establishment device provided by an embodiment of the present invention, such as Figure 5 As shown, the device comprises:

[0114] A memory 21, used for storing computer programs;

[0115] The processor 22 is used to implement the steps of the method for establishing a communication link when executing a computer program.

[0116] The communication link establishment device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0117] Among them, the processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 22 can be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 22 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 22 may be integrated with a GPU, which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 22 may also include an AI processor, which is used to process computing operations related to machine learning.

[0118] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the processor 22, it can implement the relevant steps of the method for establishing a communication link disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include, but is not limited to, data involved in the method for establishing a communication link, etc.

[0119] In some embodiments, the communication link establishing device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .

[0120] Those skilled in the art can understand that Figure 5 The structure shown in the figure does not constitute a limitation on the device for establishing a communication link, and may include more or fewer components than those shown in the figure.

[0121] The processor 22 implements the method for establishing a communication link provided in any of the above embodiments by calling instructions stored in the memory 21 .

[0122] For an introduction to a communication link establishment device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above communication link establishment method.

[0123] Furthermore, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by the processor 22, the steps of the method for establishing a communication link as described above are implemented.

[0124] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0125] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above communication link establishment method.

[0126] Furthermore, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned method for establishing a communication link when executed by a processor.

[0127] For an introduction to a computer program product provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. It has the same beneficial effects as the above communication link establishment method.

[0128] The above is a detailed introduction to a homologous clock system, a method for establishing a communication link, a device, an apparatus and a medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

[0129] It should also be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A homologous clock system, characterized in that: comprising a first controller, a second controller, a clock buffer and a switch; The first controller is connected to the clock buffer; the clock buffer is connected to the switch through the first clock interface and the second clock interface; The clock buffer is connected to the port device via a third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are used as clock references for link training of the switch and the communication protocol respectively; The first controller is connected to the second controller via a reset interface and a reset release interface; the second controller is connected to the switch and the port device; The second controller is used to receive the enable signal of the clock signal, control the reset interface to send the reset signal to the switch through a preset delay time, and synchronously output the second reset signal to the switch and the port device after receiving the first reset signal sent by the first controller to complete the establishment of the communication link.

2. The homologous clock system according to claim 1, characterized in that: Also included is a first connector and a second connector; The first controller and the switch are connected through the first connector and the second connector; wherein the first communication port and the second communication port of the switch connected to the first connector and the second connector respectively support a single uplink or dual uplink mode transmission mode.

3. The homologous clock system according to claim 2, characterized in that: The first controller and the second controller are also connected via a first communication protocol interface; The first controller is used to send a first communication protocol command to modify the configuration information corresponding to the second controller so as to modify the type of the first controller.

4. The homologous clock system according to claim 3, characterized in that: The configuration information of the second controller is stored in the non-volatile memory; the second controller and the switch are also connected via a startup configuration interface; wherein the level signal corresponding to the startup configuration interface is used to represent the configuration information of the second controller.

5. The homologous clock system according to claim 4, characterized in that: A mapping relationship is pre-established between the level signal corresponding to the startup configuration interface, the configuration information of the second controller, and the transmission mode supported by the communication port of the switch; The specific mapping relationship includes at least one of the following relationship modes: Mode 1: Establishing a mapping relationship between a first level signal corresponding to the startup configuration interface, first configuration information of the second controller, and a first transmission mode supported by the communication port; wherein the first transmission mode supports a dual uplink mode, and the first communication port and the second communication port serve as upstream ports; Mode 2: A mapping relationship is established between a second level signal corresponding to the startup configuration interface, second configuration information of the second controller, and a second transmission mode supported by the communication port; wherein the second transmission mode supports a single uplink mode; the first communication port is used as an upstream port, and the remaining ports except the first communication port are used as downstream ports, and the port devices are connected; Mode 3: A mapping relationship is established between a third level signal corresponding to the startup configuration interface, third configuration information of the second controller, and a third transmission mode supported by the communication port; wherein the third transmission mode supports a single uplink mode; the second communication port is used as an upstream port, and the remaining ports except the second communication port are used as downstream ports, and the port device is connected; Mode 4: Establishing a mapping relationship between a fourth level signal corresponding to the startup configuration interface, fourth configuration information of the second controller, and a fourth transmission mode supported by the communication port; wherein the fourth transmission mode supports a single uplink mode; the third communication port serves as an upstream port, and the remaining ports except the third communication port serve as downstream ports; Mode 5: Establishing a mapping relationship between the fifth level signal corresponding to the startup configuration interface, the fifth configuration information of the second controller, and the fifth transmission mode supported by the communication port; wherein the fifth transmission mode supports a dual uplink mode; the first communication port and the second communication port serve as upstream ports, and the first communication port and the third communication port are located in the same virtual switch; Method six: Establish a mapping relationship between the sixth level signal corresponding to the startup configuration interface, the sixth configuration information of the second controller, and the sixth transmission mode supported by the communication port; wherein the sixth transmission mode supports a dual uplink mode; the first communication port and the second communication port serve as upstream ports, and the first communication port and the second communication port are located in the same virtual switch.

6. The homologous clock system according to claim 4 or 5, characterized in that: The signal type corresponding to the level signal of the startup configuration interface and the number of the startup configuration interfaces are determined by the number of configuration information of the second controller.

7. A method for establishing a communication link, characterized in that: Applicable to a homologous clock system, comprising a first controller, a second controller, a clock buffer and a switch; the first controller is connected to the clock buffer; the clock buffer is connected to the switch via a first clock interface and a second clock interface; The clock buffer is connected to the port device through the third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used as clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller through the reset interface and the reset interface; the second controllers are connected to the switch and the port device; the method comprises: An enable signal for receiving a clock signal; Control the reset interface to send a reset signal to the switch through a preset delay time; After receiving the first reset signal sent by the first controller, a second reset signal is synchronously output to the switch and the port device to complete the establishment of the communication link.

8. A communication link establishment device, characterized in that: Applicable to a homologous clock system, comprising a first controller, a second controller, a clock buffer and a switch; the first controller is connected to the clock buffer; the clock buffer is connected to the switch via a first clock interface and a second clock interface; The clock buffer is connected to the port device through the third clock interface; wherein the clock signals of the first clock interface, the second clock interface and the third clock interface are the same, and the first clock interface and the second clock interface are respectively used as clock references for link training of the switch and the communication protocol; the first controller is connected to the second controller through the reset interface and the reset interface; the second controller is connected to the switch and the port device; the device comprises: A receiving module, used for receiving an enable signal of a clock signal; A control module, used for controlling the reset interface to send a reset signal to the switch through a preset delay time; The output module is used to receive the first reset signal sent by the first controller and then synchronously output the second reset signal to the switch and the port device to complete the establishment of the communication link.

9. A device for establishing a communication link, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the method for establishing a communication link as claimed in claim 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for establishing a communication link as claimed in claim 7 are implemented.

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