Data processing method, device and system and readable medium

Abstract

The invention provides a data processing method, which comprises the following steps: when a data exchange request message sent by a first cache unit is received, determining corresponding first target data in a memory according to address information carried in the data exchange request message, and sending a notification message to the first cache unit to enable the first cache unit to send second target data and third data, the third data is data exchanged with the first target data, and the second target data is data requested to be read by the second cache unit; under the condition that the second target data is not equal to the first target data, returning a data exchange response message carrying third data to the first cache unit; according to the embodiment of the invention, the bus bandwidth overhead can be reduced, and the chip power consumption is reduced. The invention further provides a data processing device, a data processing system and a readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer processing technology, and in particular to a data processing method, device, system and readable medium. Background Art

[0002] SMP (Symmetric multiprocessing) system refers to a system in which multiple CPUs in a server work symmetrically, and there is no master-slave relationship between the CPUs. Each CPU shares the same physical memory, and the time required for each CPU to access any address in the memory is the same, so SMP is also called Uniform Memory Access (UMA).

[0003] Based on the data access of the SMP system, if ATCCOMPARE (AtomicCompare) fails, the HN (Home Node) does not perform the data exchange operation, but the data in the cache unit is still invalidated. If the cache unit needs to access this data later, it must re-initiate a request to the HN to read the data, which reduces the processing performance of the processing core corresponding to the cache unit. Summary of the invention

[0004] The present disclosure provides a data processing method, device, system and readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a data processing method, including:

[0006] Receive a data exchange request message sent by the first cache unit, obtain address information carried in the data exchange request, and determine first target data corresponding to the address information in the memory;

[0007] Sending a notification message to the first cache unit;

[0008] receiving second target data and third data sent by the first cache unit, wherein the third data is data to be exchanged with the first target data, and the second target data is data that the second cache unit has requested to read;

[0009] In a case where the second target data is not equal to the first target data, a data exchange response message carrying the third data is returned to the first cache unit.

[0010] On the other hand, an embodiment of the present disclosure also provides a data processing device, including: one or more processors; a storage device on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method as described above.

[0011] On the other hand, an embodiment of the present disclosure further provides a data processing system, comprising at least one processing chip, wherein the processing chip comprises the data processing device as described above.

[0012] On the other hand, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein the program implements the data processing method as described above when executed.

[0013] The data processing method provided by the embodiment of the present disclosure, when receiving a data exchange request message sent by a first cache unit, determines the corresponding first target data in the memory according to the address information carried therein, and sends a notification message to the first cache unit for the first cache unit to send second target data and third data, wherein the third data is data for data exchange with the first target data, and the second target data is data that the second cache unit has requested to obtain; when the second target data is not equal to the first target data, returns a data exchange response message carrying the third data to the first cache unit; the embodiment of the present disclosure first compares the data, and then decides whether to initiate data monitoring of other cache units. If the data comparison is unsuccessful, data monitoring of other cache units is no longer initiated and other cache units no longer invalidate the corresponding data, so that it will not affect other processing cores to use the data, thereby reducing bus bandwidth overhead and chip power consumption; in addition, when other processing cores access the data, they can directly read the data from the other cache units without re-accessing the memory to read the data, which can further reduce bus bandwidth overhead and chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a flowchart of data processing in the related technology;

[0015] Figure 2 The data processing flow diagram provided by the embodiment of the present disclosure is as follows: Figure 1 ;

[0016] Figure 3 The data processing flow diagram provided by the embodiment of the present disclosure is as follows: Figure 2 ;

[0017] Figure 4 A schematic diagram of the process flow of ATCCOMPARE failure provided in an embodiment of the present disclosure;

[0018] Figure 5A schematic diagram of a successful ATCCOMPARE process provided in an embodiment of the present disclosure;

[0019] Figure 6 A schematic diagram of the structure of a data processing system (SMP) provided in an embodiment of the present disclosure Figure 1 ;

[0020] Figure 7 A schematic diagram of the structure of the data processing system provided in the embodiment of the present disclosure Figure 2 ;

[0021] Figure 8 A schematic diagram of the structure of a data processing system (CC-NUMA) provided in an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0022] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0023] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0025] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0027] The data processing method and system according to the embodiments of the present disclosure are applicable to any data processing system involving atomic operations, such as an SMP system, a cache-coherent non-uniform memory access system (CC-NUMA), etc. In the following example, the SMP system is taken as an example for description, but the embodiments of the present disclosure are not limited thereto.

[0028] Figure 6 A schematic diagram of an SMP system architecture is shown in FIG. Figure 6 As shown in FIG. 1 , the SMP system includes: a processing core (Core), a secondary cache (L2), a network-on-chip (NOC), a host node (HN), and a memory (Memory). Both L2 and HN are connected to NOC, and HN is connected to the memory. L2 may include one or more cache units, each of which may be connected to one or more processing cores. Figure 6 In the SMP system shown, L2 includes three cache units L2-0, L2-1 and L2-2, where L2-0 is connected to the processing core Core0, L2-1 is connected to the processing core Core1, and L2-2 is connected to the processing core Core2. In the SMP system, HN interacts with each cache unit of L2 to achieve cache consistency. HN manages the entire memory space in units of cache lines and tracks the memory access of each L2 cache unit.

[0029] MESI represents four states of cache line data. By switching these four states, the purpose of managing cache data is achieved. The states of MESI and their descriptions are shown in Table 1:

[0030] Table 1

[0031]

[0032] HN can track the access of all cache line data by maintaining a directory table (dir table). The data structure of the directory table (dir table) is shown in Table 2:

[0033] Table 2

[0034] State Bit width (VEC) state[1:0] vec[n-1:0]

[0035] In Table 2, each entry corresponds to a cache line data, and the location of the cache line data can be determined based on the address information. An entry includes a state field (State) and a bit width field (VEC). The state field records the state of the data read by the cache unit, and the bit width field corresponds to the number n of cache units in L2. Each bit corresponds to a cache unit in L2, indicating which cache unit in L2 stores the data.

[0036] The state field in Table 2 will only record the three states of ESI, because after the L2 cache unit gets the data in the E state, the action of modifying the data will not notify HN, so HN does not know whether the state of the data stored in the L2 cache unit is E state or M state. For example, dir.state = E, VEC = 'b001, indicating that the data of this cache line in L2-0 may be in M ​​state, E state, S state (downgraded from E state to S state without notifying HN), I state (data replaced from the cache unit without notifying HN); dir.state = S, VEC = 'b011, indicating that the data of this cache line in L2-0 and L2-1 may be in S state or I state (data replaced from the cache unit without notifying HN); dir.state = I, indicating that no L2 cache unit stores the cache line data.

[0037] Figure 1 FIG. 1 is a flow chart of data processing in the related art, namely, the atomic lock operation flow of AtomicCompare in the SMP system. Figure 1 As shown, the process includes the following steps:

[0038] Step 1, L2-0 sends an RDS (Read Date S, shared state data read request) message to HN, requesting to read data. After receiving the RDS message, HN returns a DATS (Date S, shared data read response) message and records the requested data as S state; after receiving the DATS message, L2-0 stores the requested data and changes the state of the data from I state to S state, wherein the data state of each cache unit is initially I state.

[0039] Step 2, L2-1 sends an ATCCOMPARE (atomic comparison) message to HN to implement the AtomicCompare atomic operation. The ATCCOMPARE message carries the address information, and HN queries the memory to obtain the data corresponding to the address information. On the one hand, HN returns a DBIDRESP (Date Buffer ID Response) message to L2-1; on the other hand, HN sends a SNPtoI (Snoop to Invalid) message to L2-0 to snoop on L2-0.

[0040] Step 3: After receiving the DBIDRESP message, L2-1 sends ATCCOMPARE_DAT (Atomic CompareData) to HN. ATCCOMPARE_DAT includes exchange data and comparison data.

[0041] Step 4: After the HN receives ATCCOMPARE_DAT, the data corresponding to the address information fails to be compared with the comparison data.

[0042] Step 5: After receiving the SNPtoI message, L2-0 invalidates the data corresponding to the address information and returns a SNPRSPI (Snoop Response Invalid) message to the HN.

[0043] Step 6: After receiving the SNPRSPI message, the HN records the data corresponding to the address information as the I state, and returns a DATI (Date I, invalid state data response) message to L2-1.

[0044] If the processing core Core0 corresponding to L2-0 still needs to use the data corresponding to the address information, it needs to resend the RDS message to HN to read the data, that is, it needs to execute step 7.

[0045] Step 7, L2-0 sends an RDS message to HN to request to read data. After receiving the RDS message, HN returns a DATS message and records the requested data as S state. After receiving the DATS message, L2-0 stores the requested data and changes the state of the data from I state to S state.

[0046] It should be noted that in step 4, if the comparison data in ATCCOMPARE_DAT is successfully compared with the data corresponding to the address information, HN modifies the data corresponding to the address information in the memory to the exchange data in ATCCOMPARE_DAT, and continues to execute subsequent steps. If the processing core Core0 corresponding to L2-0 still needs to access the data corresponding to the address information, at this time, the data corresponding to the address information in the memory has been modified, and L2-0 needs to resend the RDS message to HN to obtain the modified data (i.e., exchange data), that is, step 7 needs to be executed.

[0047] The defect of the related technical solution is that if the data comparison fails, the data corresponding to the address information in the memory is not actually modified, that is, no data exchange operation is performed, but the data in L2-0 is still invalidated. If the subsequent processing core Core0 still needs to access this data, it must re-initiate RDS to read the data, which will reduce the processing performance of the processing core.

[0048] In order to solve the above technical problems, the embodiment of the present disclosure provides a data processing method, which is applied to a data processing system, in which the lock performance is particularly important. The data processing system can be an SMP system or a cache-coherent non-uniform memory access system (CC-NUMA). In the embodiment of the present disclosure, Figure 6 The data processing system (SMP) shown in FIG. 1 is used as an example for explanation, wherein L2-1 is a first cache unit, L2-0 is a second cache unit, and a data processing device interacting with L2-1 and L2-0 is HN. Figure 2 As shown, the data processing method can be executed by a data processing device in a data processing system, and includes the following steps:

[0049] Step 11: Receive a data exchange request message sent by the first cache unit, obtain address information carried in the data exchange request, and determine the first target data corresponding to the address information in the memory.

[0050] In this step, L2-1 sends an ATCCOMPARE message carrying address information to HN to request HN to modify the data corresponding to the address information in the memory. HN searches the memory according to the address information carried in the ATCCOMPARE message to obtain the first target data corresponding to the address information.

[0051] Step S12: Send a notification message to the first cache unit.

[0052] In this step, HN allocates data buffer space locally, which is used to store the data sent by L2-1 later. The notification message is a data buffer identification response (DBIDRESP) message. After HN allocates data buffer space, it returns a DBI DRESP message to L2-1. The DBI DRESP message is used to indicate that the data buffer space has been allocated and exchange data and comparison data can be sent to HN.

[0053] Step S13, receiving the atomic comparison data notification message sent by the first cache unit, and obtaining the second target data and third data carried in the atomic comparison data notification message, wherein the third data is data exchanged with the first target data (i.e., exchange data), and the second target data is data that the second cache unit has requested to read.

[0054] The second target data is the comparison data, which is the data that the second cache unit has previously requested to read from the HN and has been recorded as a shared state. The second cache unit and the first cache unit are cache units of the same level. In the embodiment of the present disclosure, the second cache unit L2-0 and the first cache unit L2-1 are both cache units of the second-level cache L2.

[0055] In this step, L2-1 sends ATCCOMPARE_DAT to HN. ATCCOMPARE_DAT includes the second target data and the third data. The second target data and the third data can be stored in the cache space allocated in step S12. The third data is the data exchanged with the first target data, which is the modified data (i.e., exchanged data) at the corresponding position of the address information in the memory; the second target data is the data that other cache units have previously requested to read from HN, that is, the data that L2-0 has accessed, and the state of the data recorded in L2-0 is the S state.

[0056] Step S14: When the second target data is not equal to the first target data, a data exchange response message carrying the third data is returned to the first cache unit.

[0057] In this step, HN compares the second target data with the first target data. If the two are not equal, it means that the data to be modified by L2-1 is different from the data previously requested to be read by L2-0, and then a DATI message is returned to L2-1. The DATI message is a response message to the ATCCOMPARE message. It should be noted that, when the second target data is not equal to the first target data, the DATI message carries the third data, indicating that HN has not written the third data into the memory.

[0058] The data processing method provided by the embodiment of the present disclosure, when receiving a data exchange request message sent by a first cache unit, determines the corresponding first target data in the memory according to the address information carried therein, and sends a notification message to the first cache unit for the first cache unit to send second target data and third data, wherein the third data is data for data exchange with the first target data, and the second target data is data that the second cache unit has requested to obtain; when the second target data is not equal to the first target data, returns a data exchange response message carrying the third data to the first cache unit; the embodiment of the present disclosure first compares the data, and then decides whether to initiate data monitoring of other cache units. If the data comparison is unsuccessful, data monitoring of other cache units is no longer initiated and other cache units no longer invalidate the corresponding data, so that it will not affect other processing cores to use the data, thereby reducing bus bandwidth overhead and chip power consumption; in addition, when other processing cores access the data, they can directly read the data from the other cache units without re-accessing the memory to read the data, which can further reduce bus bandwidth overhead and chip power consumption.

[0059] In some embodiments, Figure 3 As shown, after receiving the second target data and the third data sent by the first cache unit (ie, step S13), the data processing method may further include the following steps:

[0060] Step S21, when the second target data is equal to the first target data, a data monitoring message is sent to the second cache unit, so that the second cache unit modifies the state of the second target data to an invalid state.

[0061] In this step, HN compares the second target data with the first target data. If the second target data is not equal to the first target data, it means that the data to be modified by L2-1 is the same as the data previously requested to be read by L2-0. In this case, HN initiates data monitoring of L2-0 by sending a SNPtoI message to L2-0, so that L2-0 invalidates the second target data, that is, L2-0 changes the state of the second target data from state to I state.

[0062] Step S22: receiving a data monitoring response message sent by the second cache unit.

[0063] In this step, after L2-0 changes the state of the second target data from the S state to the I state, it returns a SNPRSPI message to the HN. The SNPRSPI message is a response message of the SNPtoI message, and is used to inform the HN that the second target data has changed to the I state.

[0064] Step S23, writing the third data into the memory according to the address information, and modifying the state of the data corresponding to the address information to an invalid state.

[0065] In this step, HN writes the third data into the location corresponding to the address information in the memory, that is, updates the first target data with the third data, and modifies the state of the corresponding data in Table 2 to the I state.

[0066] Step S24: Return a data exchange response message carrying the first target data to the first cache unit.

[0067] In this step, HN returns a DATI message to L2-1, and the DATI message is a response message to the ATCCOMPARE message. It should be noted that, when the second target data is equal to the first target data, the DATI message carries the first target data, indicating that HN has modified the first target data to the third data in the memory, that is, the first target data has been invalidated. In this way, L2-1 uses the third data to exchange data with the first target data in the memory, thereby modifying the data in the memory that has been accessed by L2-0.

[0068] In some embodiments, before receiving the data exchange request message sent by the first cache unit (ie, step S11), the data processing method further includes the following steps:

[0069] Step S31: receiving a data read request message sent by the second cache unit, and modifying the state of the requested second target data of the second cache unit to a shared state.

[0070] In this step, L2-0 sends an RDS message to HN to request to read the second target data, and HN modifies the state of the second target data to S state in Table 2.

[0071] Step S32: Return the second target data to the second cache unit, so that the second cache unit stores the second target data and changes the state of the second target data to a shared state.

[0072] In this step, HN sends a DATS message to L2-0. The DATS message is a response message to the RDS message and carries the second target data. L2-0 stores the second target data and changes the state of the second target data from the I state to the S state.

[0073] It should be noted that after executing step S24, if the processing core Core0 corresponding to L2-0 still needs to access the data corresponding to the address information, and the data corresponding to the address information in the memory has been modified to the third data, therefore, L2-0 needs to resend the RDS message to HN to read the modified data (i.e., the third data), that is, it needs to execute steps 31-S32 again.

[0074] In order to clearly illustrate the technical solutions of the embodiments of the present disclosure, the following are respectively combined with Figure 4 and Figure 5 , describes the process of handling ATCCOMPARE failure and ATCCOMPARE success. Figure 4 As shown, the ATCCOMPARE failure processing flow includes the following steps:

[0075] Step S101, L2-0 needs to access the second target data, sends an RDS message to HN and receives a DATS message, thereby obtaining the second target data, L2-0 caches the second target data, and records its state as S state. After receiving the RDS message, HN modifies the state of the corresponding data in Table 2 to S state.

[0076] Step S102, L2-1 sends an ATCCOMPARE message carrying address information to HN. After allocating data cache space, HN returns a DBI DRESP message to L2-1 to notify L2-1 that it can send data.

[0077] Step S103: After receiving the DBI DRESP message, L2-1 sends ATCCOMPARE_DAT to HN, where ATCCOMPARE_DAT includes the second target data and the third data.

[0078] Step S104, after receiving ATCCOMPARE_DAT, the HN compares the second target data with the first target data corresponding to the address information, and if the two are not equal, the data comparison fails.

[0079] Step S105: HN directly returns a DATI message to L2-1, where the DATI message carries the third data.

[0080] It can be seen from the above steps S101-S105 that the embodiment of the present disclosure will not initiate data monitoring on L2-0 before performing data comparison. Accordingly, L2-0 will not modify the state of the second target data (still in S state). In this way, data comparison failure does not affect the data cached in L2-0, and the processing core Core0 corresponding to L2-0 can continue to access the data from L2-0 without having to re-initiate an RDS request to HN as in the existing solution.

[0081] In the disclosed embodiment, when Atomic Compare data comparison fails, no monitoring message will be sent to other cache units (i.e., L2-0). In this way, other cache units will not invalidate the data. Therefore, it will not affect the use of the data by other processing cores (Core0). Other processing cores (Core0) do not need to re-access the memory when accessing the data, thereby reducing bus bandwidth overhead and reducing chip power consumption.

[0082] like Figure 5 As shown, the successful processing flow of ATCCOMPARE includes the following steps:

[0083] Step S201, L2-0 needs to access the second target data, sends an RDS message to HN and receives a DATS message, thereby obtaining the second target data, L2-0 caches the second target data, and records its state as S state. After receiving the RDS message, HN modifies the state of the corresponding data in Table 2 to S state.

[0084] Step S202, L2-1 sends an ATCCOMPARE message carrying address information to HN, and HN returns a DBIDRESP message to L2-1 after allocating data cache space.

[0085] Step S203: After receiving the DBIDRESP message, L2-1 sends ATCCOMPARE_DAT to HN, where ATCCOMPARE_DAT includes the second target data and the third data.

[0086] Step S204, after receiving ATCCOMPARE_DAT, the HN compares the second target data with the first target data corresponding to the address information, and if the two are not equal, the data comparison is successful.

[0087] Step S205: HN sends a SNPtoI message to L2-0 to monitor L2-0.

[0088] Step S206, L2-0 receives the SNPtoI message, changes the state of the data corresponding to the address information from the S state to the I state, invalidates the data, and returns a SNPRSPI message to the HN to inform the HN that the data has been invalidated and can be modified.

[0089] Step S207, after receiving the SNPRSPI message, the HN writes the third data into the memory according to the address information, changes the state of the data corresponding to the address information to the I state, and returns a DATI message to L2-1, the DATI message carries the first target data, and the Atomic operation is successful.

[0090] It can be seen from steps S201-S207 that only when the data comparison is successful will it affect the data cached in L2-0. L2-0 needs to invalidate the accessed data. In this way, if the processing core Core0 corresponding to L2-0 needs to access the data again later, since the data cached in L2-0 is invalid, L2-0 needs to re-initiate an RDS request to HN.

[0091] The disclosed embodiments improve the atomic lock operation process of AtomicCompare and can be applied to systems such as SMP and CC-NUMA. In these systems, the performance of atomic lock is particularly important. The disclosed embodiments can improve the performance of AtomicCompare while reducing bandwidth overhead and chip power consumption.

[0092] In the embodiment of the present disclosure, in the case of data comparison failure, it is not necessary to monitor other cache units storing S-state data, which can avoid invalidating the data stored in other cache units after the data comparison fails, and ensure that the corresponding processing core can continue to read data from the cache unit. Only when the data comparison is successful, the monitoring of other cache units storing S-state data is initiated, thereby achieving the effect of improving the performance of the processing core. At the same time, the additional bandwidth and power consumption caused by cache unit monitoring and processing core re-accessing memory are reduced.

[0093] An embodiment of the present disclosure also provides a data processing device, which includes: one or more processors and a storage device; wherein one or more programs are stored on the storage device, and when the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method provided in the aforementioned embodiments.

[0094] The embodiment of the present disclosure further provides a data processing system, which includes at least one processing chip, and the processing chip includes the data processing device as described above.

[0095] In some embodiments, the processing system further includes a memory, at least two levels of cache, each level of cache includes at least one cache unit, and the data processing device may be a master node (HN), or the data processing device may also be one of the cache units at different levels from the first cache unit and the second cache unit. That is, the embodiments of the present disclosure are not limited to the cache unit accessing the memory data by interacting with the HN, and the cache unit may also access the memory data by interacting with cache units at other levels.

[0096] It should be noted that the processing system may further include an on-chip network NOC, and cache units at different levels and the master node may communicate through the NOC.

[0097] like Figure 7As shown, the processing system includes a second-level cache L2, a third-level cache L3 and a fourth-level cache L4, L2 includes three cache units L2-0, L2-1, and L2-2, L2-0 is connected to the processing core Core0, L2-1 is connected to the processing core Core1, and L2-2 is connected to the processing core Core2. L3 includes two processing units L3-1 and L3-2, and the data processing device can be a cache unit of the master node HN or L4.

[0098] The data processing system may be a symmetric multiprocessor (SMP) system or a cache-consistent non-uniform memory access (CC-NUMA) system.

[0099] In some embodiments, there may be at least two processing chips, each processing chip is connected to at least another processing chip, and the processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

[0100] In some embodiments, the processing chip includes but is not limited to: a central processing unit (CPU), a graphics processing unit (GPU), an embedded neural network processor (NPU), and a data processor (DPU).

[0101] In a data processing system including multiple processing chips, such as a CC-NUMA system, a cache unit can access memory data of the same processing chip as well as memory data of other processing chips, that is, cross-CPU access is achieved.

[0102] In a CC-NUMA system, distributed memories are connected to form a single memory. There is no page copying or data copying between memories, and there is no software message transmission. It is relatively fast for a processing chip to access local memory, but it is relatively slow to access remote memory belonging to another processing chip because additional delays are generated through the interconnection network. CC-NUMA has only one memory image, and the memory of each processing chip is physically connected using copper cables and some intelligent hardware. Cache-Coherent means that no software is required to maintain the consistency of multiple copies of data, nor is software required to implement data transmission between the operating system and the application system. The CC-NUMA system is the same as the SMP system. A single operating system and multiple processors are managed completely at the hardware level.

[0103] like Figure 8The CC-NUMA system shown includes four processing chips, each of which is connected in pairs, and a cache unit in one of the processing chips can implement cross-chip memory data access. It should be noted that the embodiment of the present disclosure does not limit the connection method of each processing chip in the CC-NUMA system. For example, each processing chip can also be connected in series.

[0104] The embodiments of the present disclosure further provide a computer-readable medium on which a computer program is stored, wherein the computer program, when executed, implements the data processing method provided in the aforementioned embodiments.

[0105] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, the functional modules / units in the device may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0106] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A data processing method, characterized in that: A data processing device applied to a data processing system, the method comprising: Receive a data exchange request message sent by the first cache unit, obtain address information carried in the data exchange request, and determine first target data corresponding to the address information in the memory; Sending a notification message to the first cache unit; receiving second target data and third data sent by the first cache unit, wherein the third data is data to be exchanged with the first target data, and the second target data is data that the second cache unit has requested to read; In a case where the second target data is not equal to the first target data, a data exchange response message carrying the third data is returned to the first cache unit.

2. The method according to claim 1, characterized in that After receiving the second target data and the third data sent by the first cache unit, the method further includes: When the second target data is equal to the first target data, sending a data monitoring message to the second cache unit so that the second cache unit can modify the state of the second target data to an invalid state; Receiving a data monitoring response message sent by the second cache unit; Writing the third data into the memory according to the address information, and modifying the state of the data corresponding to the address information to an invalid state; A data exchange response message carrying the first target data is returned to the first cache unit.

3. The method according to claim 2, characterized in that The data monitoring message is an invalidation monitoring message, and the data monitoring response message is an invalidation status monitoring response message.

4. The method according to claim 1, characterized in that Before receiving the data exchange request message sent by the first cache unit, the method further includes: receiving a shared state data read request message sent by the second cache unit, and modifying the state of the requested second target data of the second cache unit to a shared state; A shared state data read response message carrying the second target data is returned to the second cache unit, so that the second cache unit can store the second target data and modify the state of the second target data to a shared state.

5. The method according to claim 1, characterized in that The data exchange request message is an atomic comparison message, the notification message is a data cache identification response message, and the data exchange response message is an invalid status data response message.

6. The method according to any one of claims 1 to 5, characterized in that: The data processing system includes a processing chip, a memory, and at least two levels of cache. The processing chip includes the data processing device. Each level of the cache includes at least one cache unit. The data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

7. A data processing device, wherein: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method according to any one of claims 1 to 6.

8. A data processing system, characterized in that: The device comprises at least one processing chip, wherein the processing chip comprises the data processing device according to claim 7.

9. The data processing system according to claim 8, characterized in that The processing system also includes a memory and at least two levels of cache, each level of the cache includes at least one cache unit, the data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

10. The data processing system according to claim 8, characterized in that The data processing system is a symmetric multiprocessor system or a cache consistency non-uniform storage access system.

11. The data processing system according to claim 10, characterized in that There are at least two processing chips, each of which is connected to at least another processing chip. The processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

12. The data processing system according to any one of claims 8 to 11, characterized in that: The processing chip is one of the following: a central processing unit, a graphics processing unit, an embedded neural network processor, and a data processor.

13. A computer readable medium having a computer program stored thereon, wherein: When the program is executed, the data processing method according to any one of claims 1 to 6 is implemented.

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