System exception handling method, control system and storage medium

Abstract

The invention relates to a system exception handling method, which comprises the following steps: firstly, judging whether a main processor and a unit module in a system have communication exception or not, if the unit module has the communication exception, sending a preset level signal to a monitoring chip by the main processor, reading and analyzing the preset level signal by the monitoring chip, and based on received exceptional module identification information, judging whether the exceptional module is abnormal or not; the main processor and the monitoring chip are connected through a first signal line and a second signal line, and the first signal line and the second signal line have a high level state and a low level state. Therefore, the abnormal unit module is determined according to the high and low levels between the main processor and the monitoring chip, the corresponding level signal period and the abnormal module identification information acquired by the main processor, and then the monitoring chip resets or powers on and off the abnormal unit module so as to enable the abnormal unit module to return to normal.

Description

Technical Field

[0001] The present application relates to the field of embedded system security, and in particular to a system exception handling method, a control system and a storage medium. Background Art

[0002] For the operation of embedded systems, ensuring that the system operates normally and safely for a long time is the primary task. The system protection method commonly used in the prior art is to directly trigger the overall system reset when the system is abnormal.

[0003] This method has certain defects, such as: it is impossible to reset the abnormal functional unit module in the system separately, which affects the working efficiency of the system. In addition, there is also a situation where the system soft reset fails to reset the system successfully, causing the system to fail to work normally. Summary of the invention

[0004] The present application provides a system exception handling method, a control system and a storage medium to solve the problem in the prior art that if a system exception occurs, the entire system is directly triggered to reset, affecting the system working efficiency or causing the system to fail to work normally.

[0005] In a first aspect, the present application provides a system exception handling method, the system comprising a main processor, a monitoring chip and a plurality of unit modules, the method comprising: Determine whether communication abnormality occurs between the main processor and the unit module in the system; If the unit module has a communication anomaly, the main processor sends a preset level signal to the monitoring chip, wherein the main processor and the monitoring chip are connected via a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels; The monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication abnormality to perform reset or power on / off operation.

[0006] Furthermore, if the unit module has a communication anomaly, the main processor sends a preset level signal to the monitoring chip, including: If there is only one unit module with abnormal communication, the main processor controls the first signal line and the second signal line to output a level signal. Wherein, the level signal includes a first signal and a second signal; The first signal is the first signal line and the second signal line, one of which outputs a high level and the other outputs a low level, and the opposite levels are maintained for a first preset time; The second signal is that after the output of the first signal is completed, the first signal line and the second signal line both maintain a low level output and last for a second preset time.

[0007] Furthermore, if the unit module has a communication anomaly, the main processor sends a preset level signal to the monitoring chip, and further includes: If there are more than one unit modules with abnormal communication, count the number N of abnormal unit modules detected by the main processor; The main processor controls the first signal line and the second signal line to output N level signals in sequence, Wherein, the level signal includes a first signal and a second signal; The first signal is the first signal line and the second signal line, one of which outputs a high level and the other outputs a low level, and the opposite levels are maintained for a first preset time; The second signal is that after the output of the first signal is completed, the first signal line and the second signal line both maintain a low level output and last for a second preset time.

[0008] Further, the monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication abnormality to perform reset or power-on and power-off operations, including: The monitoring chip determines the target module based on the signal analysis information and the abnormal module identification information; Determine whether the target module has a reset port; If there is a reset port, the monitoring chip controls the reset port of the target module to reset the target module; If there is no reset port, the monitoring chip controls the power supply port of the target module to power off the target module, and then controls the target module to power on after the power-off time is a third preset time.

[0009] Furthermore, after the monitoring chip reads and analyzes the preset level signal and controls the unit module with communication abnormality to reset or power on / off based on the received abnormal module identification information, the method further includes: Monitoring whether the target module resumes normal communication within a fourth preset time, wherein the fourth preset time is counted from the time when the monitoring chip receives the preset level signal; If not, return to the step of executing the main processor sending a preset level signal to the monitoring chip, and the monitoring chip reading and parsing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to reset or power on and off.

[0010] Further, the step of returning to execute the monitoring chip to read and parse the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to reset or power on and off, includes: If the target module has a reset port, and the monitoring chip can control both the reset port and the power port of the target module, the monitoring chip controls the power port of the target module to power off the target module, and then controls the target module to power on after a third preset time has passed since the power-off.

[0011] Further, after returning to execute the step of the main processor sending a preset level signal to the monitoring chip, and the monitoring chip reading and parsing the preset level signal, and controlling the unit module with communication abnormality to reset or power on and off based on the received abnormal module identification information, the method also includes: If the target module has not yet restored normal communication, the monitoring chip, after reading and parsing the preset level signal, continuously controls the power supply port of the target module to power on and off, so that the target module can restore normal communication.

[0012] Furthermore, the determining whether communication abnormality occurs between the main processor and the unit module in the system includes: If the first signal line or the second signal line outputs a high level or a low level and the duration is greater than a fourth preset time, it is determined that a communication abnormality occurs in the main processor; After determining whether communication abnormality occurs between the main processor and the unit module in the system, the method further includes: If the main processor has a communication anomaly, the monitoring chip controls the reset port of the main processor to reset it; Determine whether the first signal line and the second signal line both output a high level or a low level, and the duration is greater than a fourth preset time; If yes, the monitoring chip controls the power supply port of the main processor to power it off, and after the power-off period is a fourth preset time, controls the power supply port of the main processor to power it on; Determine again whether the first signal line and the second signal line both output a high level or a low level, and the duration is greater than a fourth preset time; If so, the monitoring chip controls the power supply port of the main processor and the power supply ports of all unit modules to power off all of them, and after the fourth preset time, controls the power supply port of the main processor and the power supply ports of all unit modules to power on all of them.

[0013] In a second aspect, the present application provides a control system, the control system comprising a main processor module, a monitoring module and a plurality of unit modules, the main processor module and the monitoring module are connected via a first signal line and a second signal line, the first signal line and the second signal line having two states of high and low levels; The monitoring module is used to determine whether communication abnormalities occur between the main processor module and the unit module in the system based on the monitoring signal; The main processor module is used to send a preset level signal to the monitoring module if a communication abnormality occurs in the unit module; The monitoring module is further used to read and analyze the preset level signal, and based on the received abnormal module identification information, control the unit module with communication abnormality to perform reset or power on and off operations.

[0014] In a third aspect, the present application also provides a computer storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the system exception handling method described in the present application.

[0015] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: 1. If one or more functional unit modules in the system have operational problems, there is no need to reset the entire system. Fixed-point reset of specific unit modules is achieved, which shortens the time from abnormal to normal system and improves the stability and reliability of the system.

[0016] 2. When a unit module of the system has a problem, it can first control the reset input port to reset the unit module in a safe way. If it is ineffective, it can be powered on and off again through the power supply port in a tough way. In this way, it is not a rough way to directly cut off the power when encountering an abnormality. The unit module is protected as much as possible to quickly and safely resume work, reducing the physical damage caused by power outages to the system and extending the service life of the system. In addition, if the system is not restored to normal through the reset port or the power supply port, it can be retried several times, which can increase the probability of the system returning to normal, thereby making the system operation more secure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0020] Figure 1 A flowchart of a system exception handling method provided in an embodiment of the present application; Figure 2 A schematic diagram of system communication provided in an embodiment of the present application; Figure 3 A schematic diagram of a level signal output indicating that the main processor and each unit module communicate normally, provided in an embodiment of the present application; Figure 4 A schematic diagram of a level signal output indicating abnormal communication of a unit module provided in an embodiment of the present application; Figure 5 A schematic diagram of a level signal output indicating abnormal communication between two unit modules provided in an embodiment of the present application; Figure 6 Another flow chart of a system exception handling method provided in an embodiment of the present application; Figure 7 Another flow chart of a system exception handling method provided in an embodiment of the present application (for main processor exception); Figure 8 A module interaction diagram of a control system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0023] In order to solve the problems in the prior art, the present application provides a method for automatically restoring normal operation when an abnormality occurs in each unit module and main processor of the control system through a specific waveform.

[0024] Figure 1 A system exception handling method provided in an embodiment of the present application includes: S101, determining whether communication abnormality occurs between the main processor and the unit module in the system; In one embodiment, the system in the present application is composed of a main processor, a watchdog IC (monitoring chip), and multiple unit modules. According to the function and architecture of the system, the unit module can be different functional modules and the number can be different, and there can be multiple. Figure 2 , taking 3 unit modules as an example, the communication between modules in the system is as follows: The main processor is connected to the watchdog IC through signal lines A and B, where signal lines A and B are the first signal line and the second signal line, and signal lines A and B have two states: high and low. The watchdog IC is connected to the power supply port (VCC) of the main processor and the unit module in the system, and the main processor and each unit module interact with each other through their respective signal lines (sync) for output transmission. If the main processor and the unit module have their own reset signal (RESET) input ports, connect each input port to the watchdog IC. Whether there is a reset signal input port depends on the main processor and the unit module's own situation, and whether they have a RESET pin.

[0025] When the external power supply (VBAT) supplies power to the system, the watchdog IC works normally. The watchdog IC turns on the power supply (VCC) switch of each unit to power on the main processor and unit modules in the system.

[0026] The main processor checks whether the communication between each unit module is normal. If the communication between each unit module and the main processor is normal, the main processor cycles every second, and controls the signal line A and signal line B to output high level for 300ms at the same time, and then output low level for 700ms at the same time. The signal output diagram is shown in Figure 3 It should be noted that, according to the communication protocol and communication mechanism between the main processor and each unit module, if an abnormality occurs in a unit module, the main processor can be informed, which is common knowledge and the specific principle will not be repeated here.

[0027] The present application involves two situations: main processor abnormality or unit module abnormality. For different abnormal situations, the level output conditions of signal line A and signal line B are different, and this is used to determine which abnormal situation it belongs to. Furthermore, if the unit module is abnormal, the level output conditions of signal line A and signal line B are also different for one unit module abnormality and more than one unit module abnormality.

[0028] S102: If a communication abnormality occurs in the unit module, the main processor sends a preset level signal to the monitoring chip, wherein the main processor and the monitoring chip are connected via a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels; In an embodiment of the present application, if the main processor finds that a communication abnormality occurs in the unit module, then after outputting a level signal indicating that the communication between the main processor and the unit module is normal, the control signal line A and the signal line B send a preset level signal to the watchdog IC so that the watchdog IC can be informed of the abnormal situation, and then the watchdog IC controls the corresponding unit module to restore it to normal.

[0029] Specifically, the preset level signal is divided into the following two cases: The first case: if there is only one unit module with abnormal communication, the main processor controls the first signal line and the second signal line to output a level signal, wherein the level signal includes the first signal and the second signal; The output of the first signal is: controlling the first signal line and the second signal line, one of which outputs a high level and the other outputs a low level, and the two maintain opposite levels for a first preset time; The output of the second signal is: after the output of the first signal is completed, the first signal line and the second signal line are controlled to maintain a low level output and continue for a second preset time.

[0030] The second situation: if the number of unit modules with communication abnormalities is greater than one, the number of abnormal unit modules detected by the main processor is counted N, and then the main processor controls the first signal line and the second signal line to output N level signals in sequence, which can be understood as the signal output of the first situation is cycled N times.

[0031] It should be noted that N ≥ 2 and is an integer, the first preset time is preferably 50ms, and the second preset time is preferably 100ms. These two preferred time values ​​are the best values ​​for the test. In specific implementation, a time with a small range of fluctuation around these two preferred time values ​​is also acceptable, and there is no specific limitation on this. For further information, see Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of the preset level signal when an abnormality occurs in a unit module. Figure 5 A schematic diagram of preset level signals when two unit modules are abnormal.

[0032] It is worth noting that the first signal indicates a signal flip, and the second signal indicates the end of the flip. Several signal flips indicate that several unit modules are abnormal.

[0033] S103, the monitoring chip reads and analyzes the preset level signal, and controls the unit module with communication abnormality to reset or power on and off based on the received abnormal module identification information.

[0034] In the embodiment of the present application, step S103 specifically includes the following sub-steps: S1031, the monitoring chip determines the target module based on the signal analysis information and the abnormal module identification information; S1032, determining whether the target module has a reset port; S1033: If there is a reset port, the monitoring chip controls the reset port of the target module to reset the target module; S1034: If there is no reset port, the monitoring chip controls the power supply port of the target module to power off the target module, and then controls the target module to power on after a third preset time has passed since the power-off.

[0035] In the embodiment of the present application, the watchdog IC reads and analyzes the received preset level signal, and determines the abnormalities of several unit modules according to the specific high and low levels and the corresponding level signal cycle. In addition, since the main processor knows which unit modules are abnormal, the main processor sends the abnormal module identification information (which can be understood as: the identity ID of the unit module with abnormality) to the watchdog IC. At this time, the watchdog IC can determine the unit module with abnormality, that is, the target module. Further, it is determined whether there is a reset port (reset signal input port) according to whether the target module has a RESET pin. If the target module has a reset port, the watchdog IC controls its reset port to reset it; if there is no reset port, the watchdog IC controls its power supply port, first powers off the target module, then waits for the third preset time, and then controls the power supply port of the target module to power it on. Exemplarily, the third preset time is preferably 2s, that is, the target module is first powered off, then waits for 2s, and then controls the target module to power it on. It should be noted that the setting of the third preset time is the same as the above explanation of the first preset time and the second preset time. In addition, the target module can be 1, 2 or more.

[0036] In the embodiment of the present application, it is first determined whether the main processor and the unit module in the system have communication anomalies. If the unit module has communication anomalies, the main processor sends a preset level signal to the monitoring chip, and the monitoring chip reads and parses the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication anomalies to reset or power on and off, wherein the main processor and the monitoring chip are connected through a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels. In this way, the unit module with abnormalities is determined through the high and low levels between the main processor and the monitoring chip and the corresponding level signal cycle, as well as the abnormal module identification information known by the main processor, and then the monitoring chip resets or powers on and off the abnormal unit module to restore it to normal.

[0037] After determining the target module and resetting or powering it on, it is also necessary to consider whether the target module has resumed normal operation. For this purpose, the present application includes another embodiment. For details, see Figure 6 After controlling the unit module with communication abnormality to reset or power on / off, the method of the present application further includes: S104, monitoring whether the target module restores normal communication within a fourth preset time, wherein the fourth preset time is counted from the time when the monitoring chip receives the preset level signal; If not, the process returns to the step of the main processor sending a preset level signal to the monitoring chip, and the monitoring chip reading and parsing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to reset or power on / off. That is, the process returns to the step of executing S102 and S103.

[0038] In the embodiment of the present application, the target module is the unit module 1 as an example, and it is checked whether the unit module 1 returns to normal after being reset or powered on and off. Specifically, after sending the preset level signal to the watchdog IC, the main processor will check the communication with the unit module 1, starting from the time when the watchdog IC receives the preset level signal, or starting from the time after the main processor sends the preset level signal to the watchdog IC. If the communication between the main processor and the unit module 1 returns to normal within 10s, the main processor cycles every second, controls the signal line A and the signal line B to output a high level for 300ms at the same time, and then outputs a low level for 700ms at the same time, and repeats the operation of the unit module. On the contrary, if the communication between the main processor and the unit module 1 still does not return to normal within 10s, the main processor will send the preset level signal to the watchdog IC again, and then the watchdog IC will read and parse it again, and then the control unit module 1 will be reset or powered on and off.

[0039] It can be seen from the above embodiments that the fourth preset time of the present application is preferably 10s. The setting of the fourth preset time is the same as the above explanation of the first preset time and the second preset time, which will not be repeated here.

[0040] In addition, regarding the watchdog IC controlling the reset or power on / off of the unit module 1 again, it should be noted that if the watchdog IC can only control the reset input port or power supply port of the unit module 1, then when controlling again, if there is a reset port, control the reset port, if there is no reset port, control the power supply port, and try to restore the unit module 1 to normal again. If the watchdog IC can control both the reset input port and the power supply port of the unit module 1, then when controlling again, for the case where there is a reset port, since the watchdog IC has tried to restore the unit module 1 to normal through the reset input port last time, but it still did not recover after 10 seconds, then this time the watchdog IC will control its power supply port, power off the unit module 1, and then wait for 2 seconds before controlling the unit module 1 to power it on. For the case where there is no reset port, follow the process of controlling the power supply port.

[0041] Furthermore, after trying to restore the unit module 1 to normal again, it is also necessary to consider whether the unit module 1 has restored normal operation. There are the following two situations: If unit module 1 returns to normal, then the next time unit module 1 is abnormal, the watchdog IC will first try to control the reset input port to reset, and then try to control the power port to restore unit module 1. In other words, unit module 1 is directly controlled twice (of course, if unit module 1 returns to normal after the first reset port control, the second time is not necessary). In this way, it is equivalent to adopting the experience of the above control process and directly performing two controls, which helps the unit module to quickly return to normal.

[0042] In another case, after trying to restore the unit module 1 to normal again, if the unit module 1 is still abnormal, the watchdog IC will continue to try to restore the unit module 1 by controlling the power port next time, that is, regardless of whether the unit module 1 has a reset port, the reset port will not be controlled. The way to control the power port is: power off the unit module 1, wait for 2 seconds, and then control the unit module 1 to power it on.

[0043] It should be noted that the principle and process of the watchdog IC's re-control of other unit modules are the same as those of unit module 1.

[0044] In an embodiment of the present application, after the watchdog IC resets or powers on and off the abnormal unit module, the main processor detects whether it has returned to normal. If not, the main processor sends a preset level signal again, and the watchdog IC continues to control the corresponding power supply port. This is repeated through multiple cycles to ensure that the system quickly resumes normal operation.

[0045] In the present application, the abnormal communication of the system may be caused by the abnormality of the unit module, and the abnormality of the main processor may also cause the system abnormality. For this reason, the present application also includes another embodiment. For details, see Figure 7 After determining whether a communication anomaly occurs between the main processor and the unit module in the system, the method of the present application further includes: S106, if the main processor has a communication anomaly, the monitoring chip controls the reset port of the main processor to reset it; S107, determining whether the first signal line and the second signal line both output a high level or a low level, and the duration is greater than a fourth preset time; S108, if yes, the monitoring chip controls the power supply port of the main processor to power off, and after the power off is for a fourth preset time, controls the power supply port of the main processor to power on; S107, determining again whether the first signal line and the second signal line both output a high level or a low level, and the duration is greater than a fourth preset time; S109. If yes, the monitoring chip controls the power supply port of the main processor and the power supply ports of all the unit modules to power off all of them, and after the fourth preset time, controls the power supply port of the main processor and the power supply ports of all the unit modules to power on all of them.

[0046] In one embodiment, if the first signal line or the second signal line outputs a high level or a low level, and the duration is greater than a fourth preset time, it is determined that the main processor has a communication abnormality. Exemplarily, if the watchdog IC detects that the signal line A or the signal line B continues to maintain a high level or a low level for more than 10 seconds, it indicates that the main processor has an abnormality.

[0047] In case of abnormality in the main processor, the watchdog IC first controls the reset input port of the main processor and tries to reset the main processor. If the signal line A / B still maintains a high level or a low level for more than 10 seconds, the watchdog IC will try to cut off the power supply port of the main processor to power it off, and then power on the main processor after 10 seconds. Then it will be determined again whether the signal line A / B maintains a high level or a low level for more than 10 seconds. If so, it means that the main processor is still abnormal. At this time, the watchdog IC will control the main processor and all other unit modules to power off, and then power on the main processor and each unit module after 10 seconds.

[0048] In the embodiment of the present application, the situation that the main processor is abnormal is taken into consideration, and a corresponding processing method is also provided for this abnormal situation, so that the operation safety of the system is fully guaranteed. In addition, when the main processor cannot be restored to normal through the reset port or the power port alone, the entire system is powered on and off to avoid directly triggering the overall system reset when the system is abnormal, which can improve the system work efficiency.

[0049] It should be noted that the exception handling method of the present application is aimed at system software failures, not system exceptions caused by hardware device failures.

[0050] like Figure 8 As shown, the embodiment of the present application further provides a control system, including: a main processor module 801, a monitoring module 802 and a plurality of unit modules 803, wherein the main processor module and the monitoring module are connected via a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels; The monitoring module 802 is used to determine whether there is a communication abnormality between the main processor module and the unit module in the system based on the monitoring signal; The main processor module 801 is used to send a preset level signal to the monitoring module if a communication abnormality occurs in the unit module; The monitoring module 802 is further used to read and analyze the preset level signal, and control the unit module with communication abnormality to reset or power on and off based on the received abnormal module identification information.

[0051] Specifically, the first signal line and the second signal line are the signal line A and the signal line B in any of the aforementioned method embodiments, and the monitoring module includes a watchdog IC. In one embodiment, the control system can be a smart home control system, and can also be a control system for security equipment, which plays a role in protecting equipment that needs to run for a long time and prevent shutdown.

[0052] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the system exception handling method provided in any of the aforementioned method embodiments are implemented.

[0053] The device / system embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0054] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0055] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0056] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for handling system exceptions, the system comprising a main processor, a monitoring chip and a plurality of unit modules, characterized in that: The method comprises: Determine whether communication abnormality occurs between the main processor and the unit module in the system; If the unit module has a communication anomaly, the main processor sends a preset level signal to the monitoring chip, wherein the main processor and the monitoring chip are connected via a first signal line and a second signal line, and the first signal line and the second signal line have two states of high and low levels; The monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication abnormality to perform reset or power on / off operation.

2. The method according to claim 1, characterized in that If the unit module has a communication anomaly, the main processor sends a preset level signal to the monitoring chip, including: If there is only one unit module with abnormal communication, the main processor controls the first signal line and the second signal line to output a level signal. Wherein, the level signal includes a first signal and a second signal; The first signal is the first signal line and the second signal line, one of which outputs a high level and the other outputs a low level, and the opposite levels are maintained for a first preset time; The second signal is that after the output of the first signal is completed, the first signal line and the second signal line both maintain a low level output and last for a second preset time.

3. The method according to claim 1, characterized in that If the unit module has a communication anomaly, the main processor sends a preset level signal to the monitoring chip, and further includes: If there are more than one unit modules with abnormal communication, count the number N of abnormal unit modules detected by the main processor; The main processor controls the first signal line and the second signal line to output N level signals in sequence, Wherein, the level signal includes a first signal and a second signal; The first signal is the first signal line and the second signal line, one of which outputs a high level and the other outputs a low level, and the opposite levels are maintained for a first preset time; The second signal is that after the output of the first signal is completed, the first signal line and the second signal line both maintain a low level output and last for a second preset time.

4. The method according to any one of claims 1 to 3, characterized in that: The monitoring chip reads and analyzes the preset level signal, and based on the received abnormal module identification information, controls the unit module with communication abnormality to perform reset or power-on and power-off operations, including: The monitoring chip determines the target module based on the signal analysis information and the abnormal module identification information; Determine whether the target module has a reset port; If there is a reset port, the monitoring chip controls the reset port of the target module to reset the target module; If there is no reset port, the monitoring chip controls the power supply port of the target module to power off the target module, and then controls the target module to power on after the power-off time is a third preset time.

5. The method according to claim 4, characterized in that After the monitoring chip reads and analyzes the preset level signal and controls the unit module with communication abnormality to perform reset or power-on / off operation based on the received abnormal module identification information, the method further includes: Monitoring whether the target module resumes normal communication within a fourth preset time, wherein the fourth preset time is counted from the time when the monitoring chip receives the preset level signal; If not, return to the step of executing the main processor sending a preset level signal to the monitoring chip, and the monitoring chip reading and parsing the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to reset or power on and off.

6. The method according to claim 5, characterized in that The step of returning to execute the monitoring chip to read and parse the preset level signal, and based on the received abnormal module identification information, controlling the unit module with communication abnormality to reset or power on and off, includes: If the target module has a reset port, and the monitoring chip can control both the reset port and the power port of the target module, the monitoring chip controls the power port of the target module to power off the target module, and then controls the target module to power on after a third preset time has passed since the power-off.

7. The method according to claim 5, characterized in that After returning to the step of executing the main processor sending a preset level signal to the monitoring chip, and the monitoring chip reading and parsing the preset level signal, and controlling the unit module with communication abnormality to reset or power on and off based on the received abnormal module identification information, the method further includes: If the target module has not yet restored normal communication, the monitoring chip, after reading and parsing the preset level signal, continuously controls the power supply port of the target module to power on and off, so that the target module can restore normal communication.

8. The method according to claim 1, characterized in that: The determining whether communication abnormality occurs between the main processor and the unit module in the system includes: If the first signal line or the second signal line outputs a high level or a low level and the duration is greater than a fourth preset time, it is determined that a communication abnormality occurs in the main processor; After determining whether communication abnormality occurs between the main processor and the unit module in the system, the method further includes: If the main processor has a communication anomaly, the monitoring chip controls the reset port of the main processor to reset it; Determine whether the first signal line and the second signal line both output a high level or a low level, and the duration is greater than a fourth preset time; If yes, the monitoring chip controls the power supply port of the main processor to power it off, and after the power-off period is a fourth preset time, controls the power supply port of the main processor to power it on; Determine again whether the first signal line and the second signal line both output a high level or a low level, and the duration is greater than a fourth preset time; If so, the monitoring chip controls the power supply port of the main processor and the power supply ports of all unit modules to power off all of them, and after the fourth preset time, controls the power supply port of the main processor and the power supply ports of all unit modules to power on all of them.

9. A control system, characterized in that: The control system includes a main processor module, a monitoring module and a plurality of unit modules, wherein the main processor module and the monitoring module are connected via a first signal line and a second signal line, wherein the first signal line and the second signal line have two states of high and low levels; The monitoring module is used to determine whether communication abnormalities occur between the main processor module and the unit module in the system based on the monitoring signal; The main processor module is used to send a preset level signal to the monitoring module if a communication abnormality occurs in the unit module; The monitoring module is further used to read and analyze the preset level signal, and control the unit module with communication abnormality to perform reset or power on and off operations based on the received abnormal module identification information.

10. A storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of claims 1 to 8.

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