SoC bus data transmission method and device

Abstract

The invention discloses an SoC bus data transmission method, which comprises the following steps that: a first central processing unit transmits a first address of a write request to a virtual response interface circuit through a write address channel, and the virtual response interface circuit records address information of the first address; the virtual response interface circuit returns a virtual bvalid signal to the first central processing unit and marks the virtual response interface circuit as a busy state, and meanwhile, the first address is transmitted to the external memory by the virtual response interface circuit through a write address channel; the virtual response interface circuit reads the address information of the second address of the read request in the first primary cache unit through the read address channel, compares the address information with the address information of the first address recorded by the virtual response interface circuit, and blocks the operation request corresponding to the second address if the two address information have correlation; and if the first address and the second address do not have correlation, continuing to execute the operation request corresponding to the second address, so that the transmission efficiency and the system performance are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of access to a high-speed expansion bus (Advanced eXtensible Interface, AXI), and in particular to a SoC bus data transmission method and device. Background Art

[0002] The AXI bus is a high-performance, high-bandwidth, and low-latency on-chip bus. The transmission channels used for its address / control information and data transmission are separated, and it has independent read and write data channels. Based on the read and write channels, five independent transaction channels are defined, namely read address, read data, write address, write data, and write response. Figure 1 As shown, when data is transmitted based on the AXI bus, it is carried out between the master device and the slave device, and different types of transmission channels are established in the master device and the slave device respectively to realize reading and writing data. However, when performing read or write operations, the response transmission path is long. At the same time, if the problem of address correlation occurs, the host will be blocked for a long time, the delay is large, and the transmission efficiency becomes low.

[0003] For example, Figure 1 As shown, in the existing AXI bus structure, the cache attribute corresponding to a certain memory area in the synchronous dynamic random access memory is configured as a pass-through mode, that is, this memory is not cached by the cache, and there is no cache acceleration function for write-after-reading in the devices and buses other than the cache. If at this time, the first central processing unit initiates a write-after-reading operation on the address A in this memory, the write operation transmission path is divided into two steps: write operation and slave response operation; the CPU first transmits on the bus, first, write operation: ①→②→③→④→⑦→⑧; secondly, the slave response operation is: ⑧ After updating the write data to the synchronous dynamic random access memory, pull bvalid high and transmit it back to the first central processing unit according to the reverse process of the above write transmission (⑧→⑦→④→③→②→①), the first central processing unit can know that the write operation has been completed; then, the first central processing unit can initiate a read request for address A. This address-related write-after-read operation of the first central processing unit will cause the transmission path to be very long. Assume that during the transmission process, the priority of path ⑦ is occupied by devices ⑤ or ⑥. Even if there is a write cache at ⑧ that can accept the write data of ④, ⑧ fails to return a response signal in time indicating that the bvalid transmission write operation is completed, which results in the read request being blocked, affecting the transmission efficiency.

[0004] In addition, Figure 1In the system architecture and bus schematic diagram, the first central processing unit and the second central processing unit share a second-level cache unit and have an independent first-level cache unit. The consistency of L1 is managed by the cache consistency management module, and the above-mentioned CACHE adopts a write-back structure. Assume that the address A and the address B in the synchronous dynamic random access memory are in the same cache line of the CACHE, the address A is used by the first central processing unit, and the address B is used by the second central processing unit.

[0005] First, the first central processing unit reads A and modifies the value of A. After completing the above operations, A is cached in the first-level cache unit. Later, due to other accesses of the first central processing unit to non-B addresses, a CACHE replacement operation is generated, and A is written back to the synchronous dynamic random access memory. During the time from the start of the write-back operation to the completion of the write-back operation, the second central processing unit initiates an access request for the B address. Since A and B belong to the same cache line, the cache consistency management module must block the request signal for the B address initiated by the second-level cache unit until the write-back operation of the A address is completed.

[0006] The write-back operation transmission path of address A is (②→③→④→⑦→⑧). After ⑧ updates the write-back operation of address A to the synchronous dynamic random access memory, it pulls bvalid high and transmits it back to the first-level cache unit according to the reverse process of the above write transmission (⑧→⑦→④→③→②). After that, the cache consistency listener releases the cache line of address A, and then the second-level cache unit can initiate requests for other addresses. Then other addresses complete the request operations of other addresses in the transmission order of (⑩→③→④→⑦→⑧, ⑧→⑦→④→③→⑩). If, as described in Example 1, ⑧ fails to return the response signal of the completion of the bvalid transmission write operation in time, the read requests of other addresses will be blocked, affecting the transmission efficiency. Summary of the invention

[0007] Based on the above situation, the main purpose of the present invention is to provide a SoC bus data transmission method and device, which can effectively reduce the delay of the bus transmission path, improve the bus transmission efficiency, and improve the system performance.

[0008] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0009] A SoC bus data transmission method, comprising the steps of:

[0010] S100, the first central processing unit transmits the first address of the write request to the virtual response interface circuit through the write address channel, and the virtual response interface circuit records the address information of the first address;

[0011] S200, the virtual response interface circuit returns a virtual bvalid signal to the first central processing unit and marks the virtual response interface circuit as being in a busy state. Meanwhile, the first address is continuously transmitted from the virtual response interface circuit to the external memory through the write address channel.

[0012] S300, the virtual response interface circuit reads the address information of the second address of the read request in the first level cache unit through the read address channel, and compares it with the address information of the first address recorded by the virtual response interface circuit. If the two are correlated, the operation request corresponding to the second address is blocked until the operation of the first address recorded by the virtual response interface circuit is completed. If the two are not correlated, the operation request corresponding to the second address continues to be executed.

[0013] Preferably, the step S100 comprises: the first central processing unit transmits the first address of the write request to the virtual response interface circuit through the write address channel in sequence via the first level 1 cache unit, the cache consistency monitoring unit and the level 2 cache unit.

[0014] Preferably, the step S100 further includes:

[0015] If the first level cache unit is in pass-through mode, the first central processing unit backs up the address information of the first address, and before the write operation of the first address is completed, the first central processing unit cannot initiate an operation request of the first address;

[0016] If the first-level cache unit is a write-back structure, the first-level cache unit backs up the address information of the first address. Before the write operation of the first address is completed, the cache consistency management module cannot initiate an operation request for the first address and the same cache line as the first address. The cache consistency management module includes a first-level cache unit and a cache consistency monitoring unit.

[0017] Preferably, the first address in step S200 is continuously transmitted from the virtual response interface circuit to the external memory through the first address channel, including: the first address is transmitted to the external memory through a bus interconnection circuit.

[0018] Preferably, the correlation means that the address information of the second address is the same as the address information of the first address or both belong to the same cache line of the first level cache unit.

[0019] Preferably, the external memory comprises a synchronous dynamic random access memory.

[0020] Preferably, when the operation request of the first address is completed, the external memory returns a true bvalid signal to the virtual response interface circuit to clear the address information of the first address recorded by the virtual response interface circuit.

[0021] Preferably, if the address information of all addresses recorded by the virtual response interface circuit is cleared, the busy state of the virtual response interface circuit is cleared.

[0022] Preferably, when the SoC bus receives a signal from the host device that the first central processing unit has read the latest data written into the external memory, the first central processing unit initiates a bus synchronization instruction, and the bus synchronization is completed only when the busy state of the virtual response interface circuit is cleared.

[0023] Preferably, when the operation of the first address is completed, the updated data of the first address is cached in the first level cache unit, and if the first central processing unit generates other address access requests, the updated data of the first address is written back to the external memory.

[0024] Preferably, when the second central processing unit initiates a data access request for the first address, it first initiates a read address request for the first address to the first first-level cache unit. If the first address is not read in the first first-level cache unit, the second central processing unit initiates a read request for the first address to the external memory.

[0025] Preferably, the second central processing unit initiates a read address request of the first address to the first first-level cache unit via the second first-level cache unit and the cache consistency monitoring unit.

[0026] Preferably, the second central processing unit initiates a read request for the first address to the external memory via the second first-level cache unit, the cache consistency monitoring unit, the second-level cache unit, the virtual response interface circuit, and the bus interconnection circuit.

[0027] Preferably, in the process of writing the updated data of the first address back to the external memory, if the second central processing unit initiates an access request, it is determined whether the address of the access request is the same as the first address or belongs to the same cache line. If so, the access request initiated by the second central processing unit is blocked until the virtual response interface circuit returns a virtual bvalid signal; otherwise, the access request continues to be transmitted to the external memory.

[0028] Preferably, when the external storage area returns a true bvalid signal, the blocked access request continues to transmit the access request to the external memory.

[0029] The present invention also provides a computer-readable storage medium, wherein the storage medium stores a program, wherein the program is used to be executed to implement the SoC bus data transmission method according to the present invention.

[0030] The present invention also provides a SoC chip, including a processor and a memory, wherein a calculation program is stored in the memory, and the processor can execute the calculation program to implement the SoC bus data transmission method of the present invention.

[0031] The present invention also provides a SoC bus data transmission device, comprising a first central processing unit, a virtual response interface circuit unit and a first level 1 cache unit.

[0032] The first central processing unit is used to transmit the first address of the write request to the virtual response interface circuit through the write address channel;

[0033] The virtual response interface circuit unit is used to record the address information of the first address, return a virtual bvalid signal to the first central processing unit, and mark the virtual response interface circuit as busy. At the same time, the virtual response interface circuit continues to transmit the first address to the external memory through the write address channel.

[0034] The first level cache unit is used to store address information of a second address of a read request;

[0035] The virtual response interface circuit unit is also used to read the address information of the second address through the read address channel, and compare it with the address information of the first address recorded by the virtual response interface circuit. If the two are correlated, the operation request corresponding to the second address is blocked until the operation of the first address recorded by the virtual response interface circuit is completed. If the two are not correlated, the operation request corresponding to the second address continues to be executed.

[0036] Preferably, it is characterized in that the device also includes a cache consistency monitoring unit and a secondary cache unit, and the first central processing unit is used to transmit the first address of the write request to the virtual response interface circuit unit through the write address channel in sequence through the first primary cache unit, the cache consistency monitoring unit and the secondary cache unit.

[0037] Preferably, if the first level cache unit is in pass-through mode, the first central processing unit backs up the address information of the first address, and before the write operation of the first address is completed, the first central processing unit cannot initiate an operation request of the first address;

[0038] If the first-level cache unit is a write-back structure, the first-level cache unit backs up the address information of the first address. Before the write operation of the first address is completed, the cache consistency management module cannot initiate an operation request for the first address and the same cache line as the first address. The cache consistency management module includes a first-level cache unit and a cache consistency monitoring unit.

[0039] Preferably, the virtual response interface circuit continues to transmit the first address to the external memory through the write address channel, including: transmitting the first address to the external memory through a bus interconnection circuit.

[0040] Preferably, the correlation means that the address information of the second address is the same as the address information of the first address or both belong to the same cache line of the first level cache unit.

[0041] Preferably, the external memory comprises a synchronous dynamic random access memory.

[0042] Preferably, when the operation request of the first address is completed, the external memory returns a true bvalid signal to the virtual response interface circuit unit to clear the address information of the first address recorded by the virtual response interface circuit unit.

[0043] Preferably, if the address information of all addresses recorded by the virtual response interface circuit is cleared, the busy state of the virtual response interface circuit is cleared.

[0044] Preferably, when the SoC bus receives a signal from the host device that the first central processing unit has read the latest data written into the external memory, the first central processing unit initiates a bus synchronization instruction, and the bus synchronization is completed only when the busy state of the virtual response interface circuit unit is cleared.

[0045] Preferably, when the operation of the first address is completed, the updated data of the first address is cached in the first level cache unit, and if the first central processing unit generates other address access requests, the updated data of the first address is written back to the external memory.

[0046] Preferably, the device further comprises two central processing units,

[0047] When the second central processing unit initiates a data access request for the first address, it first initiates a read address request for the first address to the first first-level cache unit. If the first address is not read in the first first-level cache unit, the second central processing unit initiates a read request for the first address to the external memory.

[0048] Preferably, the device further comprises a second first-level cache unit, and the second central processing unit initiates a read address request of the first address to the first first-level cache unit via the second first-level cache unit and the cache consistency monitoring unit.

[0049] Preferably, the second central processing unit initiates a read request for the first address to the external memory via the second first-level cache unit, the cache consistency monitoring unit, the second-level cache unit, the virtual response interface circuit unit, and the bus interconnection circuit.

[0050] Preferably, in the process of writing the updated data of the first address back to the external memory, if the second central processing unit initiates an access request, it is determined whether the address of the access request is the same as the first address or belongs to the same cache line. If so, the access request initiated by the second central processing unit is blocked until the virtual response interface circuit unit returns a virtual bvalid signal; otherwise, the access request continues to be transmitted to the external memory.

[0051] Preferably, when the external storage area returns a true bvalid signal, the blocked access request continues to transmit the access request to the external memory.

[0052] The technical solution of the present application sets a "virtual response interface circuit" on the operation request transmission link, newly defines the meaning and function of the virtual bvalid signal, replaces the real bvalid signal that originally needs to be returned by the external memory with the virtual bvalid signal returned by the "virtual response interface circuit", extracts and releases the previous-level request path, and allows subsequent requests to be transmitted to the next-level bus node in advance, effectively reducing the delay of the bus transmission path, improving the bus transmission efficiency, and improving system performance.

[0053] Other beneficial effects of the present invention will be explained in the specific implementation manner through the introduction of specific technical features and technical solutions. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The preferred implementation of the SoC bus data transmission method of the present invention will be described below with reference to the accompanying drawings.

[0055] Figure 1 A schematic diagram of the AXI bus system architecture in the prior art;

[0056] Figure 2 A flow chart of a SoC bus data transmission method according to a preferred embodiment of the present invention;

[0057] Figure 3 The figure is a schematic diagram of a SoC system bus architecture implemented according to the technical solution of the present invention. DETAILED DESCRIPTION

[0058] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. In order to avoid confusing the essence of the present invention, known methods, processes, procedures, and components are not described in detail.

[0059] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0060] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0061] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0062] Figure 2 A flow chart of a SoC bus data transmission method according to a preferred embodiment of the present invention includes the following steps:

[0063] S100, the first central processing unit transmits the first address of the write request to the virtual response interface circuit through the write address channel, and the virtual response interface circuit records the address information of the first address; wherein, the first central processing unit usually refers to the CPU in the SoC chip, and the virtual response interface circuit is a digital circuit innovatively designed in this case.

[0064] S200, the virtual response interface circuit returns a virtual bvalid signal to the first central processing unit and marks the virtual response interface circuit as busy. At the same time, the first address continues to be transmitted from the virtual response interface circuit to the external memory through the write address channel. In conventional technology, the external memory returns a bvalid signal to the central processing unit as a signal that the write operation is completed. In this solution, the virtual response interface circuit first returns a virtual bvalid signal to extract and release the previous request path, so that subsequent requests can be transmitted to the next bus node in advance.

[0065] S300, the virtual response interface circuit reads the address information of the second address of the read request in the first level cache unit through the read address channel, and compares it with the address information of the first address recorded by the virtual response interface circuit. If the two are correlated, the operation request corresponding to the second address is blocked until the operation of the first address recorded by the virtual response interface circuit is completed. If the two are not correlated, the operation request corresponding to the second address continues to be executed. In the present application, blocking refers to suspending a certain operation request without transmitting it to the subsequent circuit, for example, suspending the operation request corresponding to the second address and not transmitting the operation request to the subsequent circuit.

[0066] The technical solution of the present application sets a "virtual response interface circuit" on the operation request transmission link, newly defines the meaning and function of the virtual bvalid signal, replaces the real bvalid signal that originally needs to be returned by the external memory with the virtual bvalid signal returned by the "virtual response interface circuit", extracts and releases the previous-level request path, and allows subsequent requests to be transmitted to the next-level bus node in advance, effectively reducing the delay of the bus transmission path, improving the bus transmission efficiency, and improving system performance.

[0067] The present solution is explained in the context of the AXI bus protocol, but is not limited to the AXI bus protocol. Any bus protocol that uses a write completion feedback mechanism (similar to the bvalid signal convention of the AXI protocol), such as ACE, CHI and other protocols, is applicable to the method of the present invention.

[0068] In a preferred embodiment, the step S100 includes: the first central processing unit transmits the first address of the write request to the virtual response interface circuit through the first level cache unit, the cache consistency monitoring unit and the level 2 cache unit in sequence through the write address channel. Among them, the first level cache unit is in the level 1 cache, and the level 1 cache may also include a second level cache unit, a third level cache unit, etc. The cache consistency monitoring unit is used to manage the consistency of each cache unit in the level 1 cache. For example, when the level 1 cache is in a write-back structure, the cache consistency monitoring unit will detect the correlation between the write address and the read address. If the two are correlated, the cache consistency monitoring unit will generate a blocking signal. When the previous operation request is completed, the cache consistency monitoring unit will generate a signal to release the blocking.

[0069] In a preferred embodiment, the step S100 also includes: if the first level cache unit is in a pass-through mode, the first central processing unit backs up the address information of the first address, and before the write operation of the first address is completed, the first central processing unit cannot initiate an operation request for the first address; if the first level cache unit is a write-back structure, the first level cache unit backs up the address information of the first address, and before the write operation of the first address is completed, the cache consistency management module cannot initiate an operation request for the first address and the same cache line as the first address, and the cache consistency management module includes a first level cache unit and a cache consistency monitoring unit. The pass-through mode means that the data will not be written into the cache, but directly to the external memory through the transmission link, and the write-back structure means that the cache will write itself first after receiving the data, and when new data comes in, the first written will be written to the external memory first.

[0070] In a preferred embodiment, the first address in step S200 is further transmitted from the virtual response interface circuit to the external memory through the first address channel, including: the first address is transmitted to the external memory through a bus interconnection circuit. The bus interconnection circuit may be, for example, an AXI multi-master multi-slave interconnection circuit.

[0071] In a preferred embodiment, the correlation means that the address information of the second address is the same as the address information of the first address or both belong to the same cache line of the first level 1 cache unit. Using read-write correlation check, memory requests with address correlation can be sorted.

[0072] In a preferred embodiment, the external memory includes a synchronous dynamic random access memory, and may also be other types of memory, which is not limited by the present invention.

[0073] In a preferred embodiment, when the operation request of the first address is completed, the external memory returns a true bvalid signal to the virtual response interface circuit to clear the address information of the first address recorded by the virtual response interface circuit.

[0074] In a preferred implementation, if the address information of all addresses recorded by the virtual response interface circuit is cleared, the busy state of the virtual response interface circuit is cleared.

[0075] In a preferred embodiment, when the SoC bus receives a data received by the host device reading the data most recently written to the external memory by the first central processing unit, the first central processing unit initiates a bus synchronization instruction, and the bus synchronization is not completed until the busy state of the virtual response interface circuit is cleared.

[0076] In a preferred embodiment, when the operation of the first address is completed, the updated data of the first address is cached in the first level cache unit. If the first central processing unit generates other address access requests, the updated data of the first address is written back to the external memory.

[0077] In a preferred embodiment, when the second central processing unit initiates a data access request for the first address, it first initiates a read address request for the first address to the first first-level cache unit. If the first address is not read in the first first-level cache unit, the second central processing unit initiates a read request for the first address to the external memory.

[0078] In a preferred embodiment, the second central processing unit initiates a read address request of the first address to the first first-level cache unit via the second first-level cache unit and the cache consistency monitoring unit.

[0079] In a preferred embodiment, the second central processing unit initiates a read request for the first address to the external memory via the second level 1 cache unit, the cache consistency monitoring unit, the level 2 cache unit, the virtual response interface circuit, and the bus interconnection circuit.

[0080] In a preferred embodiment, during the process of writing the updated data of the first address back to the external memory, if the second central processing unit initiates an access request, it is determined whether the address of the access request is the same as the first address or belongs to the same cache line. If so, the access request initiated by the second central processing unit is blocked until the virtual response interface circuit returns a virtual bvalid signal; otherwise, the access request continues to be transmitted to the external memory.

[0081] In a preferred embodiment, when the external memory area returns a true bvalid signal, the blocked access request continues to transmit the access request to the external memory.

[0082] Figure 3 It is a schematic diagram of the SoC system bus architecture implemented according to the technical solution of the present invention, including a first central processing unit, a second central processing unit, a first level cache unit, a second level cache unit, a cache consistency monitoring module, a second level cache unit, a graphics processor, a neural network processing unit, a virtual response interface module, an AXI multi-master and multi-slave interconnection circuit, and a synchronous dynamic random access memory.

[0083] In the pass-through mode, the first central processing unit transmits the A address in sequence through the write address channel. When the A address passes through the first level cache unit, the cache consistency monitoring module, and the second level cache unit to reach the virtual response module, the virtual response interface module sends a virtual bvalid signal to the first central processing unit, which passes through the second level cache unit, the cache consistency monitoring module, and the first level cache unit to reach the first central processing unit. At the same time, the A address continues to be transmitted synchronously through the write address channel, and reaches the synchronous dynamic random access memory after passing through the AXI multi-master multi-slave interconnection circuit.

[0084] The reference transmission path for address A is:

[0085] The virtual Bvalid signal transmission path is:

[0086] The virtual response interface module records the address information of the A address of the current operation, and at the same time, the virtual response interface module is marked as busy after returning the virtual bvalid signal, indicating that the current operation has not been completed. In addition, when the first-level cache unit is in pass-through mode, the write request operation of the A address is initiated by the first central processing unit, and the information of the current A address is backed up in the first central processing unit. Before the write operation of the A address is completed, the first central processing unit cannot initiate a read request of the A address. When the first-level cache unit adopts a write-back structure, the write request operation of the A address is triggered by the write-back operation generated by the replacement of the cache line of the first-level cache unit. The information of the current A address is backed up in the first-level cache unit. Before the write operation of the A address is completed, the cache consistency management module cannot initiate a read and write request of the A address and the same cache line of the A address.

[0087] Next, the virtual response interface module reads the address of the first-level cache unit through the read address channel, and compares it with the A address obtained in the write address channel, that is, the A address recorded by the virtual response interface module, to see whether the address information of the two is relevant. If there is no correlation, the read address request or the write address request continues to be transmitted. If there is a correlation, it is blocked until the address information of the previous level is cleared. The real bvalid signal transmission reaches the virtual response interface module, indicating that the write address information operation is completed.

[0088] When any AXI master device ( Figure 3 When the graphics processor or neural network processing unit needs to obtain the latest data written to SDRAM by the central processing unit, the central processing unit initiates a bus synchronization instruction; at this time, the synchronization operation is completed only after the busy signal generated by the virtual response interface module is cleared.

[0089] When the first central processing unit reads address A in the synchronous dynamic random access memory and modifies it, the new data at address A is cached in the first-level cache unit. Later, when the first central processing unit generates other address content when processing other access tasks, it is also stored in the first-level cache unit, generating a cache line replacement operation, so that the new data at address A needs to be written back to the synchronous dynamic random access memory (SDRAM). At this time, when the second central processing unit needs to obtain address A information, it first initiates a read address request for address A to the first-level cache unit. If address A is not read in the first-level cache unit (⑨→⑩→③→②), the second central processing unit initiates a read request for address A to the synchronous dynamic random access memory. For the specific path, refer to

[0090] In the process of new data at address A being written back to the synchronous dynamic random access memory, if the second central processing unit initiates an access (read address) request to other addresses, when the other addresses and address A belong to the same cache line, the cache consistency management module will block the second-level cache unit from initiating a (read address) request signal to the synchronous dynamic random access memory for other addresses until address A receives a virtual bvalid signal returned by the virtual response interface module. For ease of understanding, the receipt of the virtual bvalid signal refers to:

[0091] (1) When in pass-through mode, the virtual response interface module returns a virtual bvalid signal to the first central processing unit through the write response channel;

[0092] (2) When in write-back mode, the virtual response interface module returns a virtual bvalid signal to the first level cache unit through the write response channel.

[0093] At this time, the write-back operation transmission path of address A is After that, the cache consistency management module can unblock the second-level cache unit from initiating (read address) requests for other addresses, which reduces two paths ⑦ and ⑧ in terms of timing compared to the traditional solution.

[0094] The virtual response interface module takes over the subsequent transmission of address A (→⑦→⑧) until address A reaches SDRAM. The subsequent transmission of address A, the unblocking of the cache consistency management module, and the (read address) request initiated by the second-level cache unit are carried out simultaneously. Then, other addresses are sent as The transmission sequence is transmitted to When the read address request arrives, it is controlled by the read-write correlation check mechanism of the virtual response interface module. When the address tag of the A address transmission of the virtual response interface module is cleared, that is, the transmission of the A address (→⑦→⑧) has been completed, and the subsequent transmission of the (read address) request of other addresses (→⑦→⑧) will not be blocked. When the address A is transmitted, the address tag of the address A is not cleared, that is, the transmission of (→⑦→⑧) is not completed, and the virtual response interface module blocks the subsequent transmission of (→⑦→⑧) of the address that is related to the address A (the same address as A or the same cache line as A). When the address A reaches the SDRAM, the SDRAM returns the real bvalid to the virtual response interface module, and the virtual response interface module clears the tag of the address A, and other addresses can initiate the transmission of (→⑦→⑧). Compared with the traditional solution, under the blocking solution, the (read address) requests of other addresses can be transmitted to the node in advance. , there is no need to wait until the SDRAM returns a true bvalid signal before initiating a request, reducing the transmission path delay of ⑩ and ③.

[0095] The busy signal is provided through the virtual response interface module and used in conjunction with the synchronization instruction of the first central processing unit. When the busy signal is cleared, it means that the real bvalid signal transmission is completed (the real Bvalid signal only needs to be transmitted to the virtual response interface module), that is, the original definition state of the traditional solution is reached. First initiate the synchronization instruction, and then notify the GPU (node ​​⑤) to access the address operated by the above-mentioned first central processing unit. Thereby, the following problem can be solved: when the first central processing unit receives the bvalid signal returned by the virtual response interface module, it cannot guarantee that the "write address" of the first central processing unit is transmitted to node ⑧. If the GPU (node ​​⑤) is notified to access the address written to the SDRAM by the above-mentioned first central processing unit at this time, data errors may occur.

[0096] The present invention also discloses a computer-readable storage medium, wherein the storage medium stores a program, wherein the program is used to be executed to implement the SoC bus data transmission method according to the present invention.

[0097] The present invention also discloses a SoC chip, comprising a processor and a memory, wherein a calculation program is stored in the memory, and the processor can execute the calculation program to implement the SoC bus data transmission method as described in the present invention.

[0098] The present invention also discloses a SoC bus data transmission device, comprising a first central processing unit, a virtual response interface circuit unit and a first level 1 cache unit.

[0099] The first central processing unit is used to transmit the first address of the write request to the virtual response interface circuit through the write address channel;

[0100] The virtual response interface circuit unit is used to record the address information of the first address, return a virtual bvalid signal to the first central processing unit, and mark the virtual response interface circuit as busy. At the same time, the virtual response interface circuit continues to transmit the first address to the external memory through the write address channel.

[0101] The first level cache unit is used to store address information of a second address of a read request;

[0102] The virtual response interface circuit unit is also used to read the address information of the second address through the read address channel, and compare it with the address information of the first address recorded by the virtual response interface circuit. If the two are correlated, the operation request corresponding to the second address is blocked until the operation of the first address recorded by the virtual response interface circuit is completed. If the two are not correlated, the operation request corresponding to the second address continues to be executed.

[0103] In a preferred embodiment, the device also includes a cache consistency monitoring unit and a secondary cache unit, and the first central processing unit is used to transmit the first address of the write request to the virtual response interface circuit unit through the write address channel in sequence through the first primary cache unit, the cache consistency monitoring unit and the secondary cache unit.

[0104] In a preferred embodiment, if the first-level cache unit is in a pass-through mode, the first central processing unit backs up the address information of the first address, and before the write operation of the first address is completed, the first central processing unit cannot initiate an operation request for the first address; if the first-level cache unit is a write-back structure, the first-level cache unit backs up the address information of the first address, and before the write operation of the first address is completed, the cache consistency management module cannot initiate an operation request for the first address and the same cache line as the first address, and the cache consistency management module includes a first-level cache unit and a cache consistency monitoring unit.

[0105] In a preferred embodiment, the virtual response interface circuit continues to transmit the first address to the external memory through the write address channel, including: transmitting the first address to the external memory via a bus interconnection circuit.

[0106] In a preferred implementation, the correlation means that the address information of the second address is the same as the address information of the first address or both belong to the same cache line of the first level cache unit.

[0107] In a preferred embodiment, the external memory includes a synchronous dynamic random access memory.

[0108] In a preferred embodiment, when the operation request of the first address is completed, the external memory returns a true bvalid signal to the virtual response interface circuit unit to clear the address information of the first address recorded by the virtual response interface circuit unit.

[0109] In a preferred implementation, if the address information of all addresses recorded by the virtual response interface circuit is cleared, the busy state of the virtual response interface circuit is cleared.

[0110] In a preferred embodiment, when the SoC bus receives a data received by the host device reading the data most recently written to the external memory by the first central processing unit, the first central processing unit initiates a bus synchronization instruction, and the bus synchronization is not completed until the busy state of the virtual response interface circuit unit is cleared.

[0111] In a preferred embodiment, when the operation of the first address is completed, the updated data of the first address is cached in the first level cache unit. If the first central processing unit generates other address access requests, the updated data of the first address is written back to the external memory.

[0112] In a preferred embodiment, the device also includes two central processing units. When the second central processing unit initiates a data access request for the first address, it first initiates a read address request for the first address to the first first-level cache unit. If the first address is not read in the first first-level cache unit, the second central processing unit initiates a read request for the first address to the external memory.

[0113] In a preferred embodiment, the device further includes a second level one cache unit, and the second central processing unit initiates a read address request of the first address to the first level one cache unit via the second level one cache unit and the cache consistency monitoring unit.

[0114] In a preferred embodiment, the second central processing unit initiates a read request for the first address to the external memory via the second first-level cache unit, the cache consistency monitoring unit, the second-level cache unit, the virtual response interface circuit unit, and the bus interconnection circuit.

[0115] In a preferred embodiment, in the process of writing the updated data of the first address back to the external memory, if the second central processing unit initiates an access request, it is determined whether the address of the access request is the same as the first address or belongs to the same cache line. If so, the access request initiated by the second central processing unit is blocked until the virtual response interface circuit unit returns a virtual bvalid signal; otherwise, the access request continues to be transmitted to the external memory.

[0116] In a preferred embodiment, when the external memory area returns a true bvalid signal, the blocked access request continues to transmit the access request to the external memory.

[0117] It will be appreciated by those skilled in the art that, under the premise of no conflict, the above-mentioned preferred solutions can be freely combined and superimposed. Among them, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings, for example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. The numbering of each step in this article is only for the convenience of description and reference, and is not used to limit the order of execution. The specific execution order is determined by the technology itself, and those skilled in the art can determine various allowable and reasonable orders based on the technology itself.

[0118] It should be noted that the use of step numbers (letters or numbers) to refer to certain specific method steps in the present invention is only for the purpose of convenience and brevity of description, and is by no means intended to limit the order of these method steps by letters or numbers. Those skilled in the art will understand that the order of the relevant method steps should be determined by the technology itself and should not be inappropriately limited by the existence of step numbers. Those skilled in the art can determine various permissible and reasonable step orders based on the technology itself.

[0119] Those skilled in the art will appreciate that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0120] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present invention, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will be included in the scope of the claims of the present invention.

Claims

1. A SoC bus data transmission method, characterized in that: Includes steps: S100, the first central processing unit transmits the first address of the write request to the virtual response interface circuit through the write address channel, and the virtual response interface circuit records the address information of the first address; S200, the virtual response interface circuit returns a virtual bvalid signal to the first central processing unit and marks the virtual response interface circuit as being in a busy state. Meanwhile, the first address is continuously transmitted from the virtual response interface circuit to the external memory through the write address channel. S300, the virtual response interface circuit reads the address information of the second address of the read request in the first level cache unit through the read address channel, and compares it with the address information of the first address recorded by the virtual response interface circuit. If the two are correlated, the operation request corresponding to the second address is blocked until the operation of the first address recorded by the virtual response interface circuit is completed. If the two are not correlated, the operation request corresponding to the second address continues to be executed.

2. The SoC bus data transmission method according to claim 1, characterized in that: The step S100 includes: the first central processing unit transmits the first address of the write request to the virtual response interface circuit through the first level 1 cache unit, the cache consistency monitoring unit and the level 2 cache unit in sequence through the write address channel.

3. The SoC bus data transmission method according to claim 1, characterized in that: The step S100 further includes: If the first level cache unit is in pass-through mode, the first central processing unit backs up the address information of the first address, and before the write operation of the first address is completed, the first central processing unit cannot initiate an operation request of the first address; If the first-level cache unit is a write-back structure, the first-level cache unit backs up the address information of the first address. Before the write operation of the first address is completed, the cache consistency management module cannot initiate an operation request for the first address and the same cache line as the first address. The cache consistency management module includes a first-level cache unit and a cache consistency monitoring unit.

4. The SoC bus data transmission method according to claim 1, characterized in that: The first address in step S200 is continuously transmitted from the virtual response interface circuit to the external memory through the first address channel, including: the first address is transmitted to the external memory through a bus interconnection circuit.

5. The SoC bus data transmission method according to claim 1, characterized in that: The correlation means that the address information of the second address is the same as the address information of the first address or the two belong to the same cache line of the first level cache unit.

6. The SoC bus data transmission method according to claim 1, characterized in that: The external memory includes a synchronous dynamic random access memory.

7. The SoC bus data transmission method according to claim 1, characterized in that: When the operation request of the first address is completed, the external memory returns a true bvalid signal to the virtual response interface circuit to clear the address information of the first address recorded by the virtual response interface circuit.

8. The SoC bus data transmission method according to claim 7, characterized in that: If the address information of all addresses recorded by the virtual response interface circuit is cleared, the busy state of the virtual response interface circuit is cleared.

9. The SoC bus data transmission method according to claim 1, characterized in that: When the SoC bus receives data that the host device reads the data that the first central processing unit has recently written into the external memory, the first central processing unit initiates a bus synchronization instruction, and the bus synchronization is completed only when the busy state of the virtual response interface circuit is cleared.

10. The SoC bus data transmission method according to claim 1, characterized in that: When the operation of the first address is completed, the updated data of the first address is cached in the first level cache unit. If the first central processing unit generates other address access requests, the updated data of the first address is written back to the external memory.

11. The SoC bus data transmission method according to claim 10, characterized in that: When the second central processing unit initiates a data access request for the first address, it first initiates a read address request for the first address to the first first-level cache unit. If the first address is not read in the first first-level cache unit, the second central processing unit initiates a read request for the first address to the external memory.

12. The SoC bus data transmission method according to claim 11, characterized in that: The second central processing unit initiates a read address request of the first address to the first first-level cache unit via the second first-level cache unit and the cache consistency monitoring unit.

13. The SoC bus data transmission method according to claim 11, characterized in that: The second central processing unit initiates a read request for the first address to the external memory via the second first-level cache unit, the cache consistency monitoring unit, the second-level cache unit, the virtual response interface circuit, and the bus interconnection circuit.

14. The SoC bus data transmission method according to claim 11, characterized in that: During the process of writing the updated data of the first address back to the external memory, if the second central processing unit initiates an access request, it is determined whether the address of the access request is the same as the first address or belongs to the same cache line. If so, the access request initiated by the second central processing unit is blocked until the virtual response interface circuit returns a virtual bvalid signal; otherwise, the access request continues to be transmitted to the external memory.

15. The SoC bus data transmission method according to claim 14, characterized in that: When the external memory area returns a true bvalid signal, the blocked access request continues to transmit the access request to the external memory.

16. A computer-readable storage medium, characterized in that: The storage medium stores a program, wherein the program is executed to implement the SoC bus data transmission method according to any one of claims 1 to 5.

17. A SoC chip, comprising a processor and a memory, characterized in that: The memory stores a calculation program, and the processor can execute the calculation program to implement the SoC bus data transmission method as described in any one of claims 1-15.

18. A SoC bus data transmission device, characterized in that: It includes a first central processing unit, a virtual response interface circuit unit and a first level cache unit, The first central processing unit is used to transmit the first address of the write request to the virtual response interface circuit through the write address channel; The virtual response interface circuit unit is used to record the address information of the first address, return a virtual bvalid signal to the first central processing unit, and mark the virtual response interface circuit as busy. At the same time, the virtual response interface circuit continues to transmit the first address to the external memory through the write address channel. The first level cache unit is used to store address information of a second address of a read request; The virtual response interface circuit unit is also used to read the address information of the second address through the read address channel, and compare it with the address information of the first address recorded by the virtual response interface circuit. If the two are correlated, the operation request corresponding to the second address is blocked until the operation of the first address recorded by the virtual response interface circuit is completed. If the two are not correlated, the operation request corresponding to the second address continues to be executed.

19. The SoC bus data transmission device according to claim 18, characterized in that: The device also includes a cache consistency monitoring unit and a secondary cache unit. The first central processing unit is used to transmit the first address of the write request to the virtual response interface circuit unit through the write address channel in sequence through the first level 1 cache unit, the cache consistency monitoring unit and the level 2 cache unit.

20. The SoC bus data transmission device according to claim 18, characterized in that: If the first level cache unit is in pass-through mode, the first central processing unit backs up the address information of the first address, and before the write operation of the first address is completed, the first central processing unit cannot initiate an operation request of the first address; If the first-level cache unit is a write-back structure, the first-level cache unit backs up the address information of the first address. Before the write operation of the first address is completed, the cache consistency management module cannot initiate an operation request for the first address and the same cache line as the first address. The cache consistency management module includes a first-level cache unit and a cache consistency monitoring unit.

21. The SoC bus data transmission device according to claim 18, characterized in that: The virtual response interface circuit continues to transmit the first address to the external memory through the write address channel, including: the first address is transmitted to the external memory through a bus interconnection circuit.

22. The SoC bus data transmission device according to claim 18, characterized in that: The correlation means that the address information of the second address is the same as the address information of the first address or the two belong to the same cache line of the first level cache unit.

23. The SoC bus data transmission device according to claim 18, characterized in that: The external memory includes a synchronous dynamic random access memory.

24. The SoC bus data transmission device according to claim 18, characterized in that: When the operation request of the first address is completed, the external memory returns a true bvalid signal to the virtual response interface circuit unit to clear the address information of the first address recorded by the virtual response interface circuit unit.

25. The SoC bus data transmission device according to claim 24, characterized in that: If the address information of all addresses recorded by the virtual response interface circuit is cleared, the busy state of the virtual response interface circuit is cleared.

26. The SoC bus data transmission device according to claim 18, characterized in that: When the SoC bus receives data that the host device reads the data that the first central processing unit has recently written into the external memory, the first central processing unit initiates a bus synchronization instruction, and the bus synchronization is completed only when the busy state of the virtual response interface circuit unit is cleared.

27. The SoC bus data transmission device according to claim 18, characterized in that: When the operation of the first address is completed, the updated data of the first address is cached in the first level cache unit. If the first central processing unit generates other address access requests, the updated data of the first address is written back to the external memory.

28. The SoC bus data transmission device according to claim 27, characterized in that: The device also includes two central processing units, When the second central processing unit initiates a data access request for the first address, it first initiates a read address request for the first address to the first first-level cache unit. If the first address is not read in the first first-level cache unit, the second central processing unit initiates a read request for the first address to the external memory.

29. The SoC bus data transmission device according to claim 28, characterized in that: The device also includes a second level cache unit, The second central processing unit initiates a read address request of the first address to the first first-level cache unit via the second first-level cache unit and the cache consistency monitoring unit.

30. The SoC bus data transmission device according to claim 28, characterized in that: The second central processing unit initiates a read request for the first address to the external memory via the second first-level cache unit, the cache consistency monitoring unit, the second-level cache unit, the virtual response interface circuit unit, and the bus interconnection circuit.

31. The SoC bus data transmission device according to claim 28, characterized in that: During the process of writing the updated data of the first address back to the external memory, if the second central processing unit initiates an access request, it is determined whether the address of the access request is the same as the first address or belongs to the same cache line. If so, the access request initiated by the second central processing unit is blocked until the virtual response interface circuit unit returns a virtual bvalid signal; otherwise, the access request continues to be transmitted to the external memory.

32. The SoC bus data transmission device according to claim 31, characterized in that: When the external memory area returns a true bvalid signal, the blocked access request continues to transmit the access request to the external memory.

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