Data transmission method and device, upper computer and computer readable storage medium
By inserting the target signal in the data transmission, the problem of low data transmission efficiency caused by the upper computer waiting for the ACK signal is solved, and faster data transmission is achieved.
Patent Information
- Application Number
- CN202411136649.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-01-03
AI Technical Summary
During the chip testing and debugging process, the data transmission efficiency is low due to the limited amount of data that the upper computer can write to the chip at a time, and it is necessary to write multiple times and wait for the confirmation signal, which extends the data transmission time.
By dividing the data to be transmitted into a number of consecutive data and inserting target signals between two adjacent data, the emulator sends these data to the test chip to avoid waiting for the ACK signal, thereby improving data transmission efficiency.
It shortens the time for the upper computer to transmit data to the test chip, improves data transmission efficiency, and reduces the time for waiting for ACK signals. It is suitable for large data transmission scenarios.
Smart Images
Figure CN119248694A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of programmable logic devices, and in particular to a data transmission method, device, host computer and computer-readable storage medium. Background Art
[0002] Before the chip is used, the host computer can test and debug the chip through the simulator. In the process of testing and debugging the chip through the simulator, the host computer needs to send various data to the chip. However, since the amount of data that the host computer can write to the chip each time is limited, if the amount of data to be sent is large, it takes multiple times to write all the data to the chip. After the host computer writes data to the chip each time, it needs to wait for the chip to return an acknowledgment (Acknowledge, ACK) signal before continuing to write data, resulting in a long data transmission time, which reduces the data transmission efficiency. Summary of the invention
[0003] The embodiments of the present application disclose a data transmission method, device, host computer and computer-readable storage medium for improving data transmission efficiency.
[0004] In a first aspect, an embodiment of the present application discloses a data transmission method, which is applied to a host computer in a data transmission system, wherein the data transmission system also includes a simulator and a test chip, including:
[0005] Determining the data to be transmitted of the test chip;
[0006] Dividing the data to be transmitted into a plurality of continuous data;
[0007] Inserting a target signal between two adjacent data among the plurality of data to obtain first target data;
[0008] The first target data is sent to the test chip through the simulator, and the target signal is used for the test chip to continue receiving data.
[0009] In a second aspect, an embodiment of the present application discloses a data transmission device, which is applied to a host computer in a data transmission system, wherein the data transmission system also includes a joint test working group simulator and a programmable system-on-chip test chip, including:
[0010] A determination unit, used to determine the data to be transmitted of the test chip;
[0011] A division unit, used for dividing the data to be transmitted into a plurality of continuous data;
[0012] an inserting unit, configured to insert a target signal between two adjacent data among the plurality of data to obtain first target data;
[0013] A communication unit is used to send the first target data to the test chip through the simulator, and the target signal is used for the test chip to continue receiving data.
[0014] In a third aspect, an embodiment of the present application discloses a host computer, including a processor and a memory, wherein the processor is used to call a computer program stored in the memory to execute the method disclosed in the first aspect.
[0015] In a fourth aspect, an embodiment of the present application discloses a computer-readable storage medium, on which a computer program or computer instructions are stored. When the computer program or computer instructions are executed by a processor, the method disclosed in the first aspect above is implemented.
[0016] In a fifth aspect, an embodiment of the present application discloses a computer program product, which includes a computer program code. When the computer program code is executed by a processor, the above method is executed.
[0017] In an embodiment of the present application, the host computer determines the data to be transmitted of the test chip, divides the data to be transmitted of the test chip into a plurality of continuous data, inserts a target signal between two adjacent data in the plurality of data to obtain the first target data, and sends the first target data to the test chip through the simulator, and the target signal is used for the test chip to continue to receive data. The host computer first divides the data to be transmitted of the test chip into a plurality of data, inserts a target signal between two adjacent data in the plurality of data, and sends the data including the target signal to the test chip. Since the target signal has the function of enabling the test chip to continue to receive data, the test chip can continue to receive data according to the target signal after receiving data each time, and does not need to send an ACK signal to the host computer. Accordingly, since the host computer sends the target signal to the test chip, after sending the data once, it does not need to wait for the test chip to return the ACK signal, and can continue to send data to the test chip. Since the time for the host computer to wait for the ACK signal is reduced, the time for the host computer to transmit data to the test chip can be shortened, thereby improving the data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 It is a schematic diagram of a system architecture disclosed in an embodiment of the present application;
[0020] Figure 2 It is a flowchart of a data transmission method disclosed in an embodiment of the present application;
[0021] Figure 3 It is a flowchart of another data transmission method disclosed in an embodiment of the present application;
[0022] Figure 4 It is a flowchart of another data transmission method disclosed in an embodiment of the present application;
[0023] Figure 5 is a schematic diagram of a data transmission disclosed in an embodiment of the present application;
[0024] Figure 6 It is a structural schematic diagram of a data transmission device disclosed in an embodiment of the present application;
[0025] Figure 7 It is a structural schematic diagram of a host computer disclosed in an embodiment of the present application. DETAILED DESCRIPTION
[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0027] The embodiments of the present application disclose a data transmission method, device, host computer and computer-readable storage medium, which are used to improve the efficiency of data transmission.
[0028] In order to better understand the embodiments of the present application, the system architecture of the embodiments of the present application is first described below.
[0029] See also Figure 1 , Figure 1 Schematic diagram of a system architecture disclosed in the embodiment of the present application. Figure 1 As shown, the system architecture may include a host computer 101, an emulator 102 and a test chip 103. The host computer 101 and the emulator 102, and the emulator 102 and the test chip 103 may be connected via wired cables.
[0030] The host computer 101 may first send the data to be transmitted of the test chip 103 to the simulator 102. After the simulator 102 receives the data to be transmitted of the test chip 103 from the host computer 101, it may forward the data to be transmitted of the test chip 103 to the test chip 103. After the test chip 103 receives the data to be transmitted of the test chip 103 from the simulator 102, it may process the data to be transmitted.
[0031] The data to be transmitted may be configuration data or various test instructions.
[0032] In the case where the data to be transmitted is configuration data, after the test chip 103 receives the configuration data of the test chip 103 from the simulator 102 , the test chip 103 may be configured according to the configuration data.
[0033] In the case where the data to be transmitted is a test instruction, after the test chip 103 receives the test instruction from the simulator 102, it can perform a test according to the test instruction, and after the test is completed, it can send the test result to the simulator 102. After the simulator 102 receives the test result from the test chip 103, it can send the test result to the host computer 101. After receiving the test result from the simulator 102, the host computer 101 can output the test result so that the user can connect to understand the test status of the test chip 103.
[0034] The host computer refers to a device that can directly issue control commands, such as a laptop computer, desktop computer, etc.
[0035] An emulator, also called a debugger, is a device used for debugging.
[0036] The test chip can be any chip that needs to be tested or debugged.
[0037] It should be understood that Figure 1 This is an exemplary description of the system architecture of the present application, and does not limit the system architecture of the present application. For example, there may be multiple test chips and multiple simulators.
[0038] In order to better understand the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below.
[0039] With the continuous development of integrated circuit technology, System On Programmable Chip (SOPC) chips have been widely used. Before SOPC chips are used, the host computer can test and debug the SOPC chips through the Joint Test Action Group (JTAG) emulator. In the process of testing and debugging the SOPC chip by the host computer through the JTAC emulator, the host computer needs to send various data to the SOPC chip, such as configuration data, various test instructions, etc.
[0040] Since the amount of data that the host computer can transmit to the SOPC chip each time is limited, when the amount of data to be sent is large, it takes multiple times to send all the data to the SOPC chip. After the host computer sends data to the SOPC chip each time, the host computer needs to wait for the SOPC chip to return an acknowledgment (ACK) signal to ensure that the data previously sent to the SOPC chip is successfully received by the SOPC chip before continuing to write data, resulting in a longer data transmission time and reduced data transmission efficiency.
[0041] In order to solve the above problems, the present application discloses a data transmission method, in which a host computer determines the data to be transmitted of a test chip, divides the data to be transmitted into multiple continuous data, inserts a target signal between two adjacent data in the multiple data to obtain first target data, and sends the first target data to the test chip through a simulator, and the target signal is used for the test chip to continue to receive data.
[0042] The host computer first divides the data to be transmitted of the test chip into multiple data, inserts a target signal between two adjacent data in the multiple data, and sends the data including the target signal to the test chip. Since the target signal has the function of enabling the test chip to continue to receive data, the test chip can continue to receive data according to the target signal after receiving data each time, and does not need to send an ACK signal to the host computer. Accordingly, since the host computer sends the target signal to the test chip, after sending the data once, it does not need to wait for the test chip to return the ACK signal, and can continue to send data to the test chip. Since the time the host computer waits for the ACK signal is reduced, the time the host computer transmits data to the test chip can be shortened, thereby improving data transmission efficiency.
[0043] See also Figure 2 , Figure 2 1 is a flow chart of a data transmission method disclosed in an embodiment of the present application. The data transmission method can be applied to a data transmission system, which can include a host computer, a simulator and a test chip. Figure 2 As shown, the data transmission method may include the following steps.
[0044] 201. The host computer determines the data to be transmitted of the test chip.
[0045] When the test chip needs to be tested and / or debugged, the host computer and the emulator, as well as the emulator and the test chip, can be connected via wired cables.
[0046] The data to be transmitted of the test chip is data that needs to be written into the test chip. The data to be transmitted of the test chip can be configuration data of the test chip, various test instructions of the test chip, or other data that needs to be written into the test chip.
[0047] The host computer can determine the data to be transmitted of the test chip. Specifically, the host computer can obtain the data to be transmitted of the test chip, or can generate the data to be transmitted of the test chip.
[0048] When the host computer obtains the data to be transmitted of the test chip, the host computer may obtain the data to be transmitted of the test chip from a server or a database, or the host computer may obtain the data to be transmitted of the test chip from a terminal device.
[0049] 202. The host computer divides the data to be transmitted of the test chip into a plurality of continuous data.
[0050] After the host computer determines the data to be transmitted of the test chip, the data to be transmitted of the test chip can be divided into a plurality of continuous data.
[0051] In some embodiments, due to the protocol provisions, the amount of data that the host computer can write to the test chip each time is fixed. Therefore, the host computer can first determine the amount of data to be transmitted of the test chip, and then determine whether the amount of data to be transmitted is greater than the amount of written data. In the case where it is determined that the amount of data to be transmitted is greater than the amount of written data, it indicates that due to the large amount of data to be transmitted of the test chip, the host computer cannot write the data to be transmitted of the test chip into the test chip at one time. Therefore, the data to be transmitted of the test chip can be divided into multiple continuous data, so that the data to be transmitted of the test chip can be transmitted to the test chip multiple times. The continuous multiple data can be understood as the order of the multiple data after division is different from the order before division, which can ensure that the data in the data to be transmitted will not be confused.
[0052] When it is determined that the amount of data to be transmitted is less than or equal to the amount of data to be written, it indicates that the amount of data to be transmitted of the test chip is small, and the host computer can write the data to be transmitted of the test chip into the test chip at one time. Therefore, the host computer can send the data to be transmitted of the test chip to the test chip through the emulator.
[0053] The amount of data written is the amount of data that the host computer can write into the test chip each time as specified by the protocol.
[0054] It can be seen that when the amount of data to be transmitted of the test chip is greater than the amount of written data, the host computer divides the data to be transmitted of the test chip, which can ensure that when the data is large, the data can be transmitted to the test chip through multiple transmissions. When the amount of data to be transmitted of the test chip is less than or equal to the amount of written data, the host computer does not divide the data to be transmitted of the test chip, but directly sends it, which can reduce unnecessary processing processes, thereby reducing the power consumption of the host computer.
[0055] The test chips are different, and the protocol stipulates that the amount of data that the host computer can write into the test chip each time may be different.
[0056] In some embodiments, the host computer may first obtain the first information of the test chip. The first information of the test chip may be the type of the test chip, or may be the type and signal of the test chip. When the types of the test chips are different and the amount of data that can be written to the test chips each time is different, the first information of the test chip is the type of the test chip. When the models of the test chips are different and the amount of data that can be written to the test chips each time is different, it is necessary to determine not only the type of the test chip but also the model of the test chip. Therefore, the first information of the test chip is the type and model of the test chip.
[0057] Afterwards, the host computer can determine the amount of data to be written according to the first information of the test chip, that is, the amount of data to be written each time.
[0058] In one case, the host computer stores a correspondence between the test chip and the data volume. After the host computer obtains the first information of the test chip, it can determine the data volume corresponding to the information of the test chip according to the stored correspondence to obtain the write data volume.
[0059] In another case, the server stores a correspondence between the test chip and the data volume. The host computer can send a data volume acquisition request to the server, and the data volume acquisition request includes the first information of the test chip. After the server receives the data volume acquisition request for obtaining the write data volume from the host computer, it can determine the data volume corresponding to the first information of the test chip according to the stored correspondence relationship, obtain the write data volume, and then send the write data volume to the host computer. Accordingly, the host computer can receive the write data volume from the server.
[0060] After the host computer determines the amount of written data, the data to be transmitted can be divided into multiple continuous data according to the amount of written data, that is, the data to be transmitted is divided according to the amount of written data. The amount of data except the last data in the multiple data is the amount of written data. The amount of the last data in the multiple data can be equal to the amount of written data or less than the amount of written data.
[0061] It can be seen that when the data to be transmitted of the test chip is divided, it is not divided randomly, but divided according to the first information of the test chip. The first information of the test chip is different, and the amount of data after division can be different, which can improve the flexibility and applicability of data division.
[0062] In some embodiments, the amount of written data is received by a host computer.
[0063] In one case, the host computer includes an interactive device. A user can input the amount of data written to the test chip to the host computer through the interactive device. The host computer can determine the amount of data written in response to the user's input operation on the amount of data written.
[0064] In another case, the user can transmit the amount of written data to the host computer through the terminal device. The terminal device can send the amount of written data to the host computer. Correspondingly, the host computer can receive the amount of written data from the terminal device.
[0065] It can be seen that the amount of write data can be input by the user or sent by the terminal device, and does not need to be determined by the host computer, which can reduce the processing process of the host computer and thus reduce the power consumption of the host computer.
[0066] 203. The host computer inserts a target signal between two adjacent data in the multiple data to obtain first target data.
[0067] The target signal has the function of allowing the test chip to continue to execute the current task. It can be seen that when the current task is to receive data from the host computer, the target signal has the function of allowing the test chip to continue to receive data from the host computer.
[0068] After the host computer divides the data to be transmitted of the test chip into a plurality of continuous data, a target signal may be inserted between two adjacent data in the plurality of data to obtain first target data.
[0069] It can be seen that the host computer inserts a target signal between two adjacent data among the multiple data. Therefore, after the host computer sends the first data among the multiple data to the test chip, it sends the target signal to the test chip. It does not need to wait for the test chip to return the ACK signal before sending the second data to the test chip. Instead, after sending the first data and the adjacent target signal to the test chip, it can continue to send the second data to the test chip, and so on, until the last data is sent to the test chip. Since the time the host computer sends the target signal is much shorter than the time the host computer waits to receive the ACK signal, the time the host computer transmits data to the test chip can be shortened, thereby improving the data transmission efficiency.
[0070] The number of target signals inserted each time may vary depending on the test chip.
[0071] In some embodiments, the host computer may first obtain the second information of the test chip, and then determine the number of target signal insertions to obtain the target number based on the second information of the test chip. When the types of test chips are different and the number of target signals inserted each time is different, the second information of the test chip is the type of the test chip. When the models of the test chips are different and the number of target signals inserted each time is different, it is necessary not only to determine the type of the test chip but also to determine the model of the test chip. Therefore, the second information of the test chip is the type and model of the test chip. Among them, the first information of the test chip and the second information of the test chip may be the same or different.
[0072] Afterwards, the host computer may insert a target number of target signals between two adjacent data among the multiple data to obtain the first target data.
[0073] It can be seen that when inserting the target signal, it is not inserted randomly, but inserted according to the second information of the test chip. The second information of the test chip is different, and the number of inserted target signals can be different, which can improve the flexibility and applicability of target signal insertion.
[0074] The target signal may be a test clock (Test Clock, TCK), a test data input (Test DataIn, TDI) signal, a test mode select (Test Mode Select, TMS) signal, or other signals with equivalent functions.
[0075] 204. The host computer sends the first target data to the test chip through the simulator.
[0076] Correspondingly, the test chip receives the first target data from the host computer through the simulator.
[0077] After the host computer obtains the first target data, it can send the first target data to the test chip through the simulator.
[0078] The host computer sends the first target data to the test chip by sending the data multiple times, and the data sent each time may include a target signal. The target signal is used for the test chip to continue receiving data.
[0079] It can be seen that the host computer first divides the data to be transmitted of the test chip into multiple data, inserts the target signal between two adjacent data in the multiple data, and sends the data including the target signal to the test chip. Since the target signal has the function of enabling the test chip to continue to receive data, the test chip can continue to receive data according to the target signal after receiving data each time, and does not need to send an ACK signal to the host computer. Accordingly, since the host computer sends the target signal to the test chip, after sending the data once, it does not need to wait for the test chip to return the ACK signal, and can continue to send data to the test chip. Since the time the host computer waits for the ACK signal is reduced, the time the host computer transmits data to the test chip can be shortened, thereby improving the data transmission efficiency.
[0080] In some embodiments, the host computer may first send the first data among multiple data included in the first target data to the test chip through the emulator, and then may send the target signal inserted after the first data to the test chip through the emulator, and then may send the second data among the multiple data included in the first target data to the test chip through the emulator, and then may send the target signal inserted after the second data to the test chip through the emulator,… and then may send the last data among the multiple data included in the first target data to the test chip through the emulator.
[0081] It can be seen that the host computer will send a target signal after sending data to the test chip each time. Since the target signal has the function of enabling the test chip to continue to receive data, the test chip can continue to receive data according to the target signal each time it receives data, and there is no need to send an ACK signal to the host computer. Accordingly, since the host computer has sent a target signal to the test chip, after sending the data once, there is no need to wait for the test chip to return an ACK signal, and data can continue to be sent to the test chip. Since the time the host computer waits for the ACK signal is reduced, the time the host computer transmits data to the test chip can be shortened, thereby improving data transmission efficiency.
[0082] In some embodiments, the host computer can determine the maximum amount of data transmitted by the simulator according to the bandwidth of the simulator, and then generate a data buffer area according to the maximum amount of data transmitted by the simulator, and the first target data can be stored in the data buffer area in sequence, and when the remaining space of the data buffer area is 0, the first data can be sent to the test chip through the simulator. The first target data includes the first data, and the first data is the data stored in the data buffer area.
[0083] The amount of data that the host computer can send to the test chip at one time is determined by the bandwidth of the simulator connecting the host computer and the test chip. Therefore, when initializing the simulator, the host computer can obtain the simulator's bandwidth, and then determine the simulator's maximum transmission data volume based on the simulator's bandwidth, and then generate a data buffer for caching data based on the simulator's maximum transmission data volume.
[0084] The maximum bandwidth of the simulator is determined by the bandwidth of the first cable connecting the simulator and the host computer, and the bandwidth of the second cable connecting the simulator and the test chip. The maximum bandwidth of the simulator is the minimum bandwidth of the bandwidth of the first cable and the bandwidth of the second cable. The bandwidth of the simulator can be less than or equal to the maximum bandwidth of the simulator, which can ensure that the amount of data transmitted is less than or equal to the amount of data that the cable can transmit, thereby avoiding the situation where data loss due to insufficient bandwidth of the cable can be caused, and ensuring the reliability of data transmission.
[0085] After the host computer obtains the first target data, it can sequentially store the data in the first target data into the data buffer.
[0086] Exemplarily, assuming that the size of the data buffer is 20 bits and the data volume of the first target data is 70 bits, the upper computer can first store the first 20 bits of data in the first target data in the data cache area. After sending the first 20 bits of data in the data cache area to the test chip, the second 20 bits of data in the first target data can be stored in the data cache area. After sending the second 20 bits of data in the data cache area to the test chip, the third 20 bits of data in the first target data can be stored in the data cache area. After sending the third 20 bits of data in the data cache area to the test chip, the last 10 bits of data in the first target data can be stored in the data cache area.
[0087] When the host computer has data to send to the test chip, the host computer can detect the remaining space of the data cache in real time, periodically or regularly. When it is detected that the remaining space of the data cache is 0, it indicates that the data cache is full, and the first data can be sent to the test chip through the simulator.
[0088] It can be seen that the host computer can detect whether the data cache area is full. When the data cache area is full, the data stored in the data cache area can be automatically sent to the test chip, which can realize automatic data transmission without user participation and improve data transmission efficiency. In addition, since the data stored in the data cache area is sent to the test chip, the data cache area can continue to cache data.
[0089] In some embodiments, when the state of the host computer is switched from the write state to the read state, the host computer may send the first data to the test chip through the emulator.
[0090] The host computer can also detect the state of the host computer, and when it detects that the state of the host computer switches from the write state to the read state, the first data can be sent to the test chip through the emulator. The write state is the state in which the host computer writes data to the test chip, and the read state is the state in which the host computer reads data from the test chip.
[0091] It can be seen that the host computer can detect the state of the host computer in real time, periodically or regularly. When it is detected that the state of the host computer is converted from a write state to a read state, it indicates that the host computer needs to read data, and data must be written before reading the data. Therefore, the first data cached in the data cache area can be sent to the test chip through the emulator.
[0092] It can be seen that when the upper computer needs to send data to the test chip, the data is not sent directly to the test chip through the emulator, but the data is first cached in the data cache area. Then, the data cached in the data cache area can be automatically sent to the test chip through the emulator according to the automatic inspection logic of the data cache area. Automatic data sending can be achieved, user participation can be reduced, and data transmission time can be further shortened, thereby improving data transmission efficiency.
[0093] For example, assuming that the amount of data to be transmitted is 10M bits, when using the ACK signal mechanism, the host computer needs more than 60 seconds to send the data to be transmitted to the test chip. When using the target signal but not the data cache, the host computer needs about 20 seconds to send the data to be transmitted to the test chip. When using the target signal and the data cache, the host computer needs 7 to 9 seconds to send the data to be transmitted to the test chip.
[0094] In some embodiments, the host computer sends the first data to the test chip through the simulator in response to a cleaning instruction from a user for cleaning the cache.
[0095] The user can clean up the data cached in the data cache area, and the host computer can detect the cleaning instruction of the user for cleaning up the cache, and can respond to the cleaning instruction and send the first data to the test chip through the simulator. It can be seen that the user can use the cleaning instruction to make the host computer send the data in the data cache area to the test chip, which can avoid the situation where the time-sensitive instruction cannot be sent to the test chip in time. In addition, the user's control ability can also be improved.
[0096] Since the target signal is inserted between the host computer and the test chip, and the ACK signal is removed, the host computer cannot determine the working status of the test chip during the configuration of the data to be transmitted. Therefore, the host computer can add status detection information for detecting the status information of the test chip at the end of the data to be transmitted.
[0097] In some embodiments, the host computer may first add the state detection information after the first target data to obtain the second target data, and then send the second target data to the test chip through the simulator.
[0098] The host computer can first add the state detection information after the first target data to obtain the second target data, and then send the second target data to the test chip through the simulator. After the test chip receives the second target data from the host computer through the simulator, it can detect the current state of the test chip according to the state detection information in the second target data, and then determine the state information of the test chip according to the current state of the test chip, and send the state information of the test chip through the simulator, that is, the information of the current state of the test chip. After the host computer receives the state information from the test chip, it can determine the current state of the test chip according to the state information of the test chip. When the current state of the test chip is normal, it indicates that the state of the test chip is normal and the test chip successfully receives the data to be transmitted. When the current state of the test chip is abnormal, it indicates that the state of the test chip is abnormal and the test chip does not successfully receive the data to be transmitted. It can be seen that the host computer can obtain the state information of the test chip through the state detection information, so as to determine whether the data to be transmitted is successfully transmitted according to the state information of the test chip, and avoid the situation where the test fails due to the failure of the transmission of the data to be transmitted.
[0099] The state detection information has a function of switching the write state to the read state.
[0100] The way in which the host computer sends the second target data to the test chip through the simulator is the same as the way in which the host computer sends the first target data to the test chip through the simulator. For a detailed description, please refer to the above related description and will not be repeated here.
[0101] See also Figure 3 , Figure 3 FIG. 1 is a flow chart of another data transmission method disclosed in an embodiment of the present application. Figure 3 As shown, the data transmission method may include the following steps.
[0102] 301. The host computer determines the data to be transmitted of the SOPC chip.
[0103] 302. The host computer divides the data to be transmitted of the SOPC chip into a plurality of continuous data.
[0104] In some embodiments, the host computer may first obtain the first information of the SOPC chip, and then determine the amount of written data according to the first information of the SOPC chip, and further divide the data to be transmitted into multiple continuous data according to the amount of written data.
[0105] 303. The host computer inserts a target signal between two adjacent data among the multiple data to obtain first target data.
[0106] In some embodiments, the host computer can first obtain the second information of the test chip, and then determine the insertion number of the target signal according to the second information of the SOPC chip to obtain the target number, and then insert the target number of target signals between two adjacent data in multiple data to obtain the first target data.
[0107] 304. The host computer sends the first target data to the SOPC chip through the JTAG emulator.
[0108] Correspondingly, the SOPC chip receives the first target data from the host computer through the JTAG emulator.
[0109] In some embodiments, the host computer can determine the maximum transmission data volume of the JTAG emulator according to the bandwidth of the JTAG emulator, and then generate a data buffer area according to the maximum transmission data volume of the JTAG emulator, and the first target data can be stored in the data buffer area in sequence. When the remaining space of the data buffer area is 0, the first data can be sent to the SOPC chip through the JTAG emulator. The first target data includes the first data, and the first data is the data stored in the data buffer area.
[0110] In some embodiments, when the state of the host computer is switched from the write state to the read state, the host computer may send the first data to the SOPC chip through the JTAG emulator.
[0111] In some embodiments, the host computer may send the first data to the SOPC chip through the JTAG emulator in response to a cleaning instruction from a user for cleaning the cache.
[0112] In some embodiments, the host computer can add state detection information after the first target data to obtain the second target data, and can send the second target data to the SOPC chip through the JTAG emulator. The SOPC chip can detect the current state of the SOPC chip according to the state detection information, and then determine the state information of the SOPC chip according to the current state of the SOPC chip, and can send the state information of the SOPC chip to the host computer through the JTAG emulator. Accordingly, the host computer can receive the state information from the SOPC chip through the JTAG emulator.
[0113] The difference between the above embodiment and the previous embodiment is that the test chip is a SOPC chip and the simulator is a JTAG simulator. It can be seen that this embodiment is an application scenario of the above embodiment.
[0114] For example, see Figure 4 , Figure 4 FIG. 1 is a flow chart of another data transmission method disclosed in an embodiment of the present application. Figure 4 As shown, the host computer rewrites the read ACK signal into the write TCK signal. The host computer can write the data to be written to the SOPC chip and the TCK signal into the data cache together. When the data cache is full, or the state is switched from the write state to the read state, or the user clears the data cache, the host computer can write the cached data in the data cache to the SOPC chip through the JTAG emulator.
[0115] There will be validity between different data to be transmitted written by the user to the SOPC chip. Assume that the user needs to write data to be transmitted 1 and data to be transmitted 2, but requires that data to be transmitted 2 can only be sent 50 milliseconds after data to be transmitted 1 is written. Figure 5 , Figure 5 Schematic diagram of a data transmission disclosed in the embodiment of the present application. Figure 5 As shown, the host computer writes the data to be transmitted into the data buffer area. In order to ensure that all the data to be transmitted is sent to the SPOC chip, the user can clear the data buffer area. After the host computer detects the clearing instruction, it can send the data to be transmitted in the data buffer area to the SPOC chip. After clearing the data buffer area, the data to be transmitted is sent to the SPOC chip after a delay of fifty milliseconds.
[0116] See also Figure 6 , Figure 6 1 is a schematic diagram of a data transmission device disclosed in an embodiment of the present application. The data transmission device can be applied to a host computer in a data transmission system, and the data transmission system can also include an emulator and a test chip. Figure 6 As shown, the data transmission device may include:
[0117] A determination unit 601 is used to determine the data to be transmitted of the test chip;
[0118] A division unit 602, used for dividing the data to be transmitted of the test chip into a plurality of continuous data;
[0119] An inserting unit 603, configured to insert a target signal between two adjacent data in the plurality of data to obtain first target data;
[0120] The communication unit 604 is used to send first target data to the test chip through the simulator, and the target signal is used for the test chip to continue receiving data.
[0121] In some embodiments, the data transmission device may further include:
[0122] An acquisition unit, used for acquiring first information of a test chip;
[0123] The determination unit 601 is further used to determine the amount of written data according to the first information of the test chip;
[0124] The division unit 602 is specifically configured to divide the data to be transmitted into a plurality of continuous data according to the amount of written data.
[0125] In some embodiments, the acquisition unit is further used to acquire second information of the test chip;
[0126] The determining unit 601 is further used to determine the insertion quantity of the target signal according to the second information of the test chip to obtain the target quantity;
[0127] The inserting unit 603 is specifically configured to insert a target number of target signals between two adjacent data in the multiple data to obtain first target data.
[0128] In some embodiments, the data transmission device may further include:
[0129] An adding unit, used for adding state detection information after the first target data to obtain second target data;
[0130] The communication unit 604 is specifically configured to send the second target data to the test chip through the simulator;
[0131] The communication unit 604 is also used to receive status information from the test chip through the simulator.
[0132] In some embodiments, the determining unit 602 is further configured to determine the maximum amount of data transmitted by the simulator according to the bandwidth of the simulator;
[0133] The data transmission device may further include:
[0134] A generating unit, used for generating a data buffer area according to a maximum transmission data amount of the simulator;
[0135] The communication unit 604 is specifically used for:
[0136] storing the first target data in the data buffer area in sequence;
[0137] When the remaining space of the data buffer area is 0, the first data is sent to the test chip through the simulator, and the first target data includes the first data, and the first data is the data stored in the data buffer area.
[0138] In some embodiments, the communication unit 604 is further configured to:
[0139] When the state of the host computer is switched from the write state to the read state, the first data is sent to the test chip through the simulator.
[0140] In some embodiments, the communication unit 604 is further configured to:
[0141] In response to a cleaning instruction from a user for cleaning the cache, first data is sent to the test chip through the simulator.
[0142] Technical personnel in the relevant field can clearly understand that, for the convenience and brevity of description, the specific working processes of the determination unit 601, the division unit 602, the insertion unit 603, the communication unit 604, the acquisition unit, the adding unit and the generation unit described above can refer to the corresponding processes in the aforementioned method embodiment and will not be repeated here.
[0143] In several embodiments provided in the present application, the coupling between the units may be electrical, mechanical or other forms of coupling.
[0144] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0145] Please refer to Figure 7 , Figure 7 Schematic diagram of the structure of a host computer disclosed in the embodiment of this application. Figure 7 As shown, the host computer may include a processor 701 and a memory 702. The memory 702 may store one or more computer programs. The one or more computer programs are configured to execute the method described in the above method embodiment. The memory 702 may exist independently or be integrated with the processor 701.
[0146] The processor 701 may include one or more processing cores. The processor 701 may use various interfaces and lines to connect the various parts of the entire host computer, and may execute various functions of the host computer and process data by running or executing instructions, programs, code sets or instruction sets stored in the memory 702, and calling data stored in the memory 702. Optionally, the processor 701 may be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 701 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It is understandable that the above-mentioned modem may not be integrated into the processor 701, but may be implemented separately through a communication chip.
[0147] The memory 702 may include a random access memory (RAM) or a read-only memory (ROM). The memory 702 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 702 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc. The data storage area may also store data created by the host computer during use (such as a phone book, audio and video data, chat record data), etc.
[0148] When the computer program instructions stored in the memory 702 are executed, the processor 701 can be used to execute various operations performed by the host computer in the above method embodiment. The specific implementation of these operations can refer to the previous embodiments and will not be repeated here.
[0149] A schematic diagram of the structure of a computer-readable storage medium disclosed in an embodiment of the present application. The computer-readable medium stores computer program code, which can be called by a processor to perform various operations in the above method embodiment. The specific implementation of each of the above operations can be referred to the previous embodiment, and will not be repeated here.
[0150] The computer readable storage medium may be an electronic memory such as a flash memory, an electrically erasable programmable read only memory (EEPROM), an erasable programmable read only memory (EPROM), a hard disk or a ROM. Alternatively, the computer readable storage medium may include a non-transitory computer-readable storage medium. The computer readable storage medium has storage space for program codes that execute any of the method steps in the above method. These computer program codes may be read from or written to one or more computer program products. The computer program code may be compressed, for example, in an appropriate form.
[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A data transmission method, characterized in that: The method is applied to a host computer in a data transmission system, and the data transmission system also includes a simulator and a test chip, including: Determining the data to be transmitted of the test chip; Dividing the data to be transmitted into a plurality of continuous data; Inserting a test clock target signal between two adjacent data among the plurality of data to obtain first target data; The first target data is sent to the test chip through the simulator, and the target signal is used for the test chip to continue receiving data.
2. The method according to claim 1, characterized in that The method further comprises: Acquire first information of the test chip; Determine the amount of data to be written according to the first information of the test chip; The step of dividing the data to be transmitted into a plurality of continuous data comprises: The data to be transmitted is divided into a plurality of continuous data according to the amount of written data.
3. The method according to claim 1, characterized in that The method further comprises: Acquire second information of the test chip; Determine the insertion quantity of the target signal according to the second information of the test chip to obtain the target quantity; Inserting a target signal between two adjacent data in the plurality of data to obtain first target data comprises: The target number of target signals is inserted between two adjacent data among the multiple data to obtain first target data.
4. The method according to claim 1, characterized in that The method further comprises: Adding state detection information after the first target data to obtain second target data; The sending the first target data to the test chip through the simulator comprises: Sending the second target data to the test chip through the simulator; The method further comprises: The status information from the test chip is received through the simulator.
5. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Determining the maximum transmission data volume of the simulator according to the bandwidth of the simulator; Generate a data buffer area according to the maximum transmission data amount; The sending the first target data to the test chip through the simulator comprises: storing the first target data in the data buffer area in sequence; When the remaining space of the data cache area is 0, first data is sent to the test chip through the simulator, and the first target data includes the first data, and the first data is the data stored in the data cache area.
6. The method according to claim 5, characterized in that The sending the first target data to the test chip through the simulator further includes: When the state of the host computer is switched from a write state to a read state, first data is sent to the test chip through the simulator.
7. The method according to claim 5, characterized in that The sending the first target data to the test chip through the simulator further includes: In response to a cleaning instruction from a user for cleaning a cache, first data is sent to the test chip through the simulator.
8. A data transmission device, characterized in that: The device is applied to a host computer in a data transmission system, and the data transmission system also includes a joint test working group simulator and a programmable system-on-chip test chip, including: A determination unit, used to determine the data to be transmitted of the test chip; A division unit, used for dividing the data to be transmitted into a plurality of continuous data; An inserting unit, used for inserting a test clock target signal between two adjacent data among the plurality of data to obtain first target data; A communication unit is used to send the first target data to the test chip through the simulator, and the target signal is used for the test chip to continue receiving data.
9. A host computer, characterized in that: The method comprises a processor and a memory, wherein the processor calls a computer program stored in the memory to implement the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, which can be called by a processor to execute the method according to any one of claims 1 to 7.