Automatic layout method of low-noise amplifier chip circuit schematic diagram

Abstract

The invention discloses an automatic layout method for a low-noise amplifier chip circuit schematic diagram. The method comprises the following steps: storing all elements in an initial netlist and a connection relation thereof in an initial adjacency list; sequentially arranging elements connected with the power supply according to the adjacency list; sequentially finishing layout of elements connected with the resistors according to the adjacency list; completing the layout of all elements and subsequent connected elements on the shortest path between the input port and the output port; connecting lines and marks are supplemented on the transistors; comparing the initial adjacency list with the adjacency list of which all element layouts have been completed, and supplementing missing connecting lines; drawing all the layout-completed elements on the schematic diagram, setting dimension parameters of the elements, and completing the overall layout to generate the schematic diagram; and simulating the initial netlist and the generated schematic diagram, and comparing whether simulation results are consistent or not so as to verify whether the generated schematic diagram is correct or not. According to the method, automatic layout in the process of inverting the schematic circuit diagram by the circuit netlist of the low-noise amplifier chip can be realized, and the efficiency and the accuracy are improved.

Description

Technical Field

[0001] The invention belongs to the field of electronic information, and in particular relates to an automatic layout method for a circuit schematic diagram of a low-noise amplifier chip. Background Art

[0002] The automatic optimization program for the circuit schematic of the low-noise amplifier chip can automatically adjust the circuit architecture and optimize the component size parameters according to the indicators input by the designer, and output the netlist file of the circuit. Then the designer needs to perform subsequent layout drawing and simulation work to finally form a usable layout file. However, the netlist file is composed of strings, which is not easy to read for designers, so it is necessary to use a program to automatically convert the abstract netlist file into a graphical schematic diagram to display the parameters and connection relationships of all components, and the placement of components should minimize the cross-overlap of the connection lines. The schematic design part of the simulation software ADS, Schematic, is considered to be an excellent schematic design software in the industry because of its beautiful interface, easy entry and operation, and powerful simulation functions. However, this type of software can only be used to draw schematics manually, and cannot automatically process and draw related schematics. The actual situation shows that when using this type of software for manual schematic drawing, not only is the manual workload large, the design efficiency is low, and there is a lot of repetitive work, but also the consistency of the design cannot be guaranteed and it is easy to make mistakes. Therefore, an automatic layout method is needed. For low-noise amplifier chips with different architectures, it can automatically layout and generate circuit schematics that are convenient for designers to use. Summary of the invention

[0003] The purpose of the present invention is to provide an automatic layout method, computer equipment, computer-readable storage medium and computer program product for a circuit schematic diagram of a low-noise amplifier chip, which can realize automatic layout in the process of inverting the circuit schematic diagram from the circuit netlist of the low-noise amplifier chip, improve efficiency and accuracy, and solve the current problem of slow speed and high error rate of manual inversion of circuit schematic diagrams.

[0004] In order to achieve the above object, one aspect of the present invention provides an automatic layout method for a circuit schematic diagram of a low noise amplifier chip, comprising: Step S1: saving all components and their connection relationships in the initial netlist of the low noise amplifier chip circuit in an initial adjacency table; Step S2: Find the power supply component from the adjacency list, and arrange the components connected to the power supply in sequence according to the adjacency list until a ground connection or a resistor is encountered, save the resistor in the list, and then delete the arranged components in the adjacency list; Step S3: traverse the list obtained in step S2, and complete the layout of the components connected to the resistors in the list in sequence according to the adjacency list until a ground connection or a transistor is encountered, and then delete the components that have been laid out in the adjacency list; Step S4: Find the shortest path between the input and output ports in the adjacency list, complete the layout of all components on the path and their subsequent connected components in sequence, and then delete the components that have been laid out in the adjacency list; Step S5: traverse all transistors, add connections and annotations to the transistors, and then complete the layout of all remaining components in sequence; Step S6: Compare the initial adjacency list in step S1 with the adjacency list of all components in step S5, supplement the missing connections, delete the redundant connections, and repeat this step until the two are the same; Step S7: Read the size parameters of all components in the initial netlist and save them in the form of a dictionary; Step S8: Draw all the components of the completed layout on the schematic diagram, set the size parameters of the components according to the dictionary in step S7, and complete the overall layout to generate a schematic diagram; Step S9: Simulate the initial netlist and the schematic diagram generated by the overall layout in step S8, and compare the simulation results to see if they are consistent, so as to verify whether the generated schematic diagram is correct.

[0005] Preferably, step S2 comprises: Step S21: Find a power supply element in the initial adjacency list and set its coordinates; Step S22: traverse all components connected to the power supply in the initial adjacency table, set the coordinates of these components in turn, and store the component name of the resistor in the list; Step S23: Delete the elements whose positions have been set in the initial adjacency list and generate a new adjacency list.

[0006] Preferably, step S3 comprises: Step S31: traverse the list obtained in step S2, read the coordinates of the resistor elements in the list, set the coordinates of the elements subsequently connected to it in the adjacency list, and store these elements in a new list; Step S32: traverse the new list obtained in step S31, read the coordinates of the elements in the list and the elements subsequently connected to it in the adjacency list, store these elements in the new list, set the coordinates of these elements in turn, and repeat this step until a ground or a transistor is encountered; Step S33: Delete the elements whose positions have been set in the initial adjacency list and generate a new adjacency list.

[0007] Another aspect of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0008] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0009] Another aspect of the present invention provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0010] According to the automatic layout method, computer device, computer-readable storage medium and computer program product of the low-noise amplifier chip circuit schematic diagram of the above aspects of the present invention, it is possible to realize automatic layout in the process of inverting the circuit schematic diagram from the circuit netlist of the low-noise amplifier chip, thereby improving efficiency and accuracy and solving the problem of slow speed and high error rate in manual inversion of circuit schematic diagrams. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work: Figure 1 It is a flow chart of an automatic layout method of a circuit schematic diagram of a low noise amplifier chip according to an embodiment of the present invention; Figure 2 It is a simplified flow chart of an automatic layout method of a circuit schematic diagram of a low noise amplifier chip according to an embodiment of the present invention; Figure 3 is a flow chart of step S3 of an embodiment of the present invention; Figure 4 is an example diagram of a gate bias circuit generated in one embodiment of the present invention; Figure 5 This is an example diagram of a result generated through overall layout in one embodiment of the present invention; Figure 6 4 is a structural diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] An embodiment of the present invention provides an automatic layout method for a circuit schematic diagram of a low noise amplifier chip, such as Figure 1 As shown, the automatic layout method of the circuit schematic diagram of the low noise amplifier chip of the embodiment of the present invention includes steps S1 to S9. Figure 2 Each step of the method of the embodiment of the present invention is described in detail.

[0014] Step S1: Initialize the adjacency table The circuit netlist of the low-noise amplifier chip contains the connection relationship between components. The connection relationship between components in the netlist is extracted and stored in an adjacency table in the form of a dictionary. The key of the dictionary is the component name, and the corresponding value is a list containing the component names of all adjacent components, which can quickly realize the call and modification of the component connection relationship. In this step, all components and their connection relationships in the circuit netlist of the low-noise amplifier chip are saved in the initial adjacency table, and the connection relationship of the components in the netlist is saved in the form of an adjacency table, and the circuit schematic is regarded as an undirected graph.

[0015] Step S2: Layout of components connected to power supply The circuit schematic of a low-noise amplifier chip usually has only one power supply component. The components connected to the power supply are generally filter capacitors and resistors in the gate bias circuit. Designers are accustomed to treating these components separately from the main circuit, so these components are laid out first, and then the adjacency table is simplified by deleting these components to reduce the complexity of subsequent steps.

[0016] In this step, after obtaining the initial adjacency list, a power supply component is first found, and then the layout of the connected components is completed in sequence, such as Figure 4 The first row of components is shown. Subsequent components are then placed until a ground connection or resistor is encountered. The gate bias resistor is saved in a list for use in subsequent steps, and then the already placed components are deleted from the adjacency list for use in subsequent steps. In this step, the components connected to the power supply are placed according to the adjacency list, and then the already placed components in the adjacency list are deleted, thereby continuously simplifying the adjacency list and reducing the loops in the undirected graph.

[0017] Step S3: Gate bias circuit layout The gate bias circuit usually consists of five to eight components, starting from the resistor connected to the power supply and ending with the ground or the gate of the transistor. They can be arranged according to a given rule during the layout process. In this step, the list of gate bias resistors in step S2 is traversed, and then the layout of the connected components is completed in sequence until a landmark component such as ground or transistor is encountered. Figure 4 As shown, the already placed components are then deleted from the adjacency list for use in subsequent steps.

[0018] Step S4: Input and output matching circuit layout The circuit schematic of a low-noise amplifier chip usually contains multiple loops, so there can be multiple paths between the RF input and output ports. Find the shortest path between the two ports in the deleted adjacency table, lay out the components on the path as a horizontal row as the trunk, and connect other connected components vertically as branches, which can make the schematic diagram more readable, such as Figure 5 The components in the middle row are shown. After that, the layout of other components on the branch is completed in sequence, and then the components that have been laid out are deleted in the adjacency list for use in subsequent steps.

[0019] Step S5: Transistor adjacent component layout At this point, the layout of most components has been completed, but some components have not been traversed because of the operation of deleting components in the adjacency list in the previous step. These components are usually adjacent components of transistors, such as gate grounding capacitors. Therefore, it is necessary to traverse all transistors, add connections and labels on the transistor drain (D), gate (G), and source (S), and then complete the layout of all remaining components in turn, including capacitors, microstrip lines, and grounding.

[0020] Step S6: Supplement missing connections At this point, the layout of all components has been completed, but there may be some redundant or missing connections. Compare the adjacency list of the original netlist (old adjacency list) with the adjacency list of the completed layout components (new adjacency list), supplement the missing connections, delete the redundant connections, and repeat this step until the old and new adjacency lists are the same. This step can avoid missing connections or multiple connections of components or connections, and reduce the requirements for the previous steps.

[0021] Step S7: Read component size parameters At this point, the layout and wiring of all components have been completed, but the parameters of the components are initialized. It is necessary to read the size parameters of all components in the initial netlist and save them in the form of a dictionary for use in subsequent steps. The key of the dictionary is the component name, and the corresponding value is a list containing all the size parameters of the component.

[0022] Step S8: Overall layout of circuit schematic Draw all the components that have completed the layout on the schematic diagram, set the size parameters of the components according to the dictionary in step S7, add the settings required for simulation, and complete the overall layout to generate a circuit schematic diagram.

[0023] Step S9: Simulation verification Call the simulator to simulate the initial netlist and the schematic diagram generated after the overall layout, compare the simulation results to see if they are consistent, and verify whether the generated schematic diagram is correct.

[0024] In one embodiment, step S2 includes: Step S21: Find a power supply element in the initial adjacency list obtained in step S1 and set its coordinates; Step S22: traverse all components connected to the power supply in the initial adjacency list, set the coordinates of these components in turn, and store the component name of the resistor in the list for use in step S3; Step S23: Delete the elements whose positions have been set in the initial adjacency list and generate a new adjacency list.

[0025] In one embodiment, step S3 includes: Step S31: traverse the list obtained in step S2, read the coordinates of the elements in the list, use them to set the coordinates of the elements subsequently connected to it in the adjacency list, and store these elements in a new list; Step S32: traverse the new list obtained in step S31, read the coordinates of the elements in the list and the elements subsequently connected to them in the adjacency list, store these elements in the new list, set the coordinates of these elements in turn, and repeat this step until a landmark element such as a ground or transistor is encountered.

[0026] Step S33: Delete the elements whose positions have been set in the initial adjacency list and generate a new adjacency list.

[0027] The following is a specific example to further explain in detail the automatic layout method of the circuit schematic diagram of the low noise amplifier chip according to the embodiment of the present invention.

[0028] In step S1, the netlist is read row by row, and all elements in the netlist and their connection relationships are saved in an initial adjacency table.

[0029] In step S2, after obtaining the initial adjacency list, the power supply element (V_DC) is found, the coordinates are set to (0,8), and the elements connected to it are found in the adjacency list of V_DC. In this embodiment, they are a capacitor and two resistors (R1, R2), such as Figure 4 As shown. Save the component names of the two resistors into list1, and set the position coordinates of the three components to (1,8), (6,8) and (11,8) respectively.

[0030] In step S3, if Figure 3 As shown, traverse the list list1, read the coordinates of resistor R1 as (6,8), and the subsequent elements connected to it in the adjacency list are microstrip line TL1 and resistor R22. Set the coordinates P to (6,8), P is already in use, move P to (6,6), at this time P is not in use, set the coordinates of capacitor TL1 to (6,6), set the coordinates of capacitor R22 to (8,6), and connect them with a wire, and so on, to complete the gate bias circuit layout as shown in Figure 4 As shown, the components that have been placed are deleted from the adjacency list for use in subsequent steps.

[0031] In step S4, the shortest path between the input and output ports Term1 and Term2 is found in the pruned adjacency list, all the elements on the path are saved in a list, the coordinates of these elements are set in sequence, and then the layout of the subsequent connected elements of these elements is completed in sequence, such as Figure 4 As shown, the components that have been placed are deleted from the adjacency list for use in subsequent steps.

[0032] In step S5, all transistors are found, and connections and labels are added to the drain (D), gate (G), and source (S) of the transistors, and then the layout of all remaining components is completed in sequence.

[0033] In step S6, the adjacency list of the original netlist (old adjacency list) is compared with the adjacency list of the components that have been laid out (new adjacency list). If the length of the old adjacency list of a component is greater than that of the new adjacency list, it means that there are missing connections and the corresponding connections need to be added. If the length of the old adjacency list of a component is less than that of the new adjacency list, it means that there are redundant connections and the redundant connections need to be deleted. In order to avoid overlapping of connections, annotations can be used to replace the connections. This step is repeated until the old and new adjacency lists are the same.

[0034] In step S7, the size parameters of all components in the initial netlist are read, such as the length and width of capacitors and resistors, the number of turns and diameter of inductors, etc., and saved in the form of a dictionary. The key of the dictionary is the component name, and the corresponding value is a list containing all the size parameters of the component.

[0035] In step S8, all components of the completed layout are drawn on the schematic diagram, the size parameters of the components are set according to the dictionary in step S7, and the settings required for simulation are added as needed, such as frequency range and parameter definition, to complete the overall layout of the circuit schematic diagram.

[0036] In step S9, a simulator is called to simulate the initial netlist and the schematic diagram generated by the overall layout in step S8, and the simulation results are compared to see whether they are consistent, so as to verify whether the generated schematic diagram is correct.

[0037] In summary, the automatic layout method of the circuit schematic diagram of the low noise amplifier chip in the embodiment of the present invention can realize the automatic generation of the circuit schematic diagram from the netlist, improve the efficiency and accuracy, and solve the problem of slow speed and high error rate of manual inversion of the circuit schematic diagram.

[0038] Figure 4 and Figure 5 In order to combine the ADS software and use the partial and overall schematic diagram generation results of the method of the present invention, it has been verified that the method of the embodiment of the present invention can meet the actual engineering needs.

[0039] An embodiment of the present invention further provides a computer device, which may be a server, and its internal structure diagram may be as shown in FIG. Figure 6 As shown. The computer device includes a processor, a memory and a network interface connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the computer device is used to store operating parameter data of each framework. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the model construction and operation method of enhancing the simulation capability of the digital twin model of the embodiment of the present invention are implemented.

[0040] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0041] An embodiment of the present invention also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the model construction and operation method for enhancing the simulation capability of the digital twin model of the embodiment of the present invention are implemented.

[0042] An embodiment of the present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the model construction and operation method for enhancing the simulation capability of the digital twin model of an embodiment of the present invention.

[0043] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. An automatic layout method for a circuit schematic diagram of a low noise amplifier chip, characterized in that: include: Step S1: saving all components and their connection relationships in the initial netlist of the low noise amplifier chip circuit in an initial adjacency table; Step S2: Find the power supply component from the adjacency list, and arrange the components connected to the power supply in sequence according to the adjacency list until a ground connection or a resistor is encountered, save the resistor in the list, and then delete the arranged components in the adjacency list; Step S3: traverse the list obtained in step S2, and complete the layout of the components connected to the resistors in the list in sequence according to the adjacency list until a ground connection or a transistor is encountered, and then delete the components that have been laid out in the adjacency list; Step S4: Find the shortest path between the input and output ports in the adjacency list, complete the layout of all components on the path and their subsequent connected components in sequence, and then delete the components that have been laid out in the adjacency list; Step S5: traverse all transistors, add connections and annotations to the transistors, and then complete the layout of all remaining components in sequence; Step S6: Compare the initial adjacency list in step S1 with the adjacency list of all components in step S5, supplement the missing connections, delete the redundant connections, and repeat this step until the two are the same; Step S7: Read the size parameters of all components in the initial netlist and save them in the form of a dictionary; Step S8: Draw all the components of the completed layout on the schematic diagram, set the size parameters of the components according to the dictionary in step S7, and complete the overall layout to generate a schematic diagram; Step S9: Simulate the initial netlist and the schematic diagram generated by the overall layout in step S8, and compare the simulation results to see if they are consistent, so as to verify whether the generated schematic diagram is correct.

2. The method according to claim 1, characterized in that Step S2 includes: Step S21: Find a power supply element in the initial adjacency list and set its coordinates; Step S22: traverse all components connected to the power supply in the initial adjacency table, set the coordinates of these components in turn, and store the component name of the resistor in the list; Step S23: Delete the elements whose positions have been set in the initial adjacency list and generate a new adjacency list.

3. The method according to claim 1 or 2, characterized in that: Step S3 includes: Step S31: traverse the list obtained in step S2, read the coordinates of the resistor elements in the list, set the coordinates of the elements subsequently connected to it in the adjacency list, and store these elements in a new list; Step S32: traverse the new list obtained in step S31, read the coordinates of the elements in the list and the elements subsequently connected to it in the adjacency list, store these elements in the new list, set the coordinates of these elements in turn, and repeat this step until a ground or a transistor is encountered; Step S33: Delete the elements whose positions have been set in the initial adjacency list and generate a new adjacency list.

4. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 3.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

6. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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