Operation method of phase change memory, control circuit and phase change memory

Abstract

The embodiment of the invention provides an operation method and circuit of a phase change memory and the phase change memory. The method comprises the following steps: determining the life cycle of a phase change memory unit; adjusting the value of a preset parameter according to the life cycle; the preset parameters are parameters related to the write operation. According to the embodiment of the invention, the phase change memory unit can be kept stable in the full life cycle, and the performance loss is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to an operation method, a control circuit and a phase change memory. Background Art

[0002] Phase Change Memory (PCM) uses the conductivity or impedance difference between the crystalline and amorphous states of a specific phase change material to store data and is a type of non-volatile memory. The read and write operations of the storage unit (PCM unit for short) of the phase change memory are to apply voltage or current pulse signals of different widths and heights to the PCM unit; for the write 0 operation (i.e., reset operation, RESET), a short and strong pulse signal is applied to raise the temperature of the phase change material in the PCM unit to above the melting temperature, and then it is rapidly cooled to achieve the conversion of the phase change material from polycrystalline to amorphous state, that is, the conversion from "1" state to "0" state; for the write 1 operation (i.e., set operation, SET), a long and medium-intensity pulse signal is applied to raise the temperature of the phase change material to below the melting temperature and above the crystallization temperature, and it is maintained for a period of time to promote the growth of the crystal nucleus, thereby achieving the conversion from amorphous state to polycrystalline state, that is, the conversion from "0" state to "1" state; for the read operation, a very weak pulse signal that will not affect the state of the phase change material is applied, and its state is read by measuring the resistance value of the PCM unit.

[0003] When data is written to a PCM unit cyclically for a certain number of times, the PCM unit enters the middle and late stages of its life cycle. As the characteristics of the device change due to fatigue, some performance loss will occur. Summary of the invention

[0004] Embodiments of the present disclosure provide an operating method, a circuit and a phase change memory.

[0005] In a first aspect, an embodiment of the present disclosure provides an operating method of a phase change memory, wherein the phase change memory includes a plurality of phase change memory units, and the method includes:

[0006] determining a life cycle of the phase change memory unit;

[0007] According to the life cycle, the value of a preset parameter is adjusted; the preset parameter is a parameter related to the write operation.

[0008] In some embodiments, determining the life cycle of the phase change memory unit includes:

[0009] Determining the cumulative number of times the phase change memory unit is written;

[0010] If the cumulative number does not reach the preset threshold, the life cycle is determined to be in the early stage of the life cycle;

[0011] If the accumulated number reaches the preset threshold, it is determined that the life cycle is in the late stage of the life cycle.

[0012] In some embodiments, adjusting the value of a preset parameter according to the life cycle includes:

[0013] If the life cycle is in the early stage of the life cycle, the value of the preset parameter is set as a reference value;

[0014] If the life cycle is in the late life cycle, the value of the preset parameter is set to be greater than the reference value.

[0015] In some embodiments, the later stage of the life cycle includes at least one sub-stage, wherein the value of the preset parameter corresponding to the j-th sub-stage is greater than or equal to the value of the preset parameter corresponding to the ith sub-stage; wherein j and i are both integers greater than 0, and j is greater than i.

[0016] In some embodiments, setting the value of the preset parameter to be greater than the reference value includes:

[0017] Determine a step value corresponding to the current sub-stage, and superimpose the step value with the reference value to obtain a value of the preset parameter corresponding to the current sub-stage.

[0018] In some embodiments, the step value corresponding to the j-th sub-stage is greater than or equal to the step value corresponding to the ith sub-stage.

[0019] In some embodiments, the reference value includes a pulse duration reference value and a heating current reference value corresponding to a write operation signal received by the phase change memory unit, and the step value includes a corresponding pulse duration step value and a heating current step value;

[0020] The step value corresponding to the current sub-stage is determined; and the step value is superimposed on the reference value to obtain the value of the preset parameter corresponding to the current sub-stage, including:

[0021] Determine the pulse duration step value corresponding to the current sub-stage; superimpose the pulse duration step value with the pulse duration reference value to obtain the pulse duration corresponding to the current sub-stage;

[0022] And / or, determining a heating current step value corresponding to the current sub-stage; superimposing the heating current step value with the heating current reference value to obtain the magnitude of the heating current corresponding to the current sub-stage.

[0023] In a second aspect, an embodiment of the present disclosure provides a control circuit of a phase change memory, which is used to execute each step of the operating method as described in any one of the first aspects, including:

[0024] A first control circuit, used to determine the life cycle of the phase change memory unit;

[0025] The second control circuit is used to adjust the value of a preset parameter according to the life cycle; the preset parameter is a parameter related to the write operation.

[0026] In some embodiments, the second control circuit is configured to: if the life cycle is in the early stage of the life cycle, set the value of the preset parameter to a reference value; and if the life cycle is in the late stage of the life cycle, set the value of the preset parameter to be greater than the reference value;

[0027] The reference values ​​include a pulse duration reference value and a heating current reference value corresponding to a write operation signal received by the phase change memory unit.

[0028] In a third aspect, an embodiment of the present disclosure provides a phase change memory, comprising a control circuit of the phase change memory as described in any one of the second aspects.

[0029] The disclosed embodiments provide an operation method, a control circuit, and a phase change memory of a phase change memory, the method comprising: determining the life cycle of a phase change memory unit; adjusting the value of a preset parameter according to the life cycle; the preset parameter is a parameter related to a write operation. In this way, the disclosed embodiments first determine the current life cycle of the PCM unit, and then adjust the value of the relevant parameters used when writing data to the PCM unit in combination with the life cycle, thereby ensuring that the performance of the phase change memory remains stable throughout the life cycle and avoiding performance loss. The disclosed embodiments can increase the pulse time or heating current of the write operation signal in different life cycles of the PCM device, reduce the write error rate, and thus increase the life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of an equivalent circuit of a PCM unit provided in an embodiment of the present disclosure;

[0031] Figure 2 A waveform diagram of a write operation signal provided by an embodiment of the present disclosure;

[0032] Figure 3 A waveform diagram of a heating pulse provided by an embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of a flow chart of an operating method of a phase change memory provided by an embodiment of the present disclosure;

[0034] Figure 5 A block diagram of a system including a phase change memory provided by an embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram of the structure of a memory including a peripheral circuit provided in an embodiment of the present disclosure;

[0036] Figure 7 A waveform comparison diagram of a write operation signal provided by an embodiment of the present disclosure;

[0037] Figure 8 A schematic diagram for comparing the waveforms of a heating pulse provided in an embodiment of the present disclosure;

[0038] Fig. 9 A schematic diagram of the structure of an operating circuit of a phase change memory provided by an embodiment of the present disclosure;

[0039] Fig.10 A block diagram of a memory provided in an embodiment of the present disclosure;

[0040] Fig.11 A circuit diagram for performing a write operation on a PCM unit is provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0043] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0045] In PCM, the low resistance state of the PCM cell is the set state, or the state in which the stored data is logic "1"; the high resistance state of the PCM cell is the reset state, or the state in which the stored data is logic "0". By applying a certain current to the PCM cell to heat the phase change material therein, different states of the PCM cell are achieved.

[0046] See also Figure 1 , which shows an equivalent circuit diagram of a PCM unit provided by an embodiment of the present disclosure, such as Figure 1 As shown, the PCM unit is a unit structure of 1 transistor 1 resistor (1T1R). The word line WL (Word Line) is connected to the gate of the transistor T, one end of the PCM unit is connected to the transistor T, the other end of the variable resistor R is connected to the bit line BL (Bit Line), and the other end of the transistor T is grounded. When a write operation is performed on the PCM unit, the PCM unit is selected, the word line WL and the bit line BL are both selected, and the signal transmitted by the word line WL (recorded as a write operation signal) turns on the transistor T, thereby turning on the branch of the bit line BL and the variable resistor R, and the heating pulse transmitted by the bit line BL forms a heating current I in the variable resistor R. cell , heat the variable resistor R, change its state, and write 1 or write 0 based on different write operation signals and heating pulses.

[0047] like Figure 2 As shown, the waveform (reset waveform) of the write 0 operation (reset operation) of the PCM cell is generally a short pulse with a duration of 1-100ns (nanoseconds), and the waveform (set waveform) of the write 1 operation (set operation) is generally a long pulse with a duration of 300ns-1us, and may include three or more stages, such as Figure 1 The three stages of T1, T2 and T3. For example, Figure 3 The diagrams shown are respectively the heating pulse (reset heating pulse) for the write 0 operation and the heating pulse (set heating pulse) for the write 1 operation, the waveforms of which are similar to the write operation signal, but the timing is different. The pulse of the write operation can be a voltage pulse, and the heating pulse can be a current pulse or a voltage pulse.

[0048] Usually, the waveform of the write operation signal of the PCM unit generally remains unchanged throughout the life of the device, that is, no matter which life cycle stage the PCM unit is in, each write operation adopts Figure 2 and / or Figure 3As shown in the waveform, although this method can achieve good performance in the early stage of the device life cycle, in the middle and late stages of the device life, due to changes in the characteristics of the device after fatigue, the waveform of the write operation signal used in the initial state may no longer be applicable, resulting in some performance loss.

[0049] Based on this, an embodiment of the present disclosure provides an operation method of a phase change memory, wherein the phase change memory includes a plurality of phase change memory units, and the method includes: determining the life cycle of the phase change memory unit; adjusting the value of a preset parameter according to the life cycle; the preset parameter is a parameter related to the write operation. In this way, the embodiment of the present disclosure first determines the current life cycle of the PCM unit, and then adjusts the value of the relevant parameters used when writing data to the PCM unit in combination with the life cycle, thereby ensuring that the performance of the phase change memory remains stable throughout the life cycle and avoiding performance loss. Specifically, in the middle and late stages of the fatigue life of the PCM device, the write operation is optimized by increasing the pulse time of the write operation signal or increasing the current value of the heating current, thereby reducing the write error rate and improving the stability of the device.

[0050] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0051] In one embodiment of the present disclosure, see Figure 4 , which shows a flow chart of an operation method of a phase change memory provided by an embodiment of the present disclosure. Figure 4 As shown, the method may include:

[0052] S101: Determine the life cycle of a phase change memory unit.

[0053] S102: adjusting the value of a preset parameter according to the life cycle; the preset parameter is a parameter related to the write operation.

[0054] It should be noted that Figure 5 An exemplary block diagram of a system 200 including a phase change memory provided in an embodiment of the present disclosure. The system 200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 2As shown, the system 200 may include a host 201 and a memory system 202, wherein the memory system 202 has one or more memories 203 and a memory controller 204; the host 201 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 201 may be configured to send data to the memory 203 or receive data from the memory 203.

[0055] For example, the memory 203 may be a phase change memory, such as a phase change random access memory (PCRAM). In some embodiments, the memory controller 204 is coupled to the memory 203 and the host 201. The memory controller 204 is configured to control the memory 203. The memory controller 204 may manage data stored in the memory 203 and communicate with the host 201. The memory controller 204 may be configured to control operations such as erasing, reading, and writing of the memory 203.

[0056] Figure 6 An exemplary structural diagram of a memory 203 including a peripheral circuit provided in an embodiment of the present disclosure. The memory 203 may be a three-dimensional phase change memory, or of course a planar type, which may include a phase change memory array 601 and a peripheral circuit 602 coupled to the phase change memory array 601. The phase change memory array 601 may include a word line WL, a bit line BL, and a PCM unit 6013 formed between the word line WL and the bit line BL. In some embodiments, each PCM unit 6013 may include a PCM element (including a phase change material, not shown in the figure) connected in series with a selector. In order to operate the phase change memory array 601, a word line voltage may be applied to a selected word line WL, and a bit line voltage may be applied to a selected bit line BL.

[0057] In the embodiment of the present disclosure, the PCM unit can be Figure 1 The 1T1R structure shown may also be a 1 diode 1 resistor (1Diode 1Resident, 1D1R) structure, which is not specifically limited. The implementation process of the operation method of the phase change memory provided by the embodiment of the present disclosure will be described in detail below using the 1T1R structure as an example.

[0058] It should be noted that the PCM unit may have different performances in different life cycles of the PCM unit. It is understandable that in the later stage of the PCM life cycle, due to the fact that various operations have been performed many times, device fatigue may occur, resulting in performance damage, such as write or read data errors, etc. Therefore, when operating the phase change memory, for example, when writing data to the selected PCM unit or before writing data, the embodiment of the present disclosure first determines the current life cycle of the PCM unit, and then adjusts the value of the preset parameter related to the write operation according to the life cycle.

[0059] Here, the value of the preset parameter that ensures that the performance of the PCM unit does not suffer loss during different life cycles can be determined in advance through experiments, and then when performing related operations, the value of the preset parameter is adjusted to not cause the performance of the PCM unit to suffer loss. In this way, due to the dynamic adjustment of the value of the preset parameter, data writing always remains accurate, thereby reducing the error writing rate and improving stability during the entire life cycle of the PCM unit.

[0060] It should also be noted that, in some embodiments, preset parameters related to the write operation include but are not limited to one or more of the following: the pulse duration of the write operation signal received by the word line connected to the PCM unit; the magnitude of the heating current used to heat the PCM unit during the write operation.

[0061] Here, you can combine Figures 1 to 3 As shown, the write operation signal can be a signal on the word line WL during the write operation, and the heating current can be a current I flowing through the variable resistor R during the write operation. cell The size of the heating current can be controlled by the heating pulse. The write operation includes the set operation and the reset operation. The waveform of the write operation signal corresponding to the normal situation (that is, the performance of the PCM unit is not damaged and no adjustment is required) is as follows Figure 2 , heating pulses such as Figure 3 .

[0062] In the embodiment of the present disclosure, the adjustment of the write operation signal may be an adjustment of the pulse duration, such as Figure 2 As shown, the pulse of the setting waveform includes several stages, and the adjustment of the pulse duration can be to adjust the duration of any one or more stages.

[0063] For heating current I cell The adjustment can be an adjustment of the current value, which can be achieved by adjusting the intensity of the heating pulse. The heating pulse can be a voltage pulse or a current pulse, which is not specifically limited here. The voltage pulse can be generated by a voltage generator, and the current pulse can be generated by a current mirror.

[0064] Regarding step S101, in some embodiments, determining the life cycle of the phase change memory unit may include:

[0065] Determine the cumulative number of times the PCM unit is written;

[0066] Determine the life cycle based on the cumulative number of times.

[0067] It should be noted that the write operation performed on the PCM unit includes a set operation and a reset operation. The cumulative number here can be the total number of set operations and reset operations. In some cases, it can also refer to only the number of set operations, or only the number of reset operations, or one set operation and one reset operation are combined as one cycle, or the cumulative number can include not only the count of write operations, but also the count of read operations.

[0068] In the embodiment of the present disclosure, taking the cumulative number referring to the total number of set operations and reset operations as an example, a counter can be used to count the number of write operations, and then the current life cycle of the PCM unit can be determined according to the cumulative number obtained by counting.

[0069] In some embodiments, determining the life cycle according to the accumulated number of times may include:

[0070] If the cumulative number of times does not reach the preset threshold, the life cycle is determined to be in the early stage of the life cycle;

[0071] If the cumulative number reaches a preset threshold, the life cycle is determined to be in the late stage of the life cycle.

[0072] It should be noted that, in the embodiment of the present disclosure, the life cycle of the PCM unit can be divided into an early life cycle and a late life cycle (or referred to as a mid-late life cycle) by using a preset threshold.

[0073] Exemplarily, the preset threshold value may be determined in the following manner: when the PCM unit is operated at a reference value and the operation mode remains unchanged, after the PCM unit is operated cyclically for a certain number of times (recorded as a critical value), the PCM unit suffers from partial performance loss, for example, an error occurs in write data or write fails, etc. The number of cyclic operations may be the number of write operations, the number of read operations, the sum of the number of write operations and read operations, etc. Here, the sum of the number of set operations and reset operations is taken as an example.

[0074] In this way, a critical value is determined, and in order to ensure that effective and reliable treatment measures are taken in a timely manner for the PCM unit with impaired performance, the preset threshold is set to a value less than or equal to the critical value. That is, under normal circumstances, when the cumulative number of times does not reach the preset threshold, the performance of the PCM unit is not impaired, and when the cumulative number of times reaches the preset threshold, the performance of the PCM unit may be impaired. It should also be noted that the impaired performance of the PCM unit is not only related to the number of cyclic writes or reads, but also related to environmental factors, etc., which are not considered normal situations.

[0075] It should also be noted that in a phase change memory, the critical values ​​corresponding to PCM cells at different locations are often different. For example, whether the PCM cell is located in the boundary area of ​​the memory array, the distance between the PCM cell and the peripheral circuit, etc. may have an impact. Usually, the critical values ​​corresponding to multiple PCM cells in a phase change memory satisfy a certain probability distribution, such as a normal distribution.

[0076] After determining the life cycle of the PCM unit, the value of the preset parameter is adjusted according to the life cycle of the PCM unit. As mentioned above, in the embodiment of the present disclosure, the preset parameter mainly refers to the parameter of the write operation, that is, the value of the parameter involved in the write operation on the PCM unit.

[0077] It should be noted that when writing data to a PCM unit, a series of addressing, controlling, driving and other steps are usually included, which will not be described in detail in the embodiment of the present disclosure. Only the adjustment of the preset parameters will be described in detail.

[0078] In some embodiments, adjusting the value of a preset parameter according to the life cycle may include:

[0079] If the life cycle is in the early stage of the life cycle, the value of the preset parameter is set to the baseline value;

[0080] If the life cycle is in the late stage of the life cycle, the value of the preset parameter is set to be greater than the reference value.

[0081] It should be noted that if the current life cycle of the PCM unit is determined to be in the early stage of the life cycle, it means that the probability of performance impairment is very low, and there is no need to adjust the value of the preset parameter, and the reference value can be maintained. Here, the reference value may refer to: a fixed value preset by the manufacturer when writing data to the PCM unit.

[0082] It should also be noted that, in combination with the above description, the preset parameters may include the pulse duration of the write operation signal, and specifically may include the pulse duration of the set operation (which may be recorded as the set pulse) and the pulse duration of the reset operation (which may be recorded as the reset pulse), and the corresponding reference value is recorded as the pulse duration reference value, and specifically may include the set pulse reference value and the reset pulse reference value. For example, the reset pulse reference value is 30ns, and the set pulse reference value is 500ns. The preset parameters may also include the size of the heating current, and specifically may include the size of the heating current of the set operation (which may be recorded as the set current) and the size of the heating current of the reset operation (which may be recorded as the reset current), and the corresponding reference value is recorded as the heating current reference value, and specifically may include the set current reference value and the reset current reference value. For example, the set current reference value is 30μA, and the reset current reference value is 100μA.

[0083] If it is determined that the current life cycle of the PCM unit is in the late stage of the life cycle and the probability of performance impairment is high, the value of the preset parameter needs to be adjusted. Here, based on theoretical and experimental verification, the method adopted is to increase the value of the preset parameter so that the value of the preset parameter is greater than the reference value. That is, in the late stage of the life cycle, when performing a write operation on the PCM unit, the pulse time of the write operation signal is extended, and / or the current value of the heating current is increased.

[0084] It should be noted that in the later period of the life cycle of the PCM unit, the PCM unit shows fatigue due to many cycles of operation. If data is still written to the PCM unit according to the reference value, the phase change material may not be able to change state in time due to insufficient heating time or insufficient heating temperature, thereby causing errors. The disclosed embodiment extends the pulse time of the write operation signal and / or increases the current value of the heating current to ensure that the heating time and / or heating intensity are sufficient for the phase change material to change state and correctly write data.

[0085] For the later stage of the life cycle, in some embodiments, the later stage of the life cycle includes at least one sub-stage, and the method further includes:

[0086] Determine the preset interval to which the cumulative number of times belongs;

[0087] If the accumulated number of times belongs to the nth preset interval, it is determined that the PCM unit is in the nth sub-stage of the late life cycle; wherein n is an integer greater than 0.

[0088] In some embodiments, the value of the preset parameter corresponding to the j-th sub-stage is greater than or equal to the value of the preset parameter corresponding to the ith sub-stage; wherein j and i are both integers greater than 0, and j is greater than i.

[0089] It should be noted that when the PCM unit is in the later stage of its life cycle, in order to ensure that the performance of the PCM unit is not damaged, the value of the preset parameter is set to be larger as it is in the later stage, or when the value of the preset parameter reaches a certain threshold, it will no longer increase and remain unchanged. In other words, the later the life cycle is, the larger the cycle number node is, and the current increase may be linear or increasing, depending on the actual test data.

[0090] Therefore, in addition to the aforementioned preset thresholds, one or more second thresholds can be further set based on actual conditions. For example, N second thresholds are set, where the second threshold is an integer greater than 0, and the first second threshold to the Nth second threshold increase successively, and there are N+1 corresponding preset intervals.

[0091] It should also be noted that the number of cycles usually increases exponentially, and for two adjacent preset intervals, the interval length of the rear preset interval is usually greater than the interval length of the front preset interval.

[0092] In some embodiments, setting the value of the preset parameter to be greater than the reference value may include:

[0093] Determine the step value corresponding to the current sub-stage, superimpose the step value of the current sub-stage with the reference value, and obtain the value of the preset parameter corresponding to the current sub-stage.

[0094] In some embodiments, the step value corresponding to the j-th sub-stage is greater than or equal to the step value corresponding to the ith sub-stage, j and i are both integers greater than 0, and j is greater than i.

[0095] For example, the reference value includes a pulse duration reference value and a heating current reference value corresponding to a write operation signal received by the phase change memory unit, and the step value includes a corresponding pulse duration step value and a heating current step value;

[0096] Determining a step value corresponding to the current sub-stage; superimposing the step value with the reference value to obtain a value of a preset parameter corresponding to the current sub-stage may include:

[0097] Determine the pulse duration step value corresponding to the current sub-stage; superimpose the pulse duration step value with the pulse duration reference value to obtain the pulse duration corresponding to the current sub-stage;

[0098] And / or, determining a heating current step value corresponding to the current sub-stage; superimposing the heating current step value with the heating current reference value to obtain the magnitude of the heating current corresponding to the current sub-stage.

[0099] It should be noted that the increase in the value of the preset parameter can be a step value superimposed on the reference value. In this case, starting from the first sub-stage, the step value can be a value that gradually increases or does not change after increasing to a certain value. For example, the early stage of the life cycle is regarded as the 0th sub-stage, and the late stage of the life cycle starts from the 1st sub-stage. For the write operation signal, the step value of the pulse duration increase (that is, the pulse duration step value, which can be further divided into the set duration step value corresponding to the set operation and the reset duration step value corresponding to the reset operation) can be between 0-100ns, for example, starting from the 0th sub-stage, it is 0 / 50 / 100ns respectively. For the heating current, the heating current step value can be further divided into a set current step value corresponding to the set operation and a reset current step value corresponding to the reset operation. Starting from the first sub-stage, the set current step value can be between 0-10μA, for example, starting from the 0th sub-stage, it is 0 / 2 / 4 / 6 / 8 / 10μA in sequence; the reset current step value can be between 0-10μA, for example, starting from the 0th sub-stage, it is 0 / 10 / 20 / 30 / 10μA in sequence.

[0100] Assume that the first threshold is 100k (thousand), N=2, the first second threshold is 300k, and the second second threshold is 1M (mega), and there are three corresponding preset intervals and sub-stages, namely: the first preset interval with a cumulative number of 100k~300k (corresponding to the first sub-stage, the pulse duration step value, the set current step value and the reset current step value are: 50ns, 2μA, 10μA respectively), the second preset interval with a cumulative number of 300k~1M (corresponding to the second sub-stage, the pulse duration step value, the set current step value and the reset current step value are: 100ns, 4μA, 20μA respectively), and the third preset interval with a cumulative number greater than 1M (corresponding to the third sub-stage, the pulse duration step value, the set current step value and the reset current step value are: 100ns, 6μA, 30μA respectively), wherein the boundary of each preset interval may belong to the previous interval or the next interval, and is not specifically limited here.

[0101] If the cumulative number is less than 100k, it means that the PCM unit is in the early stage of its life cycle (the 0th sub-stage), and there is no need to adjust the value of the preset parameter, or add 0 to the value of the preset parameter. Assume that the set pulse reference value is 500ns, the reset pulse reference value is 30ns, the set current reference value is 30μA, and the reset current reference value is 100μA; if the cumulative number is greater than or equal to 100k and less than or equal to 300k, the corresponding sub-stage is the 1st sub-stage. After adding the corresponding step value on the basis of each reference value, the values ​​of the set pulse, reset pulse, set current, and reset current are: 550ns, 80 ns, 32μA, 110uA; if the cumulative number of times is greater than or equal to 300k and less than or equal to 1M, the corresponding sub-stage is the second sub-stage, then after increasing the corresponding step value on the basis of the benchmark value, the values ​​of the set pulse, reset pulse, set current, and reset current are 600ns, 130ns, 34μA, and 120uA respectively; if the cumulative number of times is greater than 1M, the corresponding sub-stage is the third sub-stage, then after increasing the corresponding step value on the basis of the benchmark value, the values ​​of the set pulse, reset pulse, set current, and reset current are 600ns, 130ns, 36μA, and 130uA respectively.

[0102] In this way, the embodiments of the present disclosure reduce the write error rate and improve the stability in the middle and late stages of the life of the PCM device through optimized write operations, thereby increasing the life of the device.

[0103] In some embodiments, setting the value of the preset parameter to be greater than the reference value may include:

[0104] The second step value corresponding to the current sub-stage is determined, and the value of the preset parameter corresponding to the previous sub-stage is superimposed on the second step value to obtain the value of the preset parameter corresponding to the current sub-stage.

[0105] It should be noted that, in another implementation, the increase in the value of the preset parameter may be a superposition of the second step value corresponding to the current sub-stage on the basis of the preset parameter of the previous sub-stage. In this case, the second step value corresponding to each sub-stage may be the same value or a gradually decreasing value.

[0106] Still assuming that the first threshold is 100k, N=2, the first second threshold is 300k, and the second second threshold is 1M, there are three corresponding preset intervals and sub-stages, namely: the first preset interval with a cumulative number of 100k~300k (corresponding to the first sub-stage, the second step values ​​corresponding to the write pulse, set current, and reset current are: 50ns, 2μA, 10μA, respectively), the second preset interval with a cumulative number of 300k~1M (corresponding to the second sub-stage, the second step values ​​corresponding to the write pulse, set current, and reset current are: 50ns, 2μA, 10μA, respectively), and the third preset interval with a cumulative number greater than 1M (corresponding to the third sub-stage, the second step values ​​corresponding to the write pulse, set current, and reset current are: 50ns, 2μA, 10μA, respectively), wherein the boundary of each preset interval may belong to the previous interval or the next interval, and is not specifically limited here.

[0107] If the cumulative number is less than 100k, it means that the PCM unit is in the early stage of its life cycle (the 0th sub-stage), and there is no need to adjust the value of the preset parameter, or add 0 to the value of the preset parameter. Assume that the set pulse reference value is 500ns, the reset pulse reference value is 30ns, the set current reference value is 30μA, and the reset current reference value is 100μA; if the cumulative number is greater than or equal to 100k and less than or equal to 300k, the corresponding sub-stage is the 1st sub-stage, then after adding the corresponding second step value on the basis of the reference value, the values ​​of the set pulse, reset pulse, set current, and reset current are: 550ns, 80ns, 32μA, respectively. A, 110uA; if the cumulative number of times is greater than or equal to 300k and less than or equal to 1M, the corresponding sub-stage is the second sub-stage, then on the basis of the values ​​of the first sub-stage, after adding the corresponding second step value, the values ​​of the set pulse, reset pulse, set current, and reset current are 600ns, 130ns, 34μA, and 120uA respectively; if the cumulative number of times is greater than 1M, the corresponding sub-stage is the third sub-stage, then on the basis of the values ​​of the second sub-stage, after adding the corresponding second step value, the values ​​of the set pulse, reset pulse, set current, and reset current are 650ns, 180ns, 36μA, and 130μA respectively.

[0108] For example, Figure 7 and Figure 8 A schematic diagram showing a comparison of write operation signals and heating pulses during setting and resetting in a certain sub-stage of the early stage of the life cycle and the late stage of the life cycle.

[0109] It should also be noted that when adjusting the pulse duration or the heating current of the write operation signal, the other may also be adjusted according to actual needs to ensure that the increase in the heating duration or intensity is effective.

[0110] In addition, the aforementioned division of sub-phases and setting of the step value / second step value are exemplary, and the specific values ​​depend on the actual test data of the specific device.

[0111] In short, the disclosed embodiments can gradually increase the pulse time of the write operation signal in the later stage of the life cycle of the PCM device (i.e., PCM unit), the cycle number node can be 100k / 300k / 1M, etc., and the waveform time increase step range can be 0-100ns, and / or, gradually increase the heating current of each stage in the later stage of the device life cycle, the cycle number node can be 100k / 300k / 1M, etc., and the pulse time increase step range can be 0-10μA. Among them, the life cycle parameter refers to the division of the device life cycle, and 100k / 300k / 1M is used as the division point for example. For write operations: the time of the set and reset waveforms increases as the life cycle reaches the later stage, and the step size of each step increase is between 0-100ns, for example, 0 / 50 / 100ns. The current of the set waveform increases as the life cycle reaches the later stage, and the step size of each step increase is between 0-10μA, for example, 0 / 2 / 4 / 6 / 8 / 10μA. The current of the set waveform increases as the life cycle reaches a later stage, and the step size of each increase is between 0-40 μA, for example, 0 / 10 / 20 / 30 / 40 μA.

[0112] In summary, the embodiments of the present disclosure provide an operating method for a phase change memory. At different stages of the life cycle of the PCM, the device characteristics will change with the increase in the number of operations. Therefore, the optimal heating current and pulse time of the write operation actually required in different life cycles are different. By optimizing the pulse time and heating current of the write operation, the best write operation effect can be maintained in different life cycles of the device, thereby reducing the device write error rate and improving the device stability.

[0113] In another embodiment of the present disclosure, see Fig. 9 , which shows a schematic diagram of the composition structure of a control circuit 90 of a phase change memory provided by an embodiment of the present disclosure. Fig. 9 As shown, the circuit 90 includes a first control circuit 901 and a second control circuit 902, wherein:

[0114] A first control circuit 901 is used to determine the life cycle of the phase change memory unit 903;

[0115] The second control circuit 902 is used to adjust the value of a preset parameter according to the life cycle; the preset parameter is a parameter related to the write operation.

[0116] In some embodiments, the preset parameters include at least one of the following: the pulse duration of the write operation signal received by the word line connected to the phase change memory unit; the magnitude of the heating current used to heat the phase change memory unit during the write operation.

[0117] In some embodiments, the second control circuit 902 is configured to set the value of the preset parameter to a reference value if the life cycle is in the early life cycle; and to set the value of the preset parameter to be greater than the reference value if the life cycle is in the late life cycle;

[0118] The reference value includes a pulse duration reference value and a heating current reference value corresponding to a write operation signal received by the phase change memory unit.

[0119] In some embodiments, the second control circuit 902 includes a first pulse generating circuit 9021 and / or a second pulse generating circuit 9022, wherein:

[0120] A first control circuit 901 is used to count the write operation of the phase change memory unit 6013 and generate a first control signal and / or a second control signal according to the counting result;

[0121] A first pulse generating circuit 9021, configured to generate a write operation signal according to a first control signal;

[0122] The second pulse generating circuit 9022 is used to generate a heating pulse signal according to the second control signal.

[0123] It should be noted that the control circuit 90 of the phase change memory is used to execute the steps of the operating method described in any one of the above embodiments.

[0124] It should also be noted that, in order to facilitate understanding of the working process of the circuit 90, Figure 5 and Figure 6 Please continue to refer to Fig.10 , which is an exemplary block diagram of a memory 203 including a memory array 601 and a peripheral circuit 602 provided by an embodiment of the present disclosure. Fig.10 As shown, the memory 203 includes a phase change memory array 601 and a peripheral circuit 602, wherein the memory array 601 is combined with the aforementioned Figure 6 For explanation. Fig.10 As shown, the peripheral circuit 602 may include: a control logic 6021, an address register 6022, a voltage generator 6023, a row decoder / word line driver 6024, a page buffer / sense amplifier circuit 6025, a column decoder / bit line driver / data latch 6026, and a data register / data I / O 6027, wherein;

[0125] The page buffer / sense amplifier circuit 6025 can be configured to read data from the phase change memory array 601 and program (write) data to the phase change memory array 401 according to the control signal from the control logic 6021. In one example, the page buffer / sense amplifier 6025 can store a page of programming data (write data) to be programmed into a page of the phase change memory array 601. In another example, the page buffer / sense amplifier 6025 can perform a program verification operation to ensure that the data has been correctly programmed into the phase change memory cell 4013 coupled to the selected word line. In yet another example, the page buffer / sense amplifier 6025 can also sense a low-power signal representing a data bit stored in the phase change memory cell 6013 from the selected bit line and amplify a small voltage swing to a recognizable logic level in a read operation. In some embodiments, the page buffer / sense amplifier 6025 can include a comparator (e.g., a voltage comparator) to compare a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a predetermined threshold voltage of a memory cell in a "set" state). The column decoder / bit line driver / data latch 6026 may be configured to be controlled by the control logic 6021 and select one or more phase change memory cells 6013 and bit lines. The column decoder / bit line driver / data latch 6026 may be further configured to drive the selected bit line. The column decoder / bit line driver / data latch 6026 may be further configured to drive the bit line 4012 using the bit line voltage generated from the voltage generator 6023. The column decoder / bit line driver / data latch 6026 may be a temporary binary data storage device for storing bits. In some embodiments, the column decoder / bit line driver / data latch 6026 may include a read data latch to temporarily store read data. The data register / data I / O 6027 can be coupled to the page buffer / sense amplifier 6025 and / or the column decoder / bit line driver / data latch 6026, and is configured to direct (route) data input from the data bus 6028 to the desired phase change memory cell 6013 of the phase change storage array 601, and to direct (route) data output from the desired memory cell to the data bus 6028.

[0126] The row decoder / word line driver 6024 may be configured to be controlled by the control logic 6021 and select one or more phase change memory cells 4013 and word lines of the phase change memory array 601. The row decoder / word line driver 6024 may be further configured to drive the selected word line. The row decoder / word line driver 6024 may be further configured to drive the word line using the word line voltage generated from the voltage generator 6023.

[0127] The voltage generator 6023 can be configured to be controlled by the control logic 6021 according to a control signal from the control logic 6021, and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be provided to the phase change memory array 601.

[0128] The control logic 6021 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The control logic 6021 is configured to receive a clock signal, a command signal, an address signal, and a data signal from a host, wherein the command signal is received via a command bus 6029; and the data signal is received via a data bus 6028. In some embodiments, the control logic 6021 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable logic gate array (FPGA), a programmable logic device (PLD), a state machine, a gating logic, a discrete hardware circuit, and other appropriate hardware, firmware, and / or software configured to perform the various functions described.

[0129] On this basis, Fig.11 FIG. 1 is a schematic diagram of a circuit for performing a write operation on a PCM cell. Taking the reset operation as an example, Fig.10 As shown, once the control logic 6021 determines that the command is a reset command, the control logic 6021 triggers the reset operation, leads the word line voltage to the word line WL of the selected phase change memory cell through the word line driver, leads the bit line voltage to the bit line BL of the selected phase change memory through the bit line driver, and then, under the action of the word line voltage and the bit line voltage, the selector of the selected phase change memory cell 6013 is turned on, and then, a current for resetting (converting to amorphous state) is provided to the selected phase change memory (such as provided by the current source I in the figure), so as to perform a reset operation on the selected phase change memory cell. The set operation is similar, and will not be repeated here.

[0130] On this basis (but not limited to Fig.10 and Fig.11 Structure shown), such as Fig. 9As shown, the first control circuit 901 can be integrated in the control logic 6021 to count the received write commands (including reset commands for writing 0 and set commands for writing 1), and one write command corresponds to one write operation. A first control signal for controlling the pulse duration of the write operation signal is generated according to the counting result and the specific type of the current write command (set command or reset command), and / or a heating pulse signal for controlling the heating current is generated.

[0131] The first pulse generating circuit 9021 may be integrated in the voltage generator 6023, and is used to generate a write operation signal based on the control of the first control signal, and transmit the write operation signal to the word line WL. The second pulse generating circuit 9022 may be the aforementioned current source I, and is used to generate a heating pulse signal based on the control of the second control signal, and transmit the heating pulse signal to the PCM unit 6013 through the bit line BL to heat the phase change material in the PCM unit 6013. The current source I may be a current mirror.

[0132] It should also be noted that the circuit 90 provided in the embodiment of the present disclosure is used to implement the operating method in the aforementioned embodiment. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the aforementioned embodiment for understanding, and no further details will be given here.

[0133] In another embodiment of the present disclosure, a phase change memory is provided, comprising the control circuit 90 of the phase change memory as described in any of the above embodiments. In this way, as the value of the preset parameter related to the write operation is dynamically adjusted along with the life cycle of the PCM unit, the error write rate of the PCM unit is reduced, thereby improving the life of the phase change memory.

[0134] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0135] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0136] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0137] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0138] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0139] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0140] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for operating a phase change memory, characterized in that: The phase change memory comprises a plurality of phase change memory cells, and the method comprises: determining a life cycle of the phase change memory unit; According to the life cycle, the value of a preset parameter is adjusted; the preset parameter is a parameter related to the write operation.

2. The operating method according to claim 1, characterized in that: The determining the life cycle of the phase change memory unit comprises: Determining the cumulative number of times the phase change memory unit is written; If the cumulative number does not reach the preset threshold, the life cycle is determined to be in the early stage of the life cycle; If the accumulated number reaches the preset threshold, it is determined that the life cycle is in the late stage of the life cycle.

3. The operating method according to claim 1, characterized in that: The adjusting the value of the preset parameter according to the life cycle includes: If the life cycle is in the early stage of the life cycle, the value of the preset parameter is set as a reference value; If the life cycle is in the late life cycle, the value of the preset parameter is set to be greater than the reference value.

4. The operating method according to claim 3, characterized in that: The late stage of the life cycle includes at least one sub-stage, wherein the value of the preset parameter corresponding to the j-th sub-stage is greater than or equal to the value of the preset parameter corresponding to the ith sub-stage, j and i are both integers greater than 0, and j is greater than i.

5. The operating method according to claim 4, characterized in that: The setting of the value of the preset parameter to be greater than the reference value comprises: Determine a step value corresponding to the current sub-stage; superimpose the step value and the reference value to obtain a value of the preset parameter corresponding to the current sub-stage.

6. The operating method according to claim 5, characterized in that: The step value corresponding to the j-th sub-stage is greater than or equal to the step value corresponding to the ith sub-stage.

7. The operating method according to claim 5, characterized in that: The reference value includes a pulse duration reference value and a heating current reference value corresponding to the write operation signal received by the phase change memory unit, and the step value includes a corresponding pulse duration step value and a heating current step value; Determining the step value corresponding to the current sub-stage; The step value is superimposed on the reference value to obtain the value of the preset parameter corresponding to the current sub-stage, including: Determine the pulse duration step value corresponding to the current sub-stage; superimpose the pulse duration step value with the pulse duration reference value to obtain the pulse duration corresponding to the current sub-stage; And / or, determining a heating current step value corresponding to the current sub-stage; superimposing the heating current step value with the heating current reference value to obtain the magnitude of the heating current corresponding to the current sub-stage.

8. A control circuit of a phase change memory, characterized in that: The steps for executing the operating method according to any one of claims 1 to 7 include: A first control circuit, used to determine the life cycle of the phase change memory unit; The second control circuit is used to adjust the value of a preset parameter according to the life cycle; the preset parameter is a parameter related to the write operation.

9. The circuit according to claim 8, characterized in that The second control circuit is configured to: if the life cycle is in the early stage of the life cycle, set the value of the preset parameter to a reference value; and if the life cycle is in the late stage of the life cycle, set the value of the preset parameter to be greater than the reference value; The reference values ​​include a pulse duration reference value and a heating current reference value corresponding to a write operation signal received by the phase change memory unit.

10. A phase change memory, characterized in that: A control circuit comprising the phase change memory as claimed in claim 8 or 9.

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