Chip capacitor packaging structure and packaging method thereof

Abstract

The invention discloses a chip capacitor packaging structure and a packaging method thereof, the chip capacitor packaging structure comprises a capacitor main body structure, a first electrode structure and a second electrode structure, the capacitor main body structure comprises a plurality of ceramic interlayers, a first electrode plate, a second electrode plate, a first insulating layer, a second insulating layer and a packaging shell, a plurality of ceramic interlayers are arranged on the capacitor main body structure, first electrode plates and second electrode plates are arranged among the plurality of ceramic interlayers at intervals, first insulating layers are arranged on the upper side and the lower side of the capacitor main body structure, and second insulating layers are arranged on the front side and the rear side of the capacitor main body structure. Through the heat dissipation grooves in the ceramic interlayers, heat generated in the surface-mounted capacitor during power-on use is conveniently dissipated outwards, and meanwhile, through the reinforcing strips on the inner sides of the heat dissipation grooves, the stability of the overall structure of the heat dissipation grooves can be enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip capacitors, and in particular to a chip capacitor packaging structure and a packaging method thereof. Background Art

[0002] Chip capacitors are a type of capacitor material. The full name of chip capacitors is: multi-layer (laminated, stacked) chip ceramic capacitors, also known as chip capacitors, chip capacitors, chip capacitors, chip capacitors are currently a common component with a relatively large amount of use. This type of capacitor is formed by alternating and sintering multiple internal electrode layers and filling dielectrics. It is a stacked capacitor. This type of capacitor connects the positive and negative electrodes through multiple internal electrode layers in the filling dielectric material. It has the advantages of small size and high voltage resistance, and can replace traditional aluminum electrolytic capacitors and tantalum electrolytic capacitors in some fields.

[0003] The chip capacitors currently on the market are formed by alternating and sintering multiple layers of internal electrode layers and filling dielectrics. When the chip capacitor is powered on, heat is continuously generated inside the chip capacitor. Therefore, the closer the heat is to the center of the chip capacitor, the more difficult it is to dissipate. Therefore, a chip capacitor packaging structure and a packaging method thereof are provided to solve the above problems. Summary of the invention

[0004] In order to solve the problems raised in the above background technology, the technical solution adopted by the present invention to solve the technical problems is: a chip capacitor packaging structure and a packaging method thereof, which include: a capacitor main structure, a first electrode structure and a second electrode structure, the capacitor main structure includes a ceramic partition, a first electrode sheet, a second electrode sheet, a first insulating layer, a second insulating layer, and a packaging shell, the number of the ceramic partitions is set, and the first electrode sheet and the second electrode sheet are arranged between the ceramic partitions, the first insulating layer is arranged on the upper and lower sides of the capacitor main structure, and the second insulating layer is arranged on the front and back sides of the capacitor main structure, the first insulating layer and the second insulating layer are covered with a packaging shell on the outside, and the heat dissipation structure is arranged inside the ceramic partitions.

[0005] As a preferred technical solution of the present invention, the heat dissipation structure includes a heat dissipation slot and a reinforcement strip, the heat dissipation slot is opened through the side of the ceramic interlayer, the reinforcement strip is arranged inside the heat dissipation slot, and the reinforcement strip is a cross structure.

[0006] As a preferred technical solution of the present invention, the first insulating layer and the second insulating layer are both made of epoxy resin, and the second insulating layer is provided with a heat dissipation hole facing the heat dissipation groove.

[0007] As a preferred technical solution of the present invention, the first electrode structure includes a first external electrode, a first nickel layer, and a first outer plating layer. The first external electrode is connected to the first electrode sheet. The first nickel layer is arranged on the outside of the first external electrode. The first outer plating layer is arranged on the outside of the first nickel layer.

[0008] As a preferred technical solution of the present invention, the second electrode structure includes a second external electrode, a second nickel layer, and a second outer plating layer. The second external electrode is connected to the second electrode sheet. A second nickel layer is arranged on the outside of the second external electrode. A second outer plating layer is arranged on the outside of the second nickel layer.

[0009] As a preferred technical solution of the present invention, the first external electrode and the second external electrode are both provided with double card slots relatively close to the outside.

[0010] As a preferred technical solution of the present invention, double card strips are provided on the inner sides of both ends of the packaging shell, and the double card strips are clamped in the double card slots.

[0011] As a preferred technical solution of the present invention, the first external electrode and the outer sides of the first nickel layer are both uneven surfaces.

[0012] As a preferred technical solution of the present invention, the second external electrode and the outer side of the second nickel layer are both uneven surfaces.

[0013] A packaging method for a chip capacitor packaging structure comprises the following steps: Step 1: Distribute the first electrode sheet and the second electrode sheet between a plurality of ceramic interlayers, and press and bond them so that the first external electrode is connected to the first electrode sheet, and the second external electrode is connected to the second electrode sheet; Step 2: Lay the first insulating layer and the second insulating layer on the upper and lower sides and the front and rear sides of the capacitor main structure respectively, and seal the packaging shell outside the first insulating layer and the second insulating layer; Step 3: Cover the first outer electrode with a first nickel layer, and cover the second outer electrode with a second nickel layer. Similarly, cover the first nickel layer with a first outer plating layer, and cover the second nickel layer with a second outer plating layer.

[0014] The present invention has the following advantages: the first insulating layer and the second insulating layer are respectively laid on the upper and lower sides and the front and rear sides of the capacitor main structure, thereby enhancing the protection and insulation of the capacitor main structure; The heat dissipation groove in the ceramic interlayer can facilitate the heat generated inside the chip capacitor when it is powered on to be dissipated outwards. At the same time, the reinforcement strip on the inside of the heat dissipation groove can enhance the stability of the overall structure of the heat dissipation groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1It is a structural schematic diagram of a preferred embodiment of the present invention; Figure 2 is a schematic cross-sectional view of a preferred embodiment of the present invention; Figure 3 It is a preferred embodiment of the present invention Figure 2 Schematic diagram of local split structure; Figure 4 It is a preferred embodiment of the present invention Figure 2 The structure shows the enlarged intention of A; Figure 5 is a schematic diagram of the ceramic interlayer structure of a preferred embodiment of the present invention; Figure 6 It is a schematic diagram of the second insulating layer structure of a preferred embodiment of the present invention.

[0016] Explanation of the accompanying drawings: 1. Capacitor main structure; 101. Ceramic interlayer; 1011. Heat dissipation groove; 1012. Reinforcement strip; 102. First electrode sheet; 103. Second electrode sheet; 104. First insulating layer; 105. Second insulating layer; 1051. Heat dissipation hole; 106. Packaging shell; 1061. Double card strip; 2. First electrode structure; 201. First external electrode; 2011. Double card slot; 202. First nickel layer; 203. First outer plating layer; 3. Second electrode structure; 301. Second external electrode; 302. Second nickel layer; 303. Second outer plating layer. DETAILED DESCRIPTION

[0017] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0018] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0019] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Please refer to Figure 1-Figure 6 The present invention discloses a chip capacitor packaging structure and a packaging method thereof, comprising: a capacitor main body structure 1, a first electrode structure 2 and a second electrode structure 3, wherein the capacitor main body structure 1 comprises a ceramic interlayer 101, a first electrode sheet 102, a second electrode sheet 103, a first insulating layer 104, a second insulating layer 105 and a packaging shell 106, wherein a plurality of ceramic interlayers 101 are provided, wherein the first electrode sheet 102 and the second electrode sheet 103 are arranged between the plurality of ceramic interlayers 101, the first insulating layer 104 is arranged on the upper and lower sides of the capacitor main body structure 1, the second insulating layer 105 is arranged on the front and rear sides of the capacitor main body structure 1, the first insulating layer 104 and the second insulating layer 105 are covered with a packaging shell 106 on the outside, and a heat dissipation structure is arranged inside the plurality of ceramic interlayers 101.

[0021] Combination Figure 5 As shown, the heat dissipation structure includes a heat dissipation groove 1011 and a reinforcement strip 1012. The reinforcement strip 1012 can enhance the compressive strength of the inner side of the heat dissipation groove 1011 and enhance the stability of the structure of the ceramic interlayer 101. The heat dissipation groove 1011 is opened through the side of the ceramic interlayer 101, and the reinforcement strip 1012 is arranged on the inner side of the heat dissipation groove 1011. The reinforcement strip 1012 is a cross structure.

[0022] Combination Figure 3 and Figure 6 As shown, the first insulating layer 104 and the second insulating layer 105 are both epoxy resins, and the second insulating layer 105 is provided with a heat dissipation hole 1051 facing the heat dissipation groove 1011. The heat dissipation hole 1051 makes it easier for the heat dissipation groove 1011 inside the ceramic interlayer 101 to dissipate heat outward. The first electrode structure 2 includes a first external electrode 201, a first nickel layer 202, and a first outer plating layer 203. The first external electrode 201 is connected to the first electrode sheet 102, and the first nickel layer 202 is arranged on the outer side of the first external electrode 201, and the first outer plating layer 203 is arranged on the outer side of the first nickel layer 202. The second electrode structure 3 includes a second external electrode 301, a second nickel layer 302, and a second outer plating layer 303. The second external electrode 301 is connected to the second electrode sheet 103, and the second nickel layer 302 is arranged on the outer side of the second external electrode 301, and the second outer plating layer 303 is arranged on the outer side of the second nickel layer 302.

[0023] Combination Figure 4As shown, the first external electrode 201 and the second external electrode 301 are both provided with double card slots 2011 relatively close to the outside, and double card strips 1061 are provided on the inner sides of both ends of the packaging shell 106, so as to facilitate the sealing of the packaging shell 106 on the capacitor main structure 1, and the double card strips 1061 are connected to the inside of the double card slots 2011, and the outer sides of the first external electrode 201 and the first nickel layer 202 are both uneven surfaces, and the outer sides of the second external electrode 301 and the second nickel layer 302 are both uneven surfaces. A packaging method for a chip capacitor packaging structure comprises the following steps: Step 1: Distribute the first electrode sheet 102 and the second electrode sheet 103 between a plurality of ceramic interlayers 101 and press and bond them so that the first external electrode 201 is connected to the first electrode sheet 102 and the second external electrode 301 is connected to the second electrode sheet 103; Step 2: Lay the first insulating layer 104 and the second insulating layer 105 on the upper and lower sides and the front and rear sides of the capacitor main structure 1 respectively, and package the packaging shell 106 outside the first insulating layer 104 and the second insulating layer 105; Step 3: Coat the first outer electrode 201 with the first nickel layer 202 and the second outer electrode 301 with the second nickel layer 302. Similarly, attach the first outer plating layer 203 to the outer side of the first nickel layer 202 and the second outer plating layer 303 to the outer side of the second nickel layer 302.

[0024] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the attached claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved.

[0025] Other parts of the present invention not described in detail belong to the prior art and will not be described in detail here.

[0026] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip capacitor packaging structure, comprising: A capacitor main structure (1), a first electrode structure (2) and a second electrode structure (3), characterized in that the capacitor main structure (1) comprises a ceramic interlayer (101), a first electrode sheet (102), a second electrode sheet (103), a first insulating layer (104), a second insulating layer (105) and a packaging shell (106); the number of the ceramic interlayers (101) is set to be a plurality, the first electrode sheet (102) and the second electrode sheet (103) are arranged between the plurality of the ceramic interlayers (101); the first insulating layer (104) is arranged on the upper and lower sides of the capacitor main structure (1); the second insulating layer (105) is arranged on the front and rear sides of the capacitor main structure (1); the first insulating layer (104) and the second insulating layer (105) are covered with a packaging shell (106) on the outside; and a heat dissipation structure is arranged inside the plurality of the ceramic interlayers (101).

2. A chip capacitor packaging structure as claimed in claim 1, characterized in that: The heat dissipation structure comprises a heat dissipation groove (1011) and a reinforcement strip (1012); the heat dissipation groove (1011) is opened through the side of the ceramic interlayer (101); the reinforcement strip (1012) is arranged inside the heat dissipation groove (1011); and the reinforcement strip (1012) is a cross structure.

3. A chip capacitor packaging structure as claimed in claim 1, characterized in that: The first insulating layer (104) and the second insulating layer (105) are both made of epoxy resin, and the second insulating layer (105) is provided with a heat dissipation hole (1051) facing the heat dissipation groove (1011).

4. A chip capacitor packaging structure as claimed in claim 1, characterized in that: The first electrode structure (2) comprises a first external electrode (201), a first nickel layer (202), and a first outer plating layer (203); the first external electrode (201) is connected to the first electrode sheet (102); the first nickel layer (202) is arranged outside the first external electrode (201); and the first outer plating layer (203) is arranged outside the first nickel layer (202).

5. A chip capacitor packaging structure as claimed in claim 1, characterized in that: The second electrode structure (3) comprises a second external electrode (301), a second nickel layer (302), and a second outer plating layer (303); the second external electrode (301) is connected to the second electrode sheet (103); the second nickel layer (302) is arranged outside the second external electrode (301); and the second outer plating layer (303) is arranged outside the second nickel layer (302).

6. A chip capacitor packaging structure as claimed in claim 4, characterized in that: The first external electrode (201) and the second external electrode (301) are both provided with double card slots (2011) relatively close to the outside.

7. A chip capacitor packaging structure as claimed in claim 1, characterized in that: Double card strips (1061) are provided on the inner sides of both ends of the packaging shell (106), and the double card strips (1061) are snap-connected to the inside of the double card slots (2011).

8. A chip capacitor packaging structure and packaging method thereof as claimed in claim 4, characterized in that: The outer sides of the first external electrode (201) and the first nickel layer (202) are both uneven surfaces.

9. A chip capacitor packaging structure as claimed in claim 5, characterized in that: The outer sides of the second external electrode (301) and the second nickel layer (302) are both uneven surfaces.

10. A packaging method for a chip capacitor packaging structure according to any one of claims 1 to 9, characterized in that: The following steps are involved: Step 1: Distribute the first electrode sheet (102) and the second electrode sheet (103) between a plurality of ceramic interlayers (101) at intervals, and perform compression bonding so that the first external electrode (201) is connected to the first electrode sheet (102), and the second external electrode (301) is connected to the second electrode sheet (103); Step 2: laying the first insulating layer (104) and the second insulating layer (105) on the upper and lower sides and the front and rear sides of the capacitor main structure (1), and encapsulating the packaging shell (106) on the outside of the first insulating layer (104) and the second insulating layer (105); Step 3: The first external electrode (201) is coated with a first nickel layer (202), and the second external electrode (301) is coated with a second nickel layer (302). Similarly, the first external plating layer (203) is attached to the outside of the first nickel layer (202), and the second external plating layer (303) is attached to the outside of the second nickel layer (302).

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