Method for monitoring filling of interlayer dielectric layer of static random access memory (SRAM)
By forming a pseudo-active region and a pseudo-gate structure on the substrate, simulating a complex trench structure, the problem of hollows in the dielectric layer filling between SRAM layers is solved, and the monitoring and effective filling of complex filling structures is realized, which is suitable for a variety of purposes Craft platform.
Patent Information
- Application Number
- CN202411382657.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-03
AI Technical Summary
The prior art cannot effectively monitor and solve the problem of voids in complex structures in SRAM interlayer dielectric layer filling, especially at the junction of grooves and active regions between adjacent gates.
By forming a dummy active region and a dummy gate structure on the substrate, a complex trench structure that needs to be filled is simulated, and the width and spacing of the dummy active region and a dummy gate are adjusted to monitor the filling effect of the interlayer dielectric layer. And verify the filling process window of dielectric layers between different layers.
It realizes effective monitoring of complex fill structures, ensures full filling of interlayer dielectric layers, is suitable for a variety of process platforms, and avoids device connection problems.
Smart Images
Figure CN119252754A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for monitoring the filling of an SRAM interlayer dielectric layer. Background Art
[0002] Static random access memory (SRAM) is a memory with static access function. It can save the data stored inside without refreshing the circuit. It also has the advantages of large capacity and faster reading speed than dynamic random access memory (DRAM). Static random access memory has the advantages of high speed, low power consumption and compatibility with standard processes. It is widely used in PC, personal communication, consumer electronics (smart cards, digital cameras, multimedia players) and other fields.
[0003] In the SRAM manufacturing process, the narrow groove area between adjacent gates (such as Figure 1 Yellow circle), and the boundary area between shallow trench isolation and active area (such as Figure 2 There are depressions (gaps) in all of the areas (in the yellow circle). The interlayer dielectric layer fills the grooves between adjacent gates, as well as fills and covers the shallow trench isolation and active area. After filling, there is a risk of voids in the corresponding depressions. This void is very close to the contact hole. If the critical dimension of the contact hole is larger or the active area is offset a little, the barrier layer and metal plug in the contact hole will not be filled well, which will eventually lead to problems with device connection. The current platform does not monitor the filling effect of the interlayer dielectric layer of such a complex structure as the SRAM area, and is unable to monitor whether there are voids in the SRAM at locations similar to the above depressions. Summary of the invention
[0004] The purpose of the present invention is to provide a method for monitoring the filling of an SRAM interlayer dielectric layer. The present invention can monitor complex filling structures, superimpose the two factors of the trench depth-to-width ratio between adjacent pseudo gates and the depression at the junction of the pseudo active area and the shallow trench isolation, and can also verify the filling process windows of different interlayer dielectric layers based on the structure.
[0005] The present invention provides a method for monitoring the filling of an SRAM interlayer dielectric layer, comprising:
[0006] Providing a substrate, forming a dummy active region structure in the substrate, wherein the dummy active region structure comprises a plurality of dummy active regions arranged in parallel along a first direction, and adjacent dummy active regions are spaced apart by shallow trench isolation;
[0007] A dummy gate structure is formed above the substrate, wherein the dummy gate structure includes a plurality of dummy gates arranged in parallel along a second direction; the dummy gate structure spans the dummy active area structure and the shallow trench isolation; and the first direction is perpendicular to the second direction;
[0008] By adjusting and setting the width of the dummy active region and / or the distance between adjacent dummy active regions, as well as the width of the dummy gate and / or the distance between adjacent dummy gates, a trench structure to be filled by the interlayer dielectric layer is simulated.
[0009] Furthermore, the pseudo active area structure includes multiple pseudo active area groups, each of the pseudo active area groups includes multiple pseudo active areas, the spacing between adjacent pseudo active areas in each pseudo active area group is equal, the widths of the pseudo active areas of each pseudo active area group are equal, and the spacing between adjacent pseudo active areas of each pseudo active area group gradually decreases or increases.
[0010] Furthermore, the interval between adjacent dummy active areas of each dummy active area group varies in the range of 0.30 μm to 0.10 μm.
[0011] Furthermore, the pseudo gate structure includes multiple pseudo gate groups, each of the pseudo gate groups includes multiple pseudo gates, the spacing between adjacent pseudo gates in each pseudo gate group is equal, the widths of the pseudo gates of each pseudo gate group are equal, and the spacing between adjacent pseudo gates of each pseudo gate group gradually decreases or increases.
[0012] Furthermore, the interval between adjacent dummy gates of each dummy gate group varies in the range of 0.52 μm to 0.14 μm.
[0013] Furthermore, the dummy active region structure, the dummy gate structure and the shallow trench isolation are separately manufactured on a wafer bare die.
[0014] Furthermore, the test structure in the SRAM includes: the pseudo active region structure, the pseudo gate structure and the shallow trench isolation, and the test structure and the formal storage unit of the SRAM are manufactured on the same wafer.
[0015] Furthermore, the storage unit is manufactured in the storage area of the substrate, and the test structure is manufactured in the test area of the substrate; the storage unit includes a gate and an active area which are actually used for storage.
[0016] Furthermore, the active region of the storage region and the dummy active region of the test region are formed in the same ion implantation process, and the gate of the storage region and the dummy gate of the test region are formed in the same polysilicon deposition process.
[0017] Furthermore, there is a height difference between the dummy active area and the shallow trench isolation, and the height difference is greater at the junction of the two to form a depression.
[0018] Compared with the prior art, the present invention has the following beneficial effects:
[0019] The present invention provides a method for monitoring the filling of an SRAM interlayer dielectric layer, comprising: providing a substrate, forming a pseudo active area structure in the substrate, the pseudo active area structure comprising a plurality of pseudo active areas arranged in parallel along a first direction, and adjacent pseudo active areas are spaced by shallow trench isolation; forming a pseudo gate structure above the substrate, the pseudo gate structure comprising a plurality of pseudo gates arranged in parallel along a second direction; the pseudo gate structure spans the pseudo active area structure and the shallow trench isolation; the first direction and the second direction are perpendicular; by adjusting and setting the pseudo active area width and / or the spacing between adjacent pseudo active areas, as well as the pseudo gate width and / or the spacing between adjacent pseudo gates, a complex trench structure to be filled in the interlayer dielectric layer is simulated. The present invention can monitor complex filling structures, superimpose the two factors of the trench depth-to-width ratio between adjacent pseudo gates and the depression at the junction of the pseudo active area and the shallow trench isolation, and can also verify the filling process window of different interlayer dielectric layers based on the structure, and is suitable for a variety of process platforms. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 Schematic diagram of voids appearing in the interlayer dielectric layer when filling the narrow groove area between adjacent gates in SRAM.
[0021] Figure 2 Schematic diagram of the depression at the junction of shallow trench isolation and active area in SRAM.
[0022] Figure 3 The present invention is a flowchart of a method for monitoring the filling of an SRAM interlayer dielectric layer according to an embodiment of the present invention.
[0023] Figure 4 FIG. 4 is a schematic top view of a portion of a dummy active region and a dummy gate according to an embodiment of the present invention.
[0024] Figure 5 Schematic diagram of a top view of a dummy active region structure and a dummy gate structure according to an embodiment of the present invention.
[0025] The reference numerals are as follows:
[0026] A-pseudo active area; B-pseudo gate; C-shallow trench isolation. DETAILED DESCRIPTION
[0027] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0028] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.
[0029] The embodiment of the present invention provides a method for monitoring the filling of an SRAM interlayer dielectric layer, such as Figures 3 to 5 As shown, including:
[0030] Step S1, providing a substrate, forming a dummy active region structure in the substrate, wherein the dummy active region structure comprises a plurality of dummy active regions A arranged in parallel along a first direction, and adjacent dummy active regions A are separated by shallow trench isolations C;
[0031] Step S2, forming a dummy gate structure on the substrate, the dummy gate structure comprising a plurality of dummy gates B arranged in parallel along the second direction; the dummy gate structure spans the dummy active area structure and the shallow trench isolation; the first direction is perpendicular to the second direction;
[0032] Step S3: Simulate the trench structure to be filled in the interlayer dielectric layer by adjusting the width of the dummy active region A and / or the distance between adjacent dummy active regions A, as well as the width of the dummy gate B and / or the distance between adjacent dummy gates.
[0033] The substrate provides a process platform for forming the SRAM. The material of the substrate may be silicon, germanium or silicon germanium. The substrate may also be silicon on insulator (SOI), germanium on insulator (GeOI) or silicon germanium on insulator (SiGeOI). In this embodiment, the material of the substrate is, for example, single crystal silicon. The first direction is, for example, the Y direction, and the second direction is, for example, the X direction.
[0034] The pseudo active area A and the shallow trench isolation C are expected to be flush, but under normal circumstances, there is a height difference between the two, and the difference is greater at the junction of the two (such as ac and bd), which will form a depression. The junction with the depression is relatively difficult to fill. A number of pseudo gates B arranged in parallel along the second direction are formed above the pseudo active area A and the shallow trench isolation C of the substrate. The pseudo gates B have a certain height, and the interlayer dielectric layer fills the trenches (gaps) between adjacent pseudo gates B. The filling of the interlayer dielectric layer is affected by the trench depth-to-width ratio between adjacent pseudo gates B and the depression at the junction of the pseudo active area A and the shallow trench isolation C (such as ac and bd).
[0035] In the present invention, the pseudo active area structure and the pseudo gate structure are vertically arranged, and the width of the pseudo active area A in the pseudo active area structure and / or the spacing between adjacent pseudo active areas can be adjusted, and the width of the pseudo gate B in the pseudo gate structure and / or the spacing between adjacent pseudo gates can be adjusted. In this way, it is possible to better monitor complex active areas and gate structures similar to SRAM, that is, complex filling structures (such as grooves), superimposing the trench depth-to-width ratio between adjacent pseudo gates B and the depression at the junction of the pseudo active area A and the shallow trench isolation C. The filling process windows of different interlayer dielectric layers can also be verified based on the structure, and it is suitable for a variety of process platforms.
[0036] like Figure 5 As shown, the width of the pseudo active area A in the pseudo active area structure and / or the spacing between adjacent pseudo active areas can be adjusted. In one example, in the pseudo active area structure, the width of all pseudo active areas A can be set to a fixed value (e.g., 0.14 μm), which can be equal to the actual active area width in the SRAM product to simulate the actual active area. The pseudo active area structure includes a plurality of pseudo active area groups, each pseudo active area group includes a plurality of pseudo active areas A, the spacing between adjacent pseudo active areas A in each pseudo active area group is equal, the width of the pseudo active areas A of each pseudo active area group is equal, and the spacing between adjacent pseudo active areas A of each pseudo active area group gradually decreases or gradually increases. For example, the pseudo active area structure includes 10 pseudo active area groups, each pseudo active area group includes 10 pseudo active areas A; the width of the pseudo active area in each pseudo active area group is 0.14 μm; the first pseudo active area group includes 10 pseudo active areas, and the spacing between adjacent active areas in the first pseudo active area group is 0.30 μm; the second pseudo active area group includes 10 pseudo active areas, and the spacing between adjacent pseudo active areas in the second group is 0.28 μm; and so on, the spacing between adjacent pseudo active areas in different groups varies from 0.30 μm to 0.10 μm, and 10 groups can be set, and the spacing between adjacent pseudo active areas in each group is 0.02 μm per level, and gradually decreases from 0.30 μm to 0.10 μm.
[0037] In another example, the widths of the dummy active regions A in the same dummy active region group may be set to be equal, but the widths of the dummy active regions A in different groups may be unequal, and the corresponding widths are configured as needed.
[0038] It should be understood that the width of the dummy active region and / or the distance between adjacent dummy active regions in the present invention can be arbitrarily set according to actual needs without limitation. The numerical examples given above are only for better understanding and do not constitute a limitation.
[0039] The dummy gate width and / or the spacing between adjacent dummy gates in the dummy gate structure can be adjusted. The dummy gate structure includes a plurality of dummy gate groups, each dummy gate group includes a plurality of dummy gates B, the spacing between adjacent dummy gates B in each dummy gate group is equal, the width of the dummy gates of each dummy gate group is equal, and the spacing between adjacent dummy gates of each dummy gate group gradually decreases or gradually increases. In one example, in the dummy gate structure, the width of all dummy gates can be set to a fixed value (e.g., 0.33 μm), which can be equal to the actual gate width in the SRAM product to simulate the actual gate. For example, each group includes 10 dummy gates, and the spacing between adjacent dummy gates in each group is equal; the spacing between adjacent dummy gates of different groups gradually decreases. For example, the width of the dummy gates in each group is 0.33μm; the first group includes 10 dummy gates, and the spacing between adjacent dummy gates in the first group is 0.52μm; the second group includes 10 dummy gates, and the spacing between adjacent dummy gates in the second group is 0.50μm; and so on, the spacing between adjacent dummy gates in different groups varies in the range of 0.52μm to 0.14μm, and 19 groups can be set, and the spacing between adjacent dummy gates in each group is 0.02μm per level, gradually decreasing from 0.52μm to 0.14μm.
[0040] In another example, the widths of the dummy gates B in the same dummy gate group may be set equal, but the widths of the dummy gates B in different groups may be unequal, and the corresponding widths may be configured as needed. It should be understood that the dummy gate width and / or the spacing between adjacent dummy gates in the present invention may be arbitrarily set according to actual needs without limitation, and the numerical examples given above are only for better understanding and do not constitute a limitation.
[0041] In the present invention, the test structure in the SRAM includes: the vertically arranged pseudo active region structure and pseudo gate structure, and shallow trench isolation. In one example, the test structure can be made separately on a wafer bare chip (blank chip), specifically used to study the filling process window of the interlayer dielectric layer, for occasions with urgent and large-scale memory trench filling research needs.
[0042] In another example, the test structure can also be made together with the formal SRAM product on the same wafer, and the storage cell of the storage area and the test structure of the test area are made on the same substrate, and the test structure can be made in the surrounding area of the storage cell. The storage cell includes a gate and an active area that are actually used for storage. The active area of the storage area and the pseudo active area A of the test area are formed in the same ion implantation process, and the gate of the storage area and the pseudo gate B of the test area are formed in the same polysilicon deposition process. In this way, in the same wafer process, the formal SRAM product and the SRAM test structure for trench filling are obtained at the same time, killing two birds with one stone. Polysilicon can be formed by any one of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or metal organic chemical vapor deposition (MOCVD) and other suitable processes.
[0043] In summary, the present invention provides a method for monitoring the filling of an SRAM interlayer dielectric layer, comprising: providing a substrate, forming a pseudo active area structure in the substrate, the pseudo active area structure comprising a plurality of pseudo active areas arranged in parallel along a first direction, and adjacent pseudo active areas are spaced by shallow trench isolation; forming a pseudo gate structure above the substrate, the pseudo gate structure comprising a plurality of pseudo gates arranged in parallel along a second direction; the pseudo gate structure spans the pseudo active area structure and the shallow trench isolation; the first direction and the second direction are perpendicular; by adjusting and setting the pseudo active area width and / or the spacing between adjacent pseudo active areas, as well as the pseudo gate width and / or the spacing between adjacent pseudo gates, a complex trench structure to be filled in the interlayer dielectric layer is simulated. The present invention can monitor complex filling structures, superimpose the two factors of the trench depth-to-width ratio between adjacent pseudo gates and the depression at the junction of the pseudo active area and the shallow trench isolation, and can also verify the filling process window of different interlayer dielectric layers based on the structure, and is suitable for a variety of process platforms.
[0044] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0045] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for monitoring the filling of an SRAM interlayer dielectric layer, characterized in that: include: Providing a substrate, forming a dummy active region structure in the substrate, wherein the dummy active region structure comprises a plurality of dummy active regions arranged in parallel along a first direction, and adjacent dummy active regions are spaced apart by shallow trench isolation; forming a dummy gate structure above the substrate, wherein the dummy gate structure comprises a plurality of dummy gates arranged in parallel along a second direction; The dummy gate structure spans the dummy active area structure and the shallow trench isolation; the first direction is perpendicular to the second direction; By adjusting and setting the width of the dummy active region and / or the distance between adjacent dummy active regions, as well as the width of the dummy gate and / or the distance between adjacent dummy gates, a trench structure to be filled by the interlayer dielectric layer is simulated.
2. The method for monitoring the filling of an SRAM interlayer dielectric layer according to claim 1, characterized in that: The pseudo active area structure includes multiple pseudo active area groups, each of the pseudo active area groups includes multiple pseudo active areas, the spacing between adjacent pseudo active areas in each pseudo active area group is equal, the widths of the pseudo active areas in each pseudo active area group are equal, and the spacing between adjacent pseudo active areas in each pseudo active area group gradually decreases or increases.
3. The method for monitoring the filling of the SRAM interlayer dielectric layer as claimed in claim 2, characterized in that: The interval between adjacent dummy active regions of each dummy active region group varies in the range of 0.30 μm to 0.10 μm.
4. The method for monitoring the filling of an SRAM interlayer dielectric layer according to claim 1, characterized in that: The dummy gate structure includes multiple dummy gate groups, each of the dummy gate groups includes multiple dummy gates, the spacing between adjacent dummy gates in each dummy gate group is equal, the widths of the dummy gates in each dummy gate group are equal, and the spacing between adjacent dummy gates in each dummy gate group gradually decreases or increases.
5. The method for monitoring the filling of an SRAM interlayer dielectric layer as claimed in claim 4, characterized in that: The interval between adjacent dummy gates of each dummy gate group varies in the range of 0.52 μm to 0.14 μm.
6. The method for monitoring the filling of an SRAM interlayer dielectric layer according to any one of claims 1 to 5, characterized in that: The pseudo active region structure, the pseudo gate structure and the shallow trench isolation are manufactured separately on a wafer bare die.
7. The method for monitoring the filling of an SRAM interlayer dielectric layer according to any one of claims 1 to 5, characterized in that: The test structure in the SRAM includes: the pseudo active region structure, the pseudo gate structure and the shallow trench isolation. The test structure and the formal storage unit of the SRAM are manufactured on the same wafer.
8. The method for monitoring the filling of an SRAM interlayer dielectric layer as claimed in claim 7, characterized in that: The storage unit is manufactured in the storage area of the substrate, and the test structure is manufactured in the test area of the substrate; the storage unit includes a gate and an active area which are actually used for storage.
9. The method for monitoring the filling of an SRAM interlayer dielectric layer as claimed in claim 8, characterized in that: The active region of the storage region and the dummy active region of the test region are formed in the same ion implantation process, and the gate of the storage region and the dummy gate of the test region are formed in the same polysilicon deposition process.
10. The method for monitoring the filling of an SRAM interlayer dielectric layer according to claim 1, characterized in that: There is a height difference between the dummy active area and the shallow trench isolation, and the height difference is greater at the junction of the two to form a depression.