Manufacturing method of semiconductor element structure
By forming a dielectric layer, a metal layer and a barrier layer on the P-type and N-type layers of the semiconductor element, and performing oxidation and reduction reactions in the electrolyte, the complex problem of the existing semiconductor structure production process is solved, and the problem of achieving the Process integration and production process simplification.
Patent Information
- Application Number
- CN202310862444.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-03
- Filing Date
- 2023-07-14
- Publication Date
- 2025-01-03
AI Technical Summary
The existing semiconductor structure manufacturing process is complex and time-consuming, making it difficult to integrate different processes.
By forming a dielectric layer, a metal layer and a barrier layer on the P-type and N-type layers of the semiconductor element, and performing oxidation and reduction reactions in the electrolyte, partial metal layer is removed and the thickness of the metal layer is increased, thereby forming a The void and conductive layer enables component integration and process simplification.
The integration of semiconductor component production processes and other processes has been achieved, process capabilities and flexibility have been improved, and production processes have been simplified.
Smart Images
Figure CN119252823A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor structure, and in particular to a method for manufacturing a semiconductor element structure that can be integrated with other manufacturing processes. Background Art
[0002] In the current semiconductor structure manufacturing process, different semiconductor elements and / or semiconductor components often need to be manufactured using different manufacturing processes. However, in this case, the required manufacturing process time is longer and the manufacturing process complexity is higher. Therefore, how to integrate different manufacturing processes has become a goal of continuous efforts. Summary of the invention
[0003] The invention provides a semiconductor element structure, which can integrate the manufacturing process of the semiconductor element with other manufacturing processes.
[0004] The present invention provides a method for manufacturing a semiconductor device structure, comprising the following steps. A first dielectric layer is formed on a substrate. A P-type semiconductor layer and an N-type semiconductor layer connected to each other are formed on the first dielectric layer. A second dielectric layer is formed on the P-type semiconductor layer and the N-type semiconductor layer. A first opening and a second opening are formed in the second dielectric layer. The first opening exposes the P-type semiconductor layer. The second opening exposes the N-type semiconductor layer. A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening. The first metal layer is electrically connected to the P-type semiconductor layer. The second metal layer is electrically connected to the N-type semiconductor layer. The substrate is placed in an electrolyte, wherein the electrolyte covers the second dielectric layer, the first metal layer, and the second metal layer. The P-type semiconductor layer and the N-type semiconductor layer are subjected to light treatment to perform an oxidation reaction and a reduction reaction in the electrolyte, wherein a portion of the first metal layer in the first opening is removed by the oxidation reaction to form a void, and the amount of the second metal layer is increased by the reduction reaction. The substrate is removed from the electrolyte. A first barrier layer and a conductive layer are formed in the void. The first barrier layer is located between the conductive layer and the first metal layer.
[0005] According to an embodiment of the present invention, in the method for manufacturing the semiconductor device structure, the P-type semiconductor layer and the N-type semiconductor layer can be integrally formed.
[0006] According to an embodiment of the present invention, the method for manufacturing the semiconductor device structure may further include the following steps: forming a second barrier layer between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and forming a third barrier layer between the second metal layer and the second dielectric layer and between the second metal layer and the N-type semiconductor layer.
[0007] According to an embodiment of the present invention, in the manufacturing method of the semiconductor device structure, the following steps may be further included. Before forming the first barrier layer and the conductive layer, the second metal layer located outside the second opening is removed. A third dielectric layer is formed on the second metal layer, the conductive layer and the first barrier layer. A first interconnect structure and a second interconnect structure are formed in the third dielectric layer. The first interconnect structure is electrically connected to the conductive layer, and the second interconnect structure is electrically connected to the second metal layer.
[0008] The present invention provides another method for manufacturing a semiconductor device structure, comprising the following steps. A first dielectric layer is formed on a substrate. A P-type semiconductor layer and an N-type semiconductor layer connected to each other are formed on the first dielectric layer. A second dielectric layer is formed on the P-type semiconductor layer and the N-type semiconductor layer. A first opening and a second opening are formed in the second dielectric layer. The first opening exposes the P-type semiconductor layer. The second opening exposes the N-type semiconductor layer. A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening. The first metal layer is electrically connected to the P-type semiconductor layer. The second metal layer is electrically connected to the N-type semiconductor layer. The substrate is placed in an electrolyte, wherein the electrolyte covers the second dielectric layer, the first metal layer, and the second metal layer. The P-type semiconductor layer and the N-type semiconductor layer are subjected to light treatment to perform an oxidation reaction and a reduction reaction in the electrolyte, wherein at least a portion of the first metal layer in the first opening is removed by the oxidation reaction to form a gap, and the amount of the second metal layer is increased by the reduction reaction. The substrate is removed from the electrolyte. A capacitor is formed in the gap.
[0009] According to another embodiment of the present invention, in the method for manufacturing the semiconductor device structure, the P-type semiconductor layer and the N-type semiconductor layer can be integrally formed.
[0010] According to another embodiment of the present invention, the method for manufacturing the semiconductor device structure may further include the following steps: forming a first barrier layer between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and forming a second barrier layer between the second metal layer and the second dielectric layer and between the second metal layer and the N-type semiconductor layer.
[0011] According to another embodiment of the present invention, in the method for manufacturing the semiconductor device structure, the oxidation reaction can completely remove the first metal layer.
[0012] According to another embodiment of the present invention, in the method for manufacturing the semiconductor device structure, the capacitor may include a first electrode layer, a second electrode layer and a third dielectric layer. The first electrode layer may be electrically connected to the P-type semiconductor layer. The second electrode layer is located on the first electrode layer. The third dielectric layer is located between the first electrode layer and the second electrode layer.
[0013] According to another embodiment of the present invention, in the manufacturing method of the semiconductor device structure, the following steps may also be included. Before forming the capacitor, the second metal layer located outside the second opening is removed. A fourth dielectric layer is formed on the capacitor and the second metal layer. A first interconnect structure and a second interconnect structure are formed in the fourth dielectric layer. The first interconnect structure is electrically connected to the second electrode layer, and the second interconnect structure is electrically connected to the second metal layer.
[0014] Based on the above, in the manufacturing method of the semiconductor element structure proposed by the present invention, a first metal layer is formed in the first opening, and a second metal layer is formed in the second opening, the first metal layer is electrically connected to the P-type semiconductor layer, and the second metal layer is electrically connected to the N-type semiconductor layer. Then, the substrate is placed in an electrolyte, wherein the electrolyte covers the first metal layer and the second metal layer. Then, the P-type semiconductor layer and the N-type semiconductor layer are subjected to light treatment to perform oxidation reaction and reduction reaction in the electrolyte. At least part of the first metal layer in the first opening is removed by oxidation reaction to form a gap, and the amount of the second metal layer is increased by reduction reaction. Then, a semiconductor element (such as a capacitor or a fuse element) can be formed in the gap. Thus, the manufacturing process of the above-mentioned semiconductor element can be integrated with other manufacturing processes (such as an internal connection manufacturing process). In addition, since at least part of the first metal layer in the first opening is removed by oxidation reaction, the manufacturing process capability and manufacturing process flexibility can be increased.
[0015] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figures 1A to 1L A cross-sectional view of the manufacturing process of a semiconductor device structure according to some embodiments of the present invention;
[0017] FIG. 2A to FIG. 2D The following are cross-sectional views of the manufacturing process of semiconductor device structures according to some other embodiments of the present invention.
[0018] Explanation of symbols
[0019] 10,20:Semiconductor device structure
[0020] 100: Base
[0021] 102,112,124,146,148: Dielectric layer
[0022] 104: N-type semiconductor material layer
[0023] 106: N-type semiconductor layer
[0024] 108: Patterned photoresist layer
[0025] 110: P-type semiconductor layer
[0026] 114,118: Barrier material layer
[0027] 114a,114b,118a,132,138,156,160: Barrier layer
[0028] 116: Metal material layer
[0029] 116a, 116b: metal layer
[0030] 120: conductive material layer
[0031] 120a, 130, 136, 154, 158: conductive layer
[0032] 122,134: Fuse element
[0033] 126,128,150,152: Internal connection structure
[0034] 140:Capacitor
[0035] 142,144: Electrode layer
[0036] 200:Electrolyte
[0037] IP1: Ion implantation process
[0038] LT1,LT2: Light treatment
[0039] OP1,OP2: Open
[0040] V1, V2: gap DETAILED DESCRIPTION
[0041] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.
[0042] Figures 1A to 1L 4 is a cross-sectional view of a manufacturing process of a semiconductor device structure according to some embodiments of the present invention.
[0043] Please refer to Figure 1A, a dielectric layer 102 is formed on the substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the material of the dielectric layer 102 is, for example, silicon oxide. In some embodiments, the dielectric layer 102 may be a shallow trench isolation structure formed by a shallow trench isolation (STI) manufacturing process or a dielectric layer formed by a thermal oxidation method, but the present invention is not limited thereto. As long as the dielectric layer 102 has an insulating function, it falls within the scope of the present invention.
[0044] Next, an N-type semiconductor material layer 104 may be formed on the dielectric layer 102. In some embodiments, the material of the N-type semiconductor material layer 104 is, for example, N-type doped polysilicon. In some embodiments, the method of forming the N-type semiconductor material layer 104 is, for example, chemical vapor deposition with in-situ doping. In other embodiments, a semiconductor material layer may be first formed by chemical vapor deposition, and then the semiconductor material layer may be doped with N-type dopants by ion implantation to form the N-type semiconductor material layer 104.
[0045] Please refer to Figure 1B , the N-type semiconductor material layer 104 may be patterned to form the N-type semiconductor layer 106. In some embodiments, the N-type semiconductor material layer 104 may be patterned by a photolithography process and an etching process.
[0046] Please refer to Figure 1C , a patterned photoresist layer 108 may be formed on the dielectric layer 102 and the N-type semiconductor layer 106. The patterned photoresist layer 108 may expose a portion of the N-type semiconductor layer 106. In some embodiments, the patterned photoresist layer 108 may be formed by a photolithography process.
[0047] Next, the patterned photoresist layer 108 can be used as a mask to perform an ion implantation process IP1 on the N-type semiconductor layer 106 to form a P-type semiconductor layer 110. Thus, a P-type semiconductor layer 110 and an N-type semiconductor layer 106 that are connected to each other can be formed on the dielectric layer 102. In some embodiments, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 can be integrally formed. In this embodiment, the N-type semiconductor layer 106 is first formed, and then the N-type semiconductor layer 106 is subjected to an ion implantation process to form the P-type semiconductor layer 110, but the present invention is not limited thereto. In other embodiments, the P-type semiconductor layer 110 can be first formed, and then the P-type semiconductor layer 110 is subjected to an ion implantation process to form the N-type semiconductor layer 106.
[0048] Please refer to Figure 1D, the patterned photoresist layer 108 can be removed. In some embodiments, the patterned photoresist layer 108 can be removed by, for example, dry stripping or wet stripping.
[0049] Next, a dielectric layer 112 is formed on the P-type semiconductor layer 110 and the N-type semiconductor layer 106. In some embodiments, the material of the dielectric layer 112 is, for example, a low-k material or silicon oxide. In some embodiments, the dielectric layer 112 is formed by, for example, chemical vapor deposition.
[0050] Please refer to Figure 1E , an opening OP1 and an opening OP2 are formed in the dielectric layer 112. The opening OP1 exposes the P-type semiconductor layer 110. The opening OP2 exposes the N-type semiconductor layer 106. In some embodiments, a portion of the dielectric layer 112 may be removed by a patterning process to form the opening OP1 and the opening OP2. In this embodiment, the opening OP1 and the opening OP2 are dual damascene openings, but the present invention is not limited thereto. In other embodiments, the opening OP1 and the opening OP2 may be single damascene openings.
[0051] Please refer to Figure 1F , a barrier material layer 114 may be conformally formed on the dielectric layer 112 and in the openings OP1 and OP2. In some embodiments, the barrier material layer 114 may be made of, for example, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the barrier material layer 114 may be formed by, for example, physical vapor deposition or chemical vapor deposition.
[0052] Next, a metal material layer 116 may be formed on the barrier material layer 114. In some embodiments, the material of the metal material layer 116 is, for example, copper. In some embodiments, the metal material layer 116 may be formed by, for example, physical vapor deposition, electrochemical plating (ECP), or a combination thereof.
[0053] Please refer to Figure 1G, the metal material layer 116 and the barrier material layer 114 located outside the opening OP1 and outside the opening OP2 may be removed to form a metal layer 116a, a metal layer 116b, a barrier layer 114a, and a barrier layer 114b. Thus, the metal layer 116a may be formed in the opening OP1, the metal layer 116b may be formed in the opening OP2, the barrier layer 114a may be formed between the metal layer 116a and the dielectric layer 112 and between the metal layer 116a and the P-type semiconductor layer 110, and the barrier layer 114b may be formed between the metal layer 116b and the dielectric layer 112 and between the metal layer 116b and the N-type semiconductor layer 106. The metal layer 116a is electrically connected to the P-type semiconductor layer 110. In some embodiments, the metal layer 116a may be electrically connected to the P-type semiconductor layer 110 via the barrier layer 114a. The metal layer 116b is electrically connected to the N-type semiconductor layer 106. In some embodiments, the metal layer 116b may be electrically connected to the N-type semiconductor layer 106 via the barrier layer 114b. In some embodiments, the metal material layer 116 and the barrier material layer 114 outside the opening OP1 and the opening OP2 may be removed by chemical mechanical polishing, for example.
[0054] Please refer to Figure 1H , the substrate 100 is placed in an electrolyte 200, wherein the electrolyte 200 covers the dielectric layer 112, the metal layer 116a, and the metal layer 116b. In some embodiments, the electrolyte 200 may also cover the barrier layer 114a and the barrier layer 114b. In some embodiments, when the material of the metal layer 116a and the metal layer 116b is copper, the electrolyte 200 may be a copper sulfate solution or a copper nitrate solution.
[0055] Please refer to Fig. 1I, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to light irradiation treatment LT1 to perform oxidation reaction and reduction reaction in the electrolyte 200, wherein a portion of the metal layer 116a in the opening OP1 is removed by oxidation reaction to form a gap V1, and the amount of the metal layer 116b is increased by reduction reaction. Since the P-type semiconductor layer 110 and the N-type semiconductor layer 106 have a PN junction, and the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to light irradiation treatment LT1, electron-hole pairs are generated and separated by the interface electric field. The holes flow to the P-type semiconductor layer 110, and the metal layer 116a undergoes an oxidation reaction, and the holes absorb the released electrons, and the metal layer 116a gradually disappears. The electrons flow to the N-type semiconductor layer 106, and the metal layer 116b undergoes a reduction reaction, and the metal is deposited on the metal layer 116b, thereby increasing the amount of the metal layer 116b. In this embodiment, the top-view area of the metal layer 116a is similar to the top-view area of the metal layer 116b, but the present invention is not limited thereto. In other embodiments, the top-view area of the metal layer 116b may be larger than the top-view area of the metal layer 116a, thereby preventing the height of the metal layer 116b located outside the opening OP2 from being too high, so as to facilitate subsequent manufacturing processes. In addition, the amount of metal layer 116a removed and the amount of metal layer 116b added can be controlled by controlling the time of the light treatment LT1.
[0056] Please refer to Figure 1J , the substrate 100 is taken out of the electrolyte 200. Then, the metal layer 116b located outside the opening OP2 may be removed. In some embodiments, the metal layer 116b located outside the opening OP2 may be removed by, for example, chemical mechanical polishing.
[0057] Then, a barrier material layer 118 and a conductive material layer 120 may be sequentially formed on the metal layer 116a, the barrier layer 114a, the metal layer 116b, the barrier layer 114b, and the dielectric layer 112. In some embodiments, the material of the barrier material layer 118 is, for example, titanium, titanium nitride, or a combination thereof. In some embodiments, the barrier material layer 118 is formed by, for example, physical vapor deposition or chemical vapor deposition. In some embodiments, the material of the conductive material layer 120 is, for example, tungsten. In some embodiments, the conductive material layer 120 is formed by, for example, chemical vapor deposition or physical vapor deposition.
[0058] Please refer to Figure 1K, the conductive material layer 120 and the barrier material layer 118 located outside the void V1 can be removed, and a barrier layer 118a and a conductive layer 120a are formed in the void V1. The barrier layer 118a is located between the conductive layer 120a and the metal layer 116a. Thus, a fuse element 122 can be formed. The fuse element 122 may include the metal layer 116a, the barrier layer 118a and the conductive layer 120a. Since the resistance value of the conductive layer 120a may be higher than the resistance value of the metal layer 116a, when the current is too high, the barrier layer 118a will melt, achieving the effect of a fuse. In some embodiments, the barrier layer 118a may also be located between the conductive layer 120a and the barrier layer 114a. In some embodiments, the method for removing the conductive material layer 120 and the barrier material layer 118 located outside the void V1 is, for example, a chemical mechanical polishing method.
[0059] Please refer to Figure 1L , a dielectric layer 124 may be formed on the metal layer 116b, the barrier layer 114b, the conductive layer 120a, the barrier layer 118a, the barrier layer 114a and the dielectric layer 112. In some embodiments, the material of the dielectric layer 124 is, for example, a low dielectric constant material or silicon oxide. In some embodiments, the dielectric layer 124 is formed by, for example, chemical vapor deposition.
[0060] Next, an interconnect structure 126 and an interconnect structure 128 may be formed in the dielectric layer 124. The interconnect structure 126 is electrically connected to the conductive layer 120a, and the interconnect structure 128 is electrically connected to the metal layer 116b. In some embodiments, the interconnect structure 126 and the interconnect structure 128 may be formed by an interconnect fabrication process.
[0061] In some embodiments, the interconnect structure 126 may include a conductive layer 130 and a barrier layer 132. The barrier layer 132 is located between the conductive layer 130 and the dielectric layer 124 and between the conductive layer 130 and the conductive layer 120a. Thus, a fuse element 134 may be formed. The fuse element 134 may include the conductive layer 120a, the barrier layer 132, and the conductive layer 130. Since the resistance value of the conductive layer 120a may be higher than the resistance value of the conductive layer 130, when the current is too high, the barrier layer 132 will melt, achieving the effect of a fuse. In some embodiments, the material of the conductive layer 130 is, for example, copper. In some embodiments, the material of the barrier layer 132 is, for example, tantalum, tantalum nitride, or a combination thereof.
[0062] In some embodiments, the interconnect structure 128 may include a conductive layer 136 and a barrier layer 138. The barrier layer 138 is located between the conductive layer 136 and the dielectric layer 124 and between the conductive layer 136 and the metal layer 116b. In some embodiments, the material of the conductive layer 136 is, for example, copper. In some embodiments, the material of the barrier layer 138 is, for example, tantalum, tantalum nitride, or a combination thereof.
[0063] Based on the above embodiments, it can be known that in the manufacturing method of the semiconductor device structure 10, a metal layer 116a is formed in the opening OP1, and a metal layer 116b is formed in the opening OP2, wherein the metal layer 116a is electrically connected to the P-type semiconductor layer 110, and the metal layer 116b is electrically connected to the N-type semiconductor layer 106. Next, the substrate 100 is placed in an electrolyte 200, wherein the electrolyte 200 covers the metal layer 116a and the metal layer 116b. Then, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to a light treatment LT1 to perform an oxidation reaction and a reduction reaction in the electrolyte 200. A portion of the metal layer 116a in the opening OP1 is removed by an oxidation reaction to form a void V1, and the amount of the metal layer 116b is increased by a reduction reaction. Next, a fuse element 122 can be formed in the void V1. Thus, the manufacturing process of the fuse element 122 can be integrated with other manufacturing processes (e.g., an internal connection manufacturing process). In addition, since a portion of the metal layer 116 a in the opening OP1 is removed through an oxidation reaction, the manufacturing process capability and the manufacturing process flexibility can be increased.
[0064] FIG. 2A to FIG. 2D 2 is a cross-sectional view of the manufacturing process of a semiconductor device structure according to some other embodiments of the present invention.
[0065] Please refer to Figure 2A , can provide Figure 1H In addition, Figure 1H For details of the structure, please refer to Figures 1A to 1H The description will not be repeated here.
[0066] Please refer to Figure 2B , the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to light treatment LT2 to perform oxidation reaction and reduction reaction in the electrolyte 200, wherein at least a portion of the metal layer 116a in the opening OP1 is removed by oxidation reaction to form a gap V2, and the amount of the metal layer 116b is increased by reduction reaction. In this embodiment, the oxidation reaction can completely remove the metal layer 116a, but the present invention is not limited thereto. In this embodiment, Figure 2B The time of the light treatment LT2 can be greater than Fig. 1I In some other embodiments, the oxidation reaction may only remove a portion of the metal layer 116a. Figure 2B The rest of the steps can be found in Fig. 1I The description will not be repeated here.
[0067] Please refer to Figure 2C, the substrate 100 is taken out of the electrolyte 200. Then, the metal layer 116b located outside the opening OP2 may be removed. In some embodiments, the metal layer 116b located outside the opening OP2 may be removed by, for example, chemical mechanical polishing.
[0068] Then, a capacitor 140 is formed in the gap V2. In some embodiments, the capacitor 140 may include an electrode layer 142, an electrode layer 144, and a dielectric layer 146. The electrode layer 142 may be electrically connected to the P-type semiconductor layer 110. In some embodiments, the electrode layer 142 may be electrically connected to the P-type semiconductor layer 110 via the barrier layer 114a. In some embodiments, the material of the electrode layer 142 is, for example, titanium nitride. The electrode layer 144 is located on the electrode layer 142. In some embodiments, the material of the electrode layer 142 is, for example, tungsten. The dielectric layer 146 is located between the electrode layer 142 and the electrode layer 144. In some embodiments, the material of the dielectric layer 146 is, for example, hafnium dioxide (HfO 2 )、ZrO 2 ) or titanium dioxide (TiO 2 ). In addition, the capacitor 140 can be manufactured by conventional methods, which will not be described here.
[0069] Please refer to Figure 2D , a dielectric layer 148 may be formed on the capacitor 140, the barrier layer 114a, the barrier layer 114b, the metal layer 116b, and the dielectric layer 112. In some embodiments, the material of the dielectric layer 148 is, for example, a low dielectric constant material or silicon oxide. In some embodiments, the dielectric layer 148 is formed by, for example, chemical vapor deposition.
[0070] Next, an interconnect structure 150 and an interconnect structure 152 may be formed in the dielectric layer 148. The interconnect structure 150 is electrically connected to the electrode layer 144, and the interconnect structure 152 is electrically connected to the metal layer 116b. In some embodiments, the interconnect structure 150 and the interconnect structure 152 may be formed by an interconnect fabrication process.
[0071] In some embodiments, the interconnect structure 150 may include a conductive layer 154 and a barrier layer 156. The barrier layer 156 is located between the conductive layer 154 and the dielectric layer 148 and between the conductive layer 154 and the electrode layer 144. In some embodiments, the material of the conductive layer 154 is, for example, tungsten or copper. In some embodiments, the material of the barrier layer 132 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.
[0072] In some embodiments, the interconnect structure 152 may include a conductive layer 158 and a barrier layer 160. The barrier layer 160 is located between the conductive layer 158 and the dielectric layer 148 and between the conductive layer 158 and the metal layer 116b. In some embodiments, the material of the conductive layer 158 is, for example, tungsten or copper. In some embodiments, the material of the barrier layer 160 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.
[0073] Based on the above embodiments, it can be known that in the manufacturing method of the semiconductor device structure 20, a metal layer 116a is formed in the opening OP1, and a metal layer 116b is formed in the opening OP2, the metal layer 116a is electrically connected to the P-type semiconductor layer 110, and the metal layer 116b is electrically connected to the N-type semiconductor layer 106. Then, the substrate 100 is placed in the electrolyte 200, wherein the electrolyte 200 covers the metal layer 116a and the metal layer 116b. Then, the P-type semiconductor layer 110 and the N-type semiconductor layer 106 are subjected to light treatment LT2 to perform oxidation reaction and reduction reaction in the electrolyte 200. At least part of the metal layer 116a in the opening OP1 is removed by oxidation reaction to form a gap V2, and the amount of the metal layer 116b is increased by reduction reaction. Then, a capacitor 140 can be formed in the gap V2. Thus, the manufacturing process of the capacitor 140 can be integrated with other manufacturing processes (such as the interconnect manufacturing process), and the capacitor 140 can have a larger capacitance value. In addition, since at least a portion of the metal layer 116a in the opening OP1 is removed by oxidation reaction, the manufacturing process capability and manufacturing process flexibility can be increased.
[0074] In summary, in the manufacturing method of the semiconductor device structure of the above embodiment, the manufacturing process of the semiconductor device (such as a capacitor or a fuse element) can be integrated with other manufacturing processes (such as an interconnect manufacturing process). In addition, in the manufacturing method of the semiconductor device structure of the above embodiment, at least a portion of the metal layer can be removed by oxidation reaction, thereby increasing the manufacturing process capability and manufacturing process flexibility.
[0075] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any ordinary technician in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.
Claims
1. A method for manufacturing a semiconductor device structure, comprising: forming a first dielectric layer on a substrate; forming a P-type semiconductor layer and an N-type semiconductor layer connected to each other on the first dielectric layer; forming a second dielectric layer on the P-type semiconductor layer and the N-type semiconductor layer; forming a first opening and a second opening in the second dielectric layer, wherein the first opening exposes the P-type semiconductor layer, and the second opening exposes the N-type semiconductor layer; forming a first metal layer in the first opening and forming a second metal layer in the second opening, wherein the first metal layer is electrically connected to the P-type semiconductor layer, and the second metal layer is electrically connected to the N-type semiconductor layer; placing the substrate in an electrolyte, wherein the electrolyte covers the second dielectric layer, the first metal layer, and the second metal layer; Performing light treatment on the P-type semiconductor layer and the N-type semiconductor layer to perform oxidation reaction and reduction reaction in the electrolyte, wherein the oxidation reaction removes a portion of the first metal layer in the first opening to form a gap, and the reduction reaction increases the amount of the second metal layer; removing the substrate from the electrolyte; as well as A first barrier layer and a conductive layer are formed in the gap, wherein the first barrier layer is located between the conductive layer and the first metal layer. 2 . The method for manufacturing a semiconductor device structure as claimed in claim 1 , wherein the P-type semiconductor layer and the N-type semiconductor layer are integrally formed.
3. The method for manufacturing a semiconductor device structure according to claim 1, further comprising: A second barrier layer is formed between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and a third barrier layer is formed between the second metal layer and the second dielectric layer and between the second metal layer and the N-type semiconductor layer.
4. The method for manufacturing a semiconductor device structure according to claim 1, further comprising: Before forming the first barrier layer and the conductive layer, removing the second metal layer located outside the second opening; forming a third dielectric layer on the second metal layer, the conductive layer and the first barrier layer; as well as A first interconnect structure and a second interconnect structure are formed in the third dielectric layer, wherein the first interconnect structure is electrically connected to the conductive layer, and the second interconnect structure is electrically connected to the second metal layer.
5. A method for manufacturing a semiconductor device structure, comprising: forming a first dielectric layer on a substrate; forming a P-type semiconductor layer and an N-type semiconductor layer connected to each other on the first dielectric layer; forming a second dielectric layer on the P-type semiconductor layer and the N-type semiconductor layer; forming a first opening and a second opening in the second dielectric layer, wherein the first opening exposes the P-type semiconductor layer, and the second opening exposes the N-type semiconductor layer; forming a first metal layer in the first opening and forming a second metal layer in the second opening, wherein the first metal layer is electrically connected to the P-type semiconductor layer, and the second metal layer is electrically connected to the N-type semiconductor layer; placing the substrate in an electrolyte, wherein the electrolyte covers the second dielectric layer, the first metal layer, and the second metal layer; Performing light treatment on the P-type semiconductor layer and the N-type semiconductor layer to perform oxidation reaction and reduction reaction in the electrolyte, wherein at least a portion of the first metal layer in the first opening is removed by the oxidation reaction to form a gap, and the amount of the second metal layer is increased by the reduction reaction; removing the substrate from the electrolyte; as well as A capacitor is formed in the gap. 6 . The method for manufacturing a semiconductor device structure as claimed in claim 5 , wherein the P-type semiconductor layer and the N-type semiconductor layer are integrally formed.
7. The method for manufacturing a semiconductor device structure according to claim 5, further comprising: A first barrier layer is formed between the first metal layer and the second dielectric layer and between the first metal layer and the P-type semiconductor layer, and a second barrier layer is formed between the second metal layer and the second dielectric layer and between the second metal layer and the N-type semiconductor layer. 8 . The method for manufacturing a semiconductor device structure as claimed in claim 5 , wherein the oxidation reaction completely removes the first metal layer.
9. The method for manufacturing a semiconductor device structure according to claim 5, wherein the capacitor comprises: A first electrode layer, wherein the first electrode layer is electrically connected to the P-type semiconductor layer; a second electrode layer, located on the first electrode layer; as well as The third dielectric layer is located between the first electrode layer and the second electrode layer.
10. The method for manufacturing a semiconductor device structure according to claim 9, further comprising: Before forming the capacitor, removing the second metal layer located outside the second opening; forming a fourth dielectric layer on the capacitor and the second metal layer; as well as A first interconnect structure and a second interconnect structure are formed in the fourth dielectric layer, wherein the first interconnect structure is electrically connected to the second electrode layer, and the second interconnect structure is electrically connected to the second metal layer.