Three-level inverter circuit and control method thereof

Abstract

The invention relates to the technical field of three-level inverters, and provides a three-level inverter circuit and a control method thereof. The circuit comprises a first half-bridge circuit, a second half-bridge circuit, a first capacitor, a second capacitor, a three-phase inverter circuit and a controller, the controller is used for obtaining at least one first vector, at least one second vector, a first zero vector and a second zero vector which form a reference voltage vector, inserting the first zero vector and the second zero vector between the adjacent first vector and second vector to form a vector sequence which is switched between the first vector and the second vector through the zero vectors, and according to the vector sequence, on-off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit is controlled. According to the three-level inverter circuit provided by the embodiment of the invention, the loss of the switching device can be reduced while the neutral-point voltage balance is maintained.

Description

Technical Field

[0001] The present application relates to the technical field of three-level inverters, and in particular to a three-level inverter circuit and a control method thereof. Background Art

[0002] With the increase of DC voltage level and power level, and the increase of frequency requirements of high-speed drives, three-level inverters are currently generally used to meet the application of high voltage and high power. When a three-level inverter is used to meet the application of high voltage and high power, in the related technology, SVPWM vector modulation is used to determine the synthetic voltage vector and the corresponding conductive switching device used by the three-level inverter, so as to obtain the vector constituting the reference voltage vector from each synthetic voltage vector to form a switching sequence to control the switching of the three-level inverter. However, the switching sequence formed in the prior art has a large loss on the switching device of the three-level inverter, so how to reduce the loss on the switching device to improve the working efficiency of the entire three-level inverter circuit is a problem that needs to be solved urgently. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the related art. To this end, the present application proposes a control method for a three-level inverter circuit, which can reduce the loss of switching devices and maintain the balance of the midpoint voltage.

[0004] The present application also proposes a three-level inverter circuit, which can reduce the cost of existing solutions. When the control method proposed in the present application is used, dead time is not required, which further improves efficiency.

[0005] The present application also provides a control device for a three-level inverter circuit.

[0006] The application also provides an electronic device.

[0007] According to the three-level inverter circuit of the first embodiment of the present application, the three-level inverter circuit includes a first half-bridge circuit, a second half-bridge circuit, a first capacitor, a second capacitor, a three-phase inverter circuit and a controller;

[0008] One end of the first half-bridge circuit is connected to one end of the second half-bridge circuit, the other end of the first half-bridge circuit is connected to one end of the first capacitor, the other end of the second half-bridge circuit is connected to one end of the second capacitor, the first capacitor and the second capacitor are connected in series, and one end of the first half-bridge circuit is connected to a midpoint between the first capacitor and the second capacitor;

[0009] The three-phase inverter circuit comprises a first half bridge, a second half bridge and a third half bridge, wherein the first half bridge, the second half bridge and the third half bridge are connected in parallel, one end of the first half bridge is connected to the midpoint of the first half bridge circuit, and the other end of the first half bridge is connected to the midpoint of the second half bridge circuit;

[0010] The controller is used to obtain at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector, insert the first zero vector and the second zero vector between adjacent first vectors and second vectors, and form a vector sequence between the first vector and the second vector that is switched by the zero vector, so as to control the first half-bridge circuit, the second half-bridge circuit and the on and off of each device in the three-phase inverter circuit according to the vector sequence;

[0011] The first vector and the second vector are vectors causing a change in the midpoint current between the first capacitor and the second capacitor;

[0012] The zero vector includes a first zero vector or a second zero vector, the first zero vector and the second zero vector correspond to different control strategies of the three-phase inverter circuit, the first vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit, and the second vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit.

[0013] According to one embodiment of the present application, the controller is specifically used for:

[0014] Sorting the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors, inserting the first zero vector and the second zero vector in sequence between the first vector and the second vector, and inserting the second zero vector and the first zero vector in sequence between the second vector and the first vector, to obtain the vector sequence; or,

[0015] Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is between the two second vectors;

[0016] The second zero vector and the first zero vector are sequentially inserted between the second vector and the first vector, and the first zero vector and the second zero vector are sequentially inserted between the first vector and the second vector, so as to obtain the vector sequence.

[0017] According to an embodiment of the present application, the control strategy corresponding to the first vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on;

[0018] The control strategy corresponding to the second vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0019] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0020] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0021] According to an embodiment of the present application, the control strategy corresponding to the first vector includes the lower bridge arm of the first half-bridge circuit being turned on, the lower bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on;

[0022] The control strategy corresponding to the second vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0023] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0024] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0025] According to an embodiment of the present application, the control strategy corresponding to the first vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on;

[0026] The control strategy corresponding to the second vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0027] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0028] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0029] According to an embodiment of the present application, the control strategy corresponding to the first vector includes the lower bridge arm of the first half-bridge circuit being turned on, the lower bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on;

[0030] The control strategy corresponding to the second vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0031] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0032] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0033] According to one embodiment of the present application, the first half-bridge circuit includes a first switching device and a second switching device, and the second half-bridge circuit includes a third switching device and a fourth switching device;

[0034] The first switch device, the second switch device, the third switch device and the fourth switch device are connected in series, and one end of the second switch device connected to the third switch device is connected to the midpoint between the first capacitor and the second capacitor;

[0035] The second switching device and the third switching device are passive power devices.

[0036] A control method for a three-level inverter circuit according to an embodiment of the second aspect of the present application is applied to the three-level inverter circuit as described in any of the above embodiments, including:

[0037] Acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector forming a reference voltage vector;

[0038] A first zero vector and a second zero vector are inserted between adjacent first vectors and second vectors to form a vector sequence between the first vector and the second vector, which is switched by zero vectors, so as to control the on and off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0039] A control device for a three-level inverter circuit according to an embodiment of the third aspect of the present application is applied to the three-level inverter circuit as described in any of the above embodiments, including:

[0040] A vector acquisition module, used to acquire at least one first vector, at least one second vector, a first zero vector and a second zero vector forming a reference voltage vector;

[0041] The on-off control module is used to insert a first zero vector and a second zero vector between adjacent first vectors and second vectors to form a vector sequence between the first vector and the second vector, which is switched by the zero vector, so as to control the on-off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0042] An electronic device according to an embodiment of the fourth aspect of the present application includes a processor and a memory storing a computer program, and when the processor executes the computer program, the control method of the three-level inverter circuit described in any of the above embodiments is implemented.

[0043] According to the computer-readable storage medium of the fifth aspect of the present application, a computer program is stored thereon, and when the computer program is executed by a processor, the control method of the three-level inverter circuit described in any of the above embodiments is implemented.

[0044] The vehicle according to the fifth aspect of the present application includes the three-level inverter circuit as described in the first aspect, or the electronic device as described in the fourth aspect.

[0045] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0046] By acquiring at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector, and inserting the first zero vector and the second zero vector between adjacent first vectors and second vectors, a vector sequence is formed between the first vector and the second vector, and the switching is performed by the zero vector, so as to control the on and off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence. Since the switching between the first vector and the second vector is performed by the zero vector, and the voltage is zero when the zero vector is used, there is no switching loss in the process of controlling the on and off of each device at this time, so that the loss of the switching device can be effectively reduced, the working efficiency of the entire three-level inverter circuit can be improved, and the balance of the midpoint voltage can be maintained at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 is a first structural schematic diagram of a three-level inverter circuit provided in an embodiment of the present application;

[0049] Figure 2 is a second structural schematic diagram of a three-level inverter circuit provided in an embodiment of the present application;

[0050] Figure 3 is a structural schematic diagram of a control method for a three-level inverter circuit provided in an embodiment of the present application;

[0051] Figure 4 is a structural schematic diagram of a control device for a three-level inverter circuit provided in an embodiment of the present application;

[0052] Figure 5 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] With the increase of DC voltage level and power level, and the increase of frequency requirements of high-speed drives, three-level inverters are currently generally used to meet the application of high voltage and high power. When a three-level inverter is used to meet the application of high voltage and high power, in the related technology, SVPWM vector modulation is used to determine the synthetic voltage vector and the corresponding switching devices used by the three-level inverter, so as to obtain the first vector, the second vector and the zero vector constituting the reference voltage vector from each synthetic voltage vector to form a switching sequence to control the switching of the three-level inverter, wherein the first vector and the second vector are vectors for changing the midpoint voltage of the three-level inverter.

[0055] However, the switching sequence formed in the prior art causes large losses to the switching devices of the three-level inverter. Therefore, how to reduce the losses to the switching devices to improve the working efficiency of the entire three-level inverter circuit is a problem that needs to be solved urgently.

[0056] In view of the above problems, the present application provides a three-level inverter circuit. Figure 1 As shown, the three-level inverter circuit includes a first half-bridge circuit 10, a second half-bridge circuit 20, a first capacitor C1, a second capacitor C2, a three-phase inverter circuit 30 and a controller;

[0057] One end of the first half-bridge circuit 10 is connected to one end of the second half-bridge circuit 20, the other end of the first half-bridge circuit 10 is connected to one end of the first capacitor C1, the other end of the second half-bridge circuit 20 is connected to one end of the second capacitor C2, the first capacitor C1 and the second capacitor C2 are connected in series, and one end of the first half-bridge circuit 10 is connected to the midpoint between the first capacitor C1 and the second capacitor C2;

[0058] The three-phase inverter circuit 30 includes a first half bridge, a second half bridge and a third half bridge, wherein the first half bridge, the second half bridge and the third half bridge are connected in parallel, one end of the first half bridge is connected to the midpoint of the first half bridge circuit 10, and the other end of the first half bridge is connected to the midpoint of the second half bridge circuit 20;

[0059] The controller is used to obtain at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector, insert the first zero vector and the second zero vector between adjacent first vectors and second vectors, and form a vector sequence between the first vector and the second vector that is switched by the zero vector, so as to control the on and off of each device in the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30 according to the vector sequence;

[0060] The first vector and the second vector are vectors causing the midpoint current between the first capacitor C1 and the second capacitor C2 to change;

[0061] The zero vector includes a first zero vector or a second zero vector, the first zero vector and the second zero vector correspond to different control strategies of the three-phase inverter circuit 30, the first vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit 30, and the second vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit 30.

[0062] In some embodiments, the first half-bridge circuit 10 includes a first switching device sp and a second switching device dp, and the second half-bridge circuit 20 includes a third switching device dn and a fourth switching device sn;

[0063] The first switch device sp, the second switch device dp, the third switch device dn and the fourth switch device sn are connected in series, one end of the first switch device sp is connected to one end of the first capacitor C1, one end of the fourth switch device sn is connected to one end of the second capacitor C2, and one end of the third switch device dn connected to the fourth switch device sn is connected to the midpoint between the first capacitor C1 and the second capacitor C2. The first switch device sp, the second switch device dp, the third switch device dn and the fourth switch device sn can all be active switch devices, such as IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) modules.

[0064] One end of the first capacitor C1 can be connected to the positive electrode of the power supply, and one end of the second capacitor C2 can be connected to the negative electrode of the power supply. The first capacitor C1 and the second capacitor C2 can be the same capacitor.

[0065] The three-phase inverter circuit 30 includes a first half bridge, a second half bridge and a third half bridge, the upper bridge arm of the first half bridge includes a first switch sa1, and the lower bridge arm of the first half bridge includes a second switch sa2; the upper bridge arm of the second half bridge includes a third switch sb1, and the lower bridge arm of the second half bridge includes a fourth switch sb2; the upper bridge arm of the third half bridge includes a fifth switch sc1, and the lower bridge arm of the third half bridge includes a sixth switch sc2. The first switch sa1, the second switch sa2, the third switch sb1, the fourth switch sb2, the fifth switch sc1, and the sixth switch sc2 can all be active switch devices, such as IGBT modules. The first switch sa1 and the second switch sa2 are interlocked, the third switch sb1 and the fourth switch sb2 are interlocked, and the fifth switch sc1 and the sixth switch sc2 are interlocked. The three-phase inverter circuit 30 can be connected to a three-phase circuit. For example, the three-phase inverter circuit 30 can be connected to a three-phase motor, such as the first half bridge, the second half bridge and the third half bridge are respectively connected to the A phase, the B phase and the C phase of the three-phase motor.

[0066] According to the SVPWM modulation theory, each phase of the three-level inverter circuit can have three states, so the three-level inverter circuit has a total of 27 switching states, corresponding to 27 synthetic voltage vectors. The 27 synthetic voltage vectors include a large vector lv, a small vector sv and a zero vector zv, wherein the large vector lv and the zero vector zv have no effect on the midpoint voltage between the first capacitor C1 and the second capacitor C2, while the polarity of the small vector sv will affect the midpoint voltage. The synthetic voltage vector can form a reference voltage vector, which can refer to a voltage vector used to synthesize a desired output voltage in the three-level SVPWM modulation, that is, a voltage vector of the desired output voltage obtained by the three-level inverter circuit through SVPWM modulation. Therefore, the corresponding synthetic voltage vector can be formed by controlling the switching devices of the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30 to output a reference voltage vector.

[0067] Since the large vector lv has no effect on the midpoint voltage, the reference voltage vector can be composed of multiple small vectors sv and a zero vector zv. For example, the reference voltage vector can be composed of a small vector and a zero vector. The controller can store the small vectors sv and the zero vectors zv that constitute a certain reference voltage vector, as well as the control strategy of the three-phase inverter circuit 30 corresponding to any small vector sv, and the control strategy of the three-phase inverter circuit 30 corresponding to any zero vector zv.

[0068] Exemplarily, a vector set forming a reference voltage vector may include two identical small vectors, another small vector, a zero vector identical to the switch device turned on by the two identical small vectors in the three-phase inverter circuit 30, and a zero vector identical to the switch device turned on by the other small vector in the three-phase inverter circuit 30. After determining the reference voltage vector, the controller may determine the sector in which the reference voltage vector is located according to the phase angle and modulation ratio of the reference voltage vector, and determine the vector set constituting the reference voltage vector according to the sector, so as to determine the two identical small vectors in the vector set as the first vector and the other small vector as the second vector, or determine the two identical small vectors as the second vector and the other small vector as the first vector. At the same time, the zero vector identical to the switch device turned on by the first vector in the three-phase inverter circuit 30 is determined as the first zero vector, and the zero vector identical to the switch device turned on by the second vector in the three-phase inverter circuit 30 is determined as the second zero vector.

[0069] After obtaining at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector, the first vectors and the second vectors can be alternately sorted first, and then the first zero vector and the second zero vector are inserted between adjacent first vectors and second vectors to form a vector sequence, so that the first vector and the second vector are switched through the zero vector.

[0070] After the vector sequence is obtained, the first half-bridge circuit 10, the second half-bridge circuit 20 and each device in the three-phase inverter circuit 30 can be controlled according to the vector sequence. If the vector sequence is the first vector-the first zero vector-the second zero vector-the second vector-the second zero vector-the first zero vector-the first vector, then the first half-bridge circuit 10, the second half-bridge circuit 20 and each device in the three-phase inverter circuit 30 can be controlled according to the control strategy corresponding to the first vector, and then the first half-bridge circuit 10, the second half-bridge circuit 20 and each device in the three-phase inverter circuit 30 can be controlled according to the control strategy corresponding to the first zero vector, and so on, so as to form a reference voltage vector through the three-level inverter circuit.

[0071] By acquiring at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector, and inserting the first zero vector and the second zero vector between adjacent first vectors and second vectors, a vector sequence is formed between the first vector and the second vector, and the switching of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit is controlled according to the vector sequence. Since the switching between the first vector and the second vector is performed by the zero vector, and the voltage is zero when the zero vector is used, there is no switching loss in the process of controlling the switching of each device, so the loss of the switching device can be effectively reduced, and the working efficiency of the entire three-level inverter circuit can be improved. The midpoint current polarity of the second vector can be selected, so the balance of the midpoint voltage can be maintained at the same time.

[0072] In some embodiments, the controller is specifically configured to:

[0073] Sorting the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors, inserting the first zero vector and the second zero vector in sequence between the first vector and the second vector, and inserting the second zero vector and the first zero vector in sequence between the second vector and the first vector, to obtain the vector sequence; or,

[0074] Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is between the two second vectors;

[0075] The second zero vector and the first zero vector are sequentially inserted between the second vector and the first vector, and the first zero vector and the second zero vector are sequentially inserted between the first vector and the second vector, so as to obtain the vector sequence.

[0076] As a possible implementation, the vector set forming the reference voltage vector may include two first vectors svi, a second vector svj, a first zero vector zvi and a second zero vector zvj. The second vector svj is inserted between the two first vectors svi to obtain a first initial sequence svi–svj–svi. Then, the first vector svi and the second zero vector zvj are sequentially inserted between the first vector svi and the second vector svj, and the second zero vector zvj and the first zero vector svi are sequentially inserted between the second vector svj and the first vector svi to obtain a vector sequence of: svi-zvi–zvj–svj–zvj–zvi–svi.

[0077] As another possible implementation, the vector set forming the reference voltage vector may include a first vector svi, two second vectors svj, a first zero vector zvi and a second zero vector zvj. The first vector svi is inserted between the two second vectors svj to obtain a second initial sequence svj–svi–svj. Then, the second zero vector zvj and the first zero vector svi are inserted in sequence between the second vector svj and the first vector svi. Also, the first vector svi and the second zero vector zvj are inserted in sequence between the first vector svi and the second vector svj to obtain a vector sequence of: svj-zvj–zvi–svi–zvi–zvj–svj.

[0078] At this time, when the vector sequence is used to control the on and off of each device in the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30, there are a total of 6 switching actions. Since the voltage is zero at zero vector, there is no switching loss in the process of controlling the on and off of each device at this time. Therefore, when the vector sequence obtained in the above manner controls the on and off of each device, there are only 4 switching losses, thereby further reducing the switching loss of the three-level inverter circuit.

[0079] In some embodiments, the first vector may be recorded as sv1p, the second vector may be recorded as sv2n, the first zero vector may be recorded as zv1, and the second zero vector may be recorded as zv2. The control strategy corresponding to sv1p includes that the upper bridge arm of the first half-bridge circuit 10 is turned on, the upper bridge arm of the second half-bridge circuit 20 is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on; that is, the first switch device sp is turned on, the third switch device dn is turned on, the first switch sa1 is turned on, the fourth switch sb2 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to sv2n includes that the lower bridge arm of the first half-bridge circuit 10 is turned on, the lower bridge arm of the second half-bridge circuit 20 is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on; that is, the second switch device dp and the fourth switch device sn are turned on, the first switch sa1 is turned on, the third switch sb1 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to zv1 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the fourth switch sb2 being turned on, and the sixth switch sc2 being turned on. The control strategy corresponding to zv2 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arms of the first half-bridge and the second half-bridge being turned on, and the lower bridge arm of the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the third switch sb1 being turned on, and the sixth switch sc2 being turned on.

[0080] The vector sequence obtained by the controller is:

[0081] sv1 p-zv1-zv2-sv2n-zv2-zv1-sv1 p;

[0082] or sv2n-zv2-zv1-sv1 p-zv1-zv2-sv2n

[0083] At this time, the above-mentioned vector sequence and control strategy can be used to sequentially control the on and off of each device in the first half-bridge circuit 10 , the second half-bridge circuit 20 and the three-phase inverter circuit 30 .

[0084] In some embodiments, the first vector may be recorded as sv1n, the second vector may be recorded as sv2p, the first zero vector may be recorded as zv1, and the second zero vector may be recorded as zv2. The control strategy corresponding to sv1n includes the lower bridge arm of the second half-bridge circuit 20 being turned on, the lower bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on; that is, the second switch device dp is turned on, the fourth switch device sn is turned on, the first switch sa1 is turned on, the fourth switch sb2 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to sv2p includes the upper bridge arm of the first half-bridge circuit 10 being turned on, the upper bridge arm of the second half-bridge circuit 20 being turned on, the upper bridge arms of the first half-bridge and the second half-bridge being turned on, and the lower bridge arm of the third half-bridge being turned on; that is, the first switch device sp and the third switch device dn are turned on, the first switch sa1 is turned on, the third switch sb1 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to zv1 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the fourth switch sb2 being turned on, and the sixth switch sc2 being turned on. The control strategy corresponding to zv2 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arms of the first half-bridge and the second half-bridge being turned on, and the lower bridge arm of the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the third switch sb1 being turned on, and the sixth switch sc2 being turned on.

[0085] The vector sequence obtained by the controller is:

[0086] sv1 n-zv1-zv2-sv2p-zv2-zv1-sv1 n;

[0087] or sv2p-zv2-zv1-sv1 n-zv1-zv2-sv2p

[0088] At this time, the above-mentioned vector sequence and control strategy can be used to sequentially control the on and off of each device in the first half-bridge circuit 10 , the second half-bridge circuit 20 and the three-phase inverter circuit 30 .

[0089] Considering that when the control strategy corresponding to the above vector sequence is used to control the on-off of the device, the duty ratio of the first zero vector and the second zero vector is determined, the on-off control performed using the control strategy corresponding to the above vector sequence cannot balance the midpoint voltage between the first capacitor C1 and the second capacitor C2.

[0090] To this end, in some embodiments, the first vector may be recorded as sv1p, the second vector may be recorded as sv2p, the first zero vector may be recorded as zv1, and the second zero vector may be recorded as zv2. The control strategy corresponding to sv1p includes that the upper bridge arm of the first half-bridge circuit 10 is turned on, the upper bridge arm of the second half-bridge circuit 20 is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on; that is, the first switch device sp is turned on, the third switch device dn is turned on, the first switch sa1 is turned on, the fourth switch sb2 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to sv2p includes that the upper bridge arm of the first half-bridge circuit 10 is turned on, the upper bridge arm of the second half-bridge circuit 20 is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on; that is, the first switch device sp and the third switch device dn are turned on, the first switch sa1 is turned on, the third switch sb1 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to zv1 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the fourth switch sb2 being turned on, and the sixth switch sc2 being turned on. The control strategy corresponding to zv2 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arms of the first half-bridge and the second half-bridge being turned on, and the lower bridge arm of the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the third switch sb1 being turned on, and the sixth switch sc2 being turned on.

[0091] The vector sequence obtained by the controller is:

[0092] sv1 p-zv1-zv2-sv2p-zv2-zv1-sv1 p;

[0093] or sv2p-zv2-zv1-sv1 p-zv1-zv2-sv2p

[0094] Since a change is made to the polarity of the first vector or the second vector at this time, when the control strategy corresponding to the above-mentioned vector sequence is adopted to sequentially control the on and off of each device in the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30, the polarity of the first vector or the second vector can be used to balance the midpoint voltage.

[0095] Alternatively, in some embodiments, the first vector may be recorded as sv1n, the second vector may be recorded as sv2n, the first zero vector may be recorded as zv1, and the second zero vector may be recorded as zv2. The control strategy corresponding to sv1n includes the lower bridge arm of the first half-bridge circuit 10 being turned on, the lower bridge arm of the second half-bridge circuit 20 being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on; that is, the second switch device dp is turned on, the fourth switch device sn is turned on, the first switch sa1 is turned on, the fourth switch sb2 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to sv2n includes the lower bridge arm of the first half-bridge circuit 10 being turned on, the lower bridge arm of the second half-bridge circuit 20 being turned on, the upper bridge arms of the first half-bridge and the second half-bridge being turned on, and the lower bridge arm of the third half-bridge being turned on; that is, the second switch device dp and the fourth switch device sn are turned on, the first switch sa1 is turned on, the third switch sb1 is turned on, and the sixth switch sc2 is turned on. The control strategy corresponding to zv1 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the fourth switch sb2 being turned on, and the sixth switch sc2 being turned on. The control strategy corresponding to zv2 includes the first half-bridge circuit 10 and the second half-bridge circuit 20 being short-circuited, the upper bridge arms of the first half-bridge and the second half-bridge being turned on, and the lower bridge arm of the third half-bridge being turned on; that is, the second switch device dp and the third switch device dn being turned on, the first switch sa1 being turned on, the third switch sb1 being turned on, and the sixth switch sc2 being turned on.

[0096] The vector sequence obtained by the controller is:

[0097] sv1 n-zv1-zv2-sv2n-zv2-zv1-sv1 n;

[0098] or sv2n-zv2-zv1-sv1 n-zv1-zv2-sv2n

[0099] Since a change is made to the polarity of the first vector or the second vector at this time, when the control strategy corresponding to the above-mentioned vector sequence is adopted to sequentially control the on and off of each device in the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30, the polarity of the first vector or the second vector can be used to balance the midpoint voltage.

[0100] Considering that if the first switch device sp, the second switch device dp, the third switch device dn and the fourth switch device sn are all active switch devices, in order to prevent the first switch device sp and the second switch device dp from being turned on at the same time and short-circuiting and burning, or the third switch device dn and the fourth switch device sn from being turned on at the same time and short-circuiting and burning, it is necessary to forcibly insert the dead time. To this end, in some embodiments, such as Figure 2As shown, the second switch device dp and the third switch device dn are passive power devices. Exemplarily, the second switch device dp and the third switch device dn can be diodes. Since the second switch device dp and the third switch device dn do not have a short circuit, there is no need to insert a dead time. After the first half-bridge circuit 10 and the second half-bridge circuit 20 have no dead time, it is only necessary to set the dead time for the three-phase inverter circuit 30. However, when the on-off control is performed based on the vector sequence proposed in the above manner, the devices of the three-phase inverter circuit 30 are in the ZVS state during switching, and no dead time is required, so there is no need to set the dead time, which further improves the working efficiency of the three-level inverter circuit.

[0101] Figure 3 A flow chart of a control method for a three-level inverter circuit provided in an embodiment of the present application is shown. The control method for a three-level inverter circuit is applied to the three-level inverter circuit in any of the above embodiments, and specifically, can be applied to the controller in any of the above embodiments.

[0102] In some embodiments, the control method of the three-level inverter circuit includes:

[0103] Step 101, obtaining at least one first vector, at least one second vector, a first zero vector and a second zero vector forming a reference voltage vector;

[0104] Step 102: insert a first zero vector and a second zero vector between adjacent first vectors and second vectors to form a vector sequence between the first vector and the second vector, which is switched by the zero vector, so as to control the on and off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0105] By acquiring at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector, and inserting the first zero vector and the second zero vector between adjacent first vectors and second vectors, a vector sequence is formed between the first vector and the second vector, and the switching is performed by the zero vector, so as to control the on and off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence. Since the switching between the first vector and the second vector is performed by the zero vector, and the voltage is zero when the zero vector is used, there is no switching loss in the process of controlling the on and off of each device at this time, so that the loss of the switching device can be effectively reduced, and the working efficiency of the entire three-level inverter circuit can be improved.

[0106] In some embodiments, a first zero vector and a second zero vector are inserted between adjacent first vectors and second vectors to form a vector sequence between the first vector and the second vector, which is switched by the zero vector, including:

[0107] Sorting the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors, inserting the first zero vector and the second zero vector in sequence between the first vector and the second vector, and inserting the second zero vector and the first zero vector in sequence between the second vector and the first vector, to obtain the vector sequence; or,

[0108] Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is between the two second vectors;

[0109] The second zero vector and the first zero vector are sequentially inserted between the second vector and the first vector, and the first zero vector and the second zero vector are sequentially inserted between the first vector and the second vector, so as to obtain the vector sequence.

[0110] In some embodiments, the control strategy corresponding to the first vector includes the upper bridge arm of the first half-bridge circuit being turned on, the upper bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on;

[0111] The control strategy corresponding to the second vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0112] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0113] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0114] In some embodiments, the control strategy corresponding to the first vector includes the lower bridge arm of the first half-bridge circuit being turned on, the lower bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on;

[0115] The control strategy corresponding to the second vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0116] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0117] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0118] In some embodiments, the control strategy corresponding to the first vector includes the upper bridge arm of the first half-bridge circuit being turned on, the upper bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on;

[0119] The control strategy corresponding to the second vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0120] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0121] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0122] In some embodiments, the control strategy corresponding to the first vector includes the lower bridge arm of the first half-bridge circuit being turned on, the lower bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on;

[0123] The control strategy corresponding to the second vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on;

[0124] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge;

[0125] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0126] Figure 4A schematic structural block diagram of a control device for a three-level inverter circuit provided in an embodiment of the present application is shown. It should be understood that the device and Figure 3 The method embodiment executed in the embodiment corresponds to the method embodiment, and the steps involved in the aforementioned method can be executed. The specific functions of the device can be referred to the description above. To avoid repetition, the detailed description is appropriately omitted here. The device includes at least one software function module that can be stored in a memory in the form of software or firmware or solidified in the operating system (OS) of the device. Specifically, the device can be applied to the charging control subsystem in any of the above embodiments.

[0127] In one embodiment, if Figure 4 As shown, a control device for a three-level inverter circuit is provided, comprising:

[0128] A vector acquisition module 210, configured to acquire at least one first vector, at least one second vector, a first zero vector and a second zero vector forming a reference voltage vector;

[0129] The on-off control module 220 is used to insert a first zero vector and a second zero vector between adjacent first vectors and second vectors to form a vector sequence between the first vector and the second vector, which is switched by the zero vector, so as to control the on-off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0130] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5 As shown, the electronic device may include: a processor 81, a communication interface 82, a memory 83 and a communication bus 840, wherein the processor 81, the communication interface 82 and the memory 83 communicate with each other through the communication bus 840. The processor 81 may call a computer program in the memory 83 to execute a control method for a three-level inverter circuit, for example, including:

[0131] Acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector forming a reference voltage vector;

[0132] A first zero vector and a second zero vector are inserted between adjacent first vectors and second vectors to form a vector sequence between the first vector and the second vector, which is switched by zero vectors, so as to control the on and off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0133] In addition, the logic instructions in the above-mentioned memory 83 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0134] On the other hand, an embodiment of the present application also provides a storage medium, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the control method of the three-level inverter circuit provided in the above embodiments.

[0135] On the other hand, an embodiment of the present application further provides a vehicle, comprising the three-level inverter circuit in any of the above embodiments, or the electronic device in the above embodiments.

[0136] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0137] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-level inverter circuit, characterized in that: It includes a first half-bridge circuit, a second half-bridge circuit, a first capacitor, a second capacitor, a three-phase inverter circuit and a controller; One end of the first half-bridge circuit is connected to one end of the second half-bridge circuit, the other end of the first half-bridge circuit is connected to one end of the first capacitor, the other end of the second half-bridge circuit is connected to one end of the second capacitor, the first capacitor and the second capacitor are connected in series, and one end of the first half-bridge circuit is connected to a midpoint between the first capacitor and the second capacitor; The three-phase inverter circuit comprises a first half bridge, a second half bridge and a third half bridge, wherein the first half bridge, the second half bridge and the third half bridge are connected in parallel, one end of the first half bridge is connected to the midpoint of the first half bridge circuit, and the other end of the first half bridge is connected to the midpoint of the second half bridge circuit; The controller is used to obtain at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector, insert the first zero vector and the second zero vector between adjacent first vectors and second vectors, and form a vector sequence between the first vector and the second vector that is switched by the zero vector, so as to control the first half-bridge circuit, the second half-bridge circuit and the on and off of each device in the three-phase inverter circuit according to the vector sequence; The first vector and the second vector are vectors causing a change in the midpoint current between the first capacitor and the second capacitor; The zero vector includes a first zero vector or a second zero vector, the first zero vector and the second zero vector correspond to different control strategies of the three-phase inverter circuit, the first vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit, and the second vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit.

2. The three-level inverter circuit according to claim 1, characterized in that: The controller is specifically used for: sorting the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors, inserting the first zero vector and the second zero vector in sequence between the first vector and the second vector, and inserting the second zero vector and the first zero vector in sequence between the second vector and the first vector, to obtain the vector sequence; or, Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is between the two second vectors; The second zero vector and the first zero vector are sequentially inserted between the second vector and the first vector, and the first zero vector and the second zero vector are sequentially inserted between the first vector and the second vector, so as to obtain the vector sequence.

3. The three-level inverter circuit according to claim 2, characterized in that: The control strategy corresponding to the first vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on; The control strategy corresponding to the second vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on; The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge; The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

4. The three-level inverter circuit according to claim 2, characterized in that: The control strategy corresponding to the first vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on; The control strategy corresponding to the second vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on; The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge; The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

5. The three-level inverter circuit according to claim 2, characterized in that: The control strategy corresponding to the first vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on; The control strategy corresponding to the second vector includes that the upper bridge arm of the first half-bridge circuit is turned on, the upper bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on; The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge; The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

6. The three-level inverter circuit according to claim 2, characterized in that: The control strategy corresponding to the first vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arm of the first half-bridge is turned on, and the lower bridge arms of the second half-bridge and the third half-bridge are turned on; The control strategy corresponding to the second vector includes that the lower bridge arm of the first half-bridge circuit is turned on, the lower bridge arm of the second half-bridge circuit is turned on, the upper bridge arms of the first half-bridge and the second half-bridge are turned on, and the lower bridge arm of the third half-bridge is turned on; The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge; The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arms of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

7. The three-level inverter circuit according to any one of claims 1 to 6, characterized in that: The first half-bridge circuit includes a first switching device and a second switching device, and the second half-bridge circuit includes a third switching device and a fourth switching device; The first switch device, the second switch device, the third switch device and the fourth switch device are connected in series, and one end of the second switch device connected to the third switch device is connected to the midpoint between the first capacitor and the second capacitor; The second switching device and the third switching device are passive power devices.

8. A control method for a three-level inverter circuit, characterized in that: Applied to the three-level inverter circuit according to any one of claims 1 to 7, the method comprises: Acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector forming a reference voltage vector; A first zero vector and a second zero vector are inserted between adjacent first vectors and second vectors to form a vector sequence between the first vector and the second vector, which is switched by zero vectors, so as to control the on and off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

9. An electronic device comprising a processor and a memory storing a computer program, characterized in that: When the processor executes the computer program, the control method of the three-level inverter circuit according to claim 8 is implemented.

10. A vehicle, characterized in that: It comprises the three-level inverter circuit as described in any one of claims 1 to 7, or the electronic device as described in claim 9.

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