Semiconductor element structure with embedded fuse structure in substrate

Abstract

The invention provides a semiconductor element structure and a preparation method thereof. The semiconductor device structure includes a substrate, a fuse structure and a first word line. The fuse structure comprises a fuse electrode which is arranged in the substrate. The first word line is electrically coupled to the fuse structure. The first word line is disposed within the substrate and spaced apart from the fuse electrode of the fuse structure. The fuse electrode has a side surface protruding toward the first word line.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 217,717 (i.e., the priority date is "July 3, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device structure and a preparation method thereof, and more particularly to a semiconductor device structure including a fuse structure embedded in a substrate. Background Art

[0003] Many integrated circuits (ICs) consist of millions of interconnected components, such as transistors, resistors, capacitors, and diodes, on a single chip on a semiconductor substrate. It is often desirable for an IC to run as fast as possible and consume as little power as possible. Semiconductor ICs often include one or more types of memory, such as complementary metal oxide semiconductor (CMOS) memory, antifuse memory, and electronic fuse memory.

[0004] Electronic fuses are usually integrated into semiconductor ICs by placing a semiconductor material (e.g., polysilicon or a metallization layer) on a dielectric layer (e.g., silicon oxide). A programmed current is applied to blow the dielectric layer, thereby changing the resistivity of the electronic fuse. This is called a programmed "eFuse". However, this structure requires a relatively large breakdown voltage, which may adversely affect the performance of the semiconductor device. In addition, the traditional eFuse structure occupies a relatively large space on the substrate, reducing the density of the IC.

[0005] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a fuse structure and a first word line. The fuse structure includes a fuse electrode disposed in the substrate. The first word line is electrically coupled to the fuse structure. The first word line is disposed in the substrate and is spaced apart from the fuse electrode of the fuse structure. The fuse electrode has a side surface protruding toward the first word line.

[0007] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a fuse structure and a first word line. The fuse structure includes a fuse electrode disposed in the substrate. The first word line is electrically coupled to the fuse structure. A horizontal distance between the fuse electrode of the fuse structure and the first word line changes along a direction away from the substrate.

[0008] Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The method includes providing a substrate; forming a first word line and a second word line in the substrate; forming an opening extending from an upper surface of the substrate and located between the first word line and the second word line; forming an insulating layer in the opening; and forming a metallization layer above the insulating layer to define a fuse structure.

[0009] The embodiments disclosed herein provide a semiconductor device structure. The semiconductor device structure includes a substrate, a fuse structure, a first word line and a second word line. The first word line is electrically coupled to the fuse structure. In addition, the first word line is electrically coupled to the second word line in parallel. As a result, a relatively large drive current can be generated. The fuse electrode of the fuse structure has a side surface that protrudes toward the first word line and the second word line. The semiconductor device structure can have a relatively small resistance value between the fuse structure and the first word line (or the second word line). Therefore, the fuse structure can be blown with a smaller voltage.

[0010] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0012] Figure 1 is a schematic diagram illustrating the circuitry of some embodiments of the present disclosure.

[0013] Figure 2A is a top view schematically illustrating a semiconductor device structure according to some embodiments of the present disclosure.

[0014] Figure 2B is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 2A The semiconductor device structure is shown along the section line AA'.

[0015] Figure 3 It is a schematic flow chart illustrating a method for preparing a semiconductor device structure according to some embodiments of the present disclosure.

[0016] Figure 4A and Figure 4B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0017] Figure 5A and Figure 5B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0018] Fig. 6A and Figure 6B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0019] Fig. 7A and Figure 7B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0020] Fig. 8A and Figure 8B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0021] Fig.9A and Fig. 9B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0022] Fig. 10A and Fig. 10B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0023] Fig.11A and Fig. 11B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0024] Fig. 12A and Fig. 12Bare schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0025] Fig.13A and Fig. 13B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0026] Fig.14A and Fig. 14B are schematic diagrams from different viewing angles, illustrating one or more stages of a method for preparing a semiconductor device structure illustrated in some embodiments of the present disclosure.

[0027] The reference numerals are described as follows:

[0028] 100: Circuit

[0029] 110: Fuse

[0030] 111: Terminal

[0031] 112: Terminal

[0032] 120a: Transistor

[0033] 121a: terminal

[0034] 122a: terminal

[0035] 123a: Terminal

[0036] 120b: Transistor

[0037] 121b: terminal

[0038] 122b: Terminal

[0039] 123b: Terminal

[0040] 200: Semiconductor component structure

[0041] 202: Programming Unit

[0042] 210: Base

[0043] 210s1: Surface

[0044] 210s2: Surface

[0045] 212: Isolation Structure

[0046] 214: Opening

[0047] 214e: Extension

[0048] 216: Air Gap

[0049] 220: Fuse structure

[0050] 220s1: Side

[0051] 220s2: Side

[0052] 222: Isolation layer

[0053] 2221: Fuse dielectric

[0054] 2222: Upper level

[0055] 222s1: Surface

[0056] 222s2: Surface

[0057] 224: Metallization layer

[0058] 224': Conductive layer

[0059] 2241: Fuse electrode

[0060] 2242: Upper plate part

[0061] 2242a: Partial

[0062] 2242b: Partial

[0063] 2242c: Partial

[0064] 224s1: Surface

[0065] 224s2: Surface

[0066] 230a: Transistor

[0067] 230b: Transistor

[0068] 232a: Character line

[0069] 232b: character line

[0070] 232c: character line

[0071] 232d: character line

[0072] 240: Doping area

[0073] 242a: Doping area

[0074] 242b: Doped region

[0075] 244a: Doped region

[0076] 244b: Doped region

[0077] 250: Barrier layer

[0078] 250s1: Surface

[0079] 252: Dielectric layer

[0080] 260: Dielectric Structure

[0081] 262a: Conductive contact point

[0082] 262b: Conductive contact point

[0083] 264a: Conductive layer

[0084] 264b: Conductive layer

[0085] 266: Conductive contact point

[0086] 268: Conductive layer

[0087] 272: Mask

[0088] 282: Gas

[0089] 300: Preparation method

[0090] 301: Steps

[0091] 302: Steps

[0092] 303: Steps

[0093] 304: Steps

[0094] 305: Steps

[0095] 306: Steps

[0096] 307: Steps

[0097] 308: Steps

[0098] 309: Steps

[0099] D1: Distance

[0100] D2: Depth

[0101] N1: Node

[0102] N2: Node

[0103] P1: Processing

[0104] V1: voltage

[0105] V2: voltage DETAILED DESCRIPTION

[0106] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0107] It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the original element may be directly connected to or coupled to the other element or other intervening elements may be present.

[0108] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0109] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0110] It should be understood that in the description of the present disclosure, the term "about" is used to change the quantity of the ingredients, components or reactants of the present disclosure, meaning, for example, the quantitative changes that may occur by typical measurements and liquid handling procedures used to prepare concentrates or solutions. Furthermore, inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the composition or implement the method, etc. may cause changes. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

[0111] Figure 1 1 is a schematic diagram illustrating a circuit 100 of some embodiments of the present disclosure. In some embodiments, the circuit 100 may include a fuse 110, a transistor 120a, and a transistor 120b. In some embodiments, the circuit 100 may be included in a memory element or other suitable element. For example, the memory element may include a one-time programmable (OTP) memory element, a dynamic random access memory (DRAM) element, a static random access memory (SRAM) element, or other suitable memory element.

[0112] The fuse 110 may include a terminal 111 and a terminal 112. The terminal 111 may be electrically connected to a voltage V1, such as VDDQ. The terminal 112 may be electrically connected to the transistors 120a and 120b.

[0113] The transistor 120a can be used as a switch to turn on and / or turn off the fuse 110. The transistor 120a can include a terminal 121a, a terminal 122a, and a terminal 123a. The terminal 121a can be electrically connected to a voltage V2. The terminal 122a can be electrically connected to the fuse 110. The terminal 123a can be electrically connected to a node N1, and the node N1 can be electrically connected to a bit line or a voltage. In some embodiments, the terminal 123a can be electrically connected to ground.

[0114] Transistor 120b can be used as a switch to turn on and / or turn off fuse 110. Transistor 120b can include a terminal 121b, a terminal 122b and a terminal 123b. Terminal 121b can be electrically connected to voltage V2. Terminal 122b can be electrically connected to fuse 110. Terminal 123b can be electrically connected to a node N2, and node N2 can be electrically connected to a bit line or a voltage. In some embodiments, terminal 123b can be electrically connected to ground. In some embodiments, transistors 120a and 120b can be electrically coupled in parallel.

[0115] In some embodiments, the circuit 100 can be used as a programmable unit. In some embodiments, when a relatively large voltage (e.g., 5V or higher) is applied to the terminal 111, a relatively small voltage (e.g., 2V or lower) is applied to the terminals 121a and 121b, and the terminals 123a and 123b are electrically connected to the ground, the fuse 110 may be blown. As a result, the resistance state of the circuit 100 is changed.

[0116] Please refer to Figure 2A and Figure 2B , Figure 2A is a top view of the semiconductor device structure 200, Figure 2B For along Figure 2A Cross-sectional view along the section line A-A'.

[0117] like Figure 2A As shown, the semiconductor device structure 200 may include a plurality of programming units 202 , a substrate 210 and a plurality of isolation structures 212 .

[0118] In some embodiments, each programming unit 202 may be configured to enable Figure 1 1. In some embodiments, each programming unit 202 may be separated by an isolation structure 212. In some embodiments, each programming unit 202 may include a fuse structure 220, a transistor 230a, and a transistor 230b. In some embodiments, the fuse structure 220 may correspond to Figure 1 In some embodiments, the transistors 230a and 230b may correspond to the following Figure 1 Transistors 120a and 120b are shown.

[0119] The substrate 210 may define a plurality of openings 214. In some embodiments, the fuse structure 220 may be disposed within the openings 214. Figure 2B Described in.

[0120] The semiconductor device structure 200 may include word lines 232a, 232b, 232c, and 232d. Each of the word lines 232a, 232b, 232c, and 232d may extend along the Y direction. The word lines 232a, 232b, 232c, and 232d may be configured as follows: Figure 1 Terminal 121a (or terminal 121b) is shown.

[0121] The semiconductor device structure 200 may include a plurality of metallization layers 224. Each metallization layer 224 may be electrically connected to two or more programming units 202. Each metallization layer 224 may be electrically connected to two or more fuse structures 220. Each metallization layer 224 may be configured to apply, transmit or supply a voltage to a fuse electrode, such as a fuse electrode. Figure 1 Terminal 111 of fuse 110 is shown. In some embodiments, each metallization layer 224 may have a plurality of protrusions. In some embodiments, each metallization layer 224 may have a portion 2242a, a portion 2242b, and a portion 2242c. The protrusions of metallization layer 224 may be defined by portions 2242a, 2242b, and 2242c.

[0122] In some embodiments, portion 2242a (or a horizontally extending portion) may extend along the X direction. In some embodiments, portion 2242a may substantially vertically overlap an active region (e.g., a region including fuse structures and transistors) of programming cell 202. In some embodiments, portion 2242a may extend between word lines 232a and 232b.

[0123] In some embodiments, portion 2242b (or a longitudinally extending portion) may extend along the Y direction. In some embodiments, portion 2242b may be substantially orthogonal to portions 2242a and / or 2242c. In some embodiments, portion 2242b may overlap word lines 232a, 232b, 232c, and 232d substantially vertically. In some embodiments, word line 232a may be parallel to portion 2242b of metallization layer 224. In some embodiments, word line 232b may be parallel to portion 2242b of metallization layer 224.

[0124] In some embodiments, portion 2242c (or a horizontally extending portion) may extend along the X direction. In some embodiments, portion 2242a may be parallel to portion 2242c. In some embodiments, portion 2242c may not vertically overlap with the active area of ​​programming unit 202. In some embodiments, portion 2242c may not be aligned with portion 2242a.

[0125] The semiconductor device structure 200 may include a doped region 240 . The doped region 240 may be configured to define source / drain features of the transistors 230 a and 230 b . The doped region 240 may be configured to define multiple channels between the transistors 230 a (or 230 b ) and the fuse structure 220 .

[0126] The semiconductor device structure 200 may include a conductive contact 262a, a conductive contact 262b, and a conductive contact 266. The conductive contact 262a may be disposed on the doped region 240 and electrically connected to the transistor 230a. The conductive contact 262b may be disposed on the doped region 240 and electrically connected to the transistor 230b. The conductive contact 266 may be disposed on the metallization layer 224 and electrically connected to the fuse structure 220.

[0127] like Figure 2B As shown, the substrate 210 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like. The substrate 210 may include an elemental semiconductor in a single crystal form, a polycrystalline form, or an amorphous form, including silicon or germanium; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the Si to Ge composition changes from one ratio at one position of the gradient SiGe feature to another ratio at another position. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, a SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 210 may have a multilayer structure, or the substrate 210 may include a multilayer compound semiconductor structure. The substrate 210 may have a surface 210s1 , which may also be referred to as an upper surface.

[0128] In some embodiments, the substrate 210 may include a well region (not shown). In some embodiments, the well region may include a first conductivity type. In some embodiments, the first conductivity type is a p-type. In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, the first conductivity type is an n-type. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other Group V elements, or any combination thereof.

[0129] The isolation structure 212 may be embedded in the substrate 210. The isolation structure 212 may include a shallow trench isolation (STI), a local oxidation of silicon (LOCOS) structure, or any other suitable isolation structure. The isolation structure 212 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0130] The substrate 210 may define an opening 214 extending from the surface 210s1 in a direction away from the surface 210s1. In some embodiments, the opening 214 may be disposed between the word lines 232a and 232b. The substrate 210 may have a surface 210s2 (or a side surface) defining a sidewall of the opening 214. In some embodiments, the opening 214 may have an elliptical profile. In some embodiments, the surface 210s2 of the substrate 210 may protrude toward the word lines 232a and / or 232b.

[0131] The semiconductor device structure 200 may include an isolation layer 222. The isolation layer 222 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the isolation layer 222 may include a single layer structure or a multilayer structure, which includes an interface layer and a high-k (dielectric constant greater than 7) dielectric layer. The high-k dielectric layer may include metal oxides, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but is not limited thereto. For example, the high-k dielectric layer may also include multiple dopants, such as lanthanum and aluminum. In some embodiments, the isolation layer 222 may include a fuse medium 2221 and an upper layer 2222.

[0132] In some embodiments, the fuse medium 2221 may be disposed within the opening 214. In some embodiments, the fuse medium 2221 is adapted to change from a first conductive state to a second conductive state after a current exceeding a critical level flows through the fuse medium 2221. For example, after a current exceeding a critical level flows through the fuse medium 2221, the resistance of the fuse medium 2221 may be changed. Therefore, after a current exceeding a critical level flows through the fuse structure 220, the resistance of the fuse structure 220 may be changed. In some embodiments, after a current exceeding a critical level flows through the fuse medium 2221, the fuse medium 2221 collapses.

[0133] The fuse medium 2221 may be embedded in the substrate 210. In some embodiments, the fuse medium 2221 may include a surface 222s1 and a surface 222s2. In some embodiments, the surface 222s1 (or a lower surface) may be a substantially flat surface. In some embodiments, the surface 222s1 of the fuse medium 2221 may be substantially parallel to the surface 210s1 of the substrate 210. The surface 222s2 (or a side surface) may extend between the surface 210s1 of the substrate 210 and the surface 222s1 of the fuse medium 2221. In some embodiments, the surface 222s2 may include a curved surface. In some embodiments, the surface 222s2 may protrude toward the word lines 232a and / or 232b.

[0134] The upper layer 2222 may be connected to the fuse medium 2221. The upper layer 2222 may be disposed on the surface 210s1 of the substrate 210. In some embodiments, the fuse medium 2221 and the upper layer 2222 may be a monolithic structure.

[0135] The semiconductor device structure 200 may include a metallization layer 224. The metallization layer 224 may include a conductive material, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (such as tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (such as titanium nitride), transition metal aluminide, or a combination thereof. In some embodiments, the metallization layer 224 may include a fuse electrode 2241 and an upper plate portion 2242.

[0136] In some embodiments, the fuse electrode 2241 may be disposed in the opening 214. In some embodiments, the fuse electrode 2241 may serve as the terminal 111 of the fuse 110. Figure 1As shown. In some embodiments, the fuse electrode 2241 may be disposed on the fuse medium 2221 of the isolation layer 222. The fuse electrode 2241 may be embedded in the substrate 210. In some embodiments, the fuse electrode 2241 may include a surface 224s1 and a surface 224s2. In some embodiments, the surface 224s1 (or a lower surface) may be a substantially flat surface. In some embodiments, the surface 224s1 of the fuse electrode 2241 may be substantially parallel to the surface 210s1 of the substrate 210. The surface 224s2 (or a side surface) may extend between the surface 210s1 of the substrate 210 and the surface 224s1 of the fuse electrode 2241. In some embodiments, the surface 224s2 may include a curved surface. In some embodiments, the surface 224s2 may protrude toward the word lines 232a and / or 232b. In some embodiments, the surface 224s2 of the fuse electrode 224 may overlap vertically with the surface 222s2 of the fuse medium 222. In some embodiments, the fuse electrode 2241 may be replaced by a semiconductor material, such as polysilicon, silicon-germanium and / or other suitable materials.

[0137] The upper plate portion 2242 may be connected to the fuse electrode 2241. The upper plate portion 2242 may be disposed on the surface 210s1 of the substrate 210. The upper plate portion 2242 may be disposed on the upper layer 2222 of the isolation layer 222. In some embodiments, the fuse electrode 2241 and the upper plate portion 2242 may be a monolithic structure. In some embodiments, the upper plate portion 2242 may include Figure 2A 2242a, 2242b, and 2242c are shown. In some embodiments, the upper plate portion 2242 of the metallization layer 224 may vertically overlap the word line 232a. In some embodiments, the upper plate portion 2242 of the metallization layer 224 may vertically overlap the word line 232b. In some embodiments, the upper plate portion 2242 of the metallization layer 224 may extend between the word lines 232a and 232b.

[0138] In some embodiments, the upper plate portion 2242 of the metallization layer 224 may define an air gap 216. In some embodiments, the air gap 216 may be disposed between the transistors 230a and 230b. In some embodiments, the air gap 216 may be disposed between the word lines 232a and 232b. In some embodiments, the air gap 216 may be surrounded by the fuse electrode 2241 of the metallization layer 224. In some embodiments, the air gap 216 may have an elliptical profile. The air gap 216 may have a dielectric constant of about 1, thereby improving leakage of the programming unit 202.

[0139] In some embodiments, the word line 232a may be disposed at a side 220s1 of the fuse structure 220. In some embodiments, the word line 232a may be embedded in the substrate 210. In some embodiments, the word line 232a may be recessed from the surface 210s1 of the substrate 210. The word line 232a may include a conductive material, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof. In some embodiments, the word line 232a may include a semiconductor material, such as polysilicon or other suitable semiconductor materials.

[0140] In some embodiments, the word line 232b may be disposed at a side 220s2 of the fuse structure 220 opposite to the side 220s1. In some embodiments, the word line 232b may be embedded in the substrate 210. In some embodiments, the word line 232a may be recessed from the surface 210s1 of the substrate 210. In some embodiments, the word line 232b may be spaced apart from the word line 232a by the fuse structure 220. In some embodiments, the material of the word line 232b may be the same as or similar to the material of the word line 232a.

[0141] In some embodiments, the doping region 240 may be disposed within the substrate 210. The doping region 240 may be adjacent to the surface 210s2 of the substrate 210. In some embodiments, the doping region 240 may have a second conductivity type different from the first conductivity type. The doping region 240 may surround the word line 232a. The doping region 240 may surround the word line 232b. The doping region 240 may surround the fuse electrode 2241 of the metallization layer 224. The doping concentration of the doping region 240 may be approximately 10 20 Dopant ions / cm 3 In some embodiments, the doping region 240 may include doping regions 242a, 242b, 244a, and 244b.

[0142] The doped region 242a may be disposed between the isolation structure 212 and the word line 232a. In some embodiments, the doped region 242a may function as a source / drain feature of the transistor 230a.

[0143] The doped region 242b may be disposed between the isolation structure 212 and the word line 232b. In some embodiments, the doped region 242b may function as a source / drain feature of the transistor 230b.

[0144] The doped region 244a may be disposed between the word line 232a and the fuse structure 220. The doped region 244a may be disposed between the word line 232a and the fuse electrode 2241 of the metallization layer 224. In some embodiments, the doped region 244a may function as a source / drain feature of the transistor 230a. The doped region 244a may function as a channel for transmitting carriers or accumulating carriers, thereby facilitating the blowing of the fuse structure 220.

[0145] The doped region 244b may be disposed between the word line 232b and the fuse structure 220. The doped region 244b may be disposed between the word line 232b and the fuse electrode 2241 of the metallization layer 224. In some embodiments, the doped region 244b may function as a source / drain feature of the transistor 230b. The doped region 244b may function as a channel for transmitting carriers or accumulating carriers, thereby facilitating the blowing of the fuse structure 220.

[0146] In some embodiments, a distance D1 between the word line 232a and the fuse electrode 2241 of the metallization layer 224 may vary along a direction away from the surface 210s1 of the substrate 210. For example, the word line 232a and the fuse electrode 2241 of the metallization layer 224 may have a smaller distance in the middle of the surface 224s2, and the middle is between the sidewall of the word line 232a and the surface 224s1; the word line 232a and the fuse electrode 2241 of the metallization layer 224 may have a larger distance near the surface 210s1 of the substrate 210. In some embodiments, a depth D2 (or length) of the doped region 240 may be configured to control the position where the isolation layer 222 is blown.

[0147] The semiconductor device structure 200 may include a barrier layer 250 (or an etch stop layer). In some embodiments, the barrier layer 250 may be embedded in the substrate 210. In some embodiments, the barrier layer 250 may be disposed below the fuse structure 220. In some embodiments, the barrier layer 250 may be disposed below the fuse dielectric 2221. In some embodiments, the barrier layer 250 may be disposed below the fuse electrode 2241. In some embodiments, the barrier layer 250 may contact the isolation layer 222. In some embodiments, the material of the barrier layer 250 may be different from the material of the isolation layer 222. The barrier layer 250 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, the barrier layer 250 may have a surface 250s1 (or an upper surface). The surface 250s1 of the barrier layer 250 may be a substantially flat surface. In some embodiments, the surface 250s1 of the barrier layer 250 may be substantially parallel to the surface 210s1 of the substrate 210.

[0148] The semiconductor device structure 200 may include a dielectric structure 260. The dielectric structure 260 may be disposed on the surface 210s1 of the substrate 210. In some embodiments, the dielectric structure 260 may cover the metallization layer 224. The dielectric structure 260 may include silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, Dongran silazane, undoped silicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, plasma enhanced tetraethyl orthosilicate, fluoride silicate glass, carbon doped silicon oxide, or a combination thereof.

[0149] Conductive contact 262a may be disposed on doped region 242a. Conductive contact 262a may be electrically connected to transistor 230a. Conductive contact 262a may penetrate dielectric structure 260. Conductive contact 262a may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof.

[0150] The conductive contact 262b may be disposed on the doped region 242b. The conductive contact 262b may be electrically connected to the transistor 230b. The conductive contact 262b may penetrate the dielectric structure 260. The conductive contact 262b may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0151] The conductive contact 266 may be disposed on the metallization layer 224. The conductive contact 266 may be electrically connected to the fuse structure 220. The conductive contact 266 may penetrate the dielectric structure 260. The conductive contact 266 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0152] The semiconductor device structure 200 may include a conductive layer 264a, a conductive layer 264b, and a conductive layer 268. The conductive layer 264a may be disposed on the dielectric structure 260. The conductive layer 264a may be electrically connected to the conductive contact point 262a.

[0153] Conductive layer 264b may be disposed on dielectric structure 260. Conductive layer 264b may be electrically connected to conductive contact 262b. Although not shown, conductive layer 264a may be electrically connected to conductive layer 264b via a plurality of traces at a higher metallization layer (or via traces at the same level as conductive layer 264a) so that word lines 232a and 232b may have the same potential.

[0154] Conductive layer 268 may be disposed on conductive contact point 266. Conductive layer 268 may be electrically connected to conductive contact point 266.

[0155] In the present embodiment, the word lines 232a and 232b are electrically coupled to the fuse structure 220. In addition, the word lines 232a and 232b are electrically coupled in parallel. As a result, a relatively large driving current can be generated. The metallization layer 224 has a surface 224s2 protruding toward the word lines 232a and 232b. Therefore, the distance between the fuse structure 220 and the transistor 230a (or the transistor 230b) can be reduced. Therefore, the performance of the semiconductor device structure 200 can be enhanced.

[0156] Figure 3 3 is a flow chart illustrating a method 300 for fabricating a semiconductor device structure according to some embodiments of the present disclosure. More specifically, the method 300 may be configured to produce a programming cell including a fuse structure and two transistors configured to switch the fuse structure.

[0157] The manufacturing method 300 begins with step 301 , where a substrate may be provided.

[0158] The fabrication method 300 continues with step 302 where a first word line and a second word line may be formed in the substrate.

[0159] The fabrication method 300 continues with step 303 where an opening may be formed in the substrate and between the first word line and the second word line.

[0160] The fabrication method 300 continues with step 304 where a barrier layer may be formed at the bottom of the opening.

[0161] The fabrication method 300 continues with step 305, where the opening may be enlarged by performing a process (e.g., a hydrogen annealing technique). As a result, the opening may have an extension protruding toward the first word line and the second word line. That is, the sidewall defining the opening may have a curved surface protruding toward the first word line and the second word line.

[0162] The fabrication method 300 continues with step 306, where an isolation layer and a metallization layer may be formed. As a result, a fuse dielectric and a fuse electrode may be formed within the opening of the substrate. An air gap may be formed and surrounded by the fuse electrode.

[0163] The preparation method 30 continues with step 307, wherein a doped region can be formed in the substrate. As a result, a source / drain feature of the transistor can be defined. In addition, a channel between the transistor and the fuse structure can be defined. In this embodiment, a blanket implantation technique can be used to form the doped region.

[0164] The preparation method 300 continues with step 308, wherein an upper plate portion of the metallization layer may be patterned. As a result, the upper plate portion of the metallization layer may have a first portion, a second portion, and a third portion. The first portion may extend horizontally and overlap the fuse structure and the transistor. The first portion may overlap the first word line and the second word line vertically. The second portion may extend longitudinally. The second portion may extend along a direction substantially parallel to an extension direction of the first word line and the second word line. The third portion may be parallel to and not aligned with the first portion.

[0165] The fabrication method 300 continues with step 309, where a first conductive contact and a second conductive contact can be formed on the source / drain features of the transistor. The first conductive contact can be electrically connected to the second conductive contact.

[0166] Preparation method 300 is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional steps may be provided before, during, or after each step of preparation method 300, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 300 may include Figure 3 In some embodiments, the preparation method 300 may include: Figure 3 One or more steps depicted in .

[0167] FIG. 4A to FIG. 14A as well as FIG. 4B to FIG. 14B Various stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure are shown in different perspectives. FIG. 4A to FIG. 14A It is a top view. FIG. 4B to FIG. 14B Along FIG. 4A to FIG. 14A Cross-sectional view along the section line A-A'.

[0168] Please refer to Figure 4A and Figure 4B , a substrate 210 may be provided. An isolation structure 212 may be formed in the substrate 210. The isolation structure 212 may be configured to define a region in which a programming unit including a fuse structure and a transistor is located. Word lines 232a, 232b, 232c, and 232d may be formed in the substrate 210. In some embodiments, a plurality of trenches (not shown) may be formed and recessed from a surface 210s1 of the substrate 210, and a conductive material or a semiconductor material may fill the trenches to form word lines 232a, 232b, 232c, and 232d.

[0169] Please refer to Figure 5A and Figure 5B , a mask 272 can be formed on the surface 210s1 of the substrate 210. The mask 272 may include a photosensitive material, such as a photoresist or other suitable material. The mask 272 may be configured to define an opening 214 of the substrate 210. The manufacturing technology of the opening 214 may include a patterning process. The patterning process may include a lithography process, an etching process, and other suitable processes. The lithography process may include photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (such as hard baking). For example, the etching process may include a dry etching process or a wet etching process.

[0170] Please refer to Fig. 6A and Figure 6B , a dielectric layer 252 may be formed. The dielectric layer 252 may be formed on the mask 272. The dielectric layer 252 may be formed on the substrate 210. The dielectric layer 252 may fill the opening 214. For example, the manufacturing technology of the dielectric layer 252 may include chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes. The dielectric layer 252 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0171] Please refer to Fig. 7A and Figure 7B , a portion of the dielectric layer 252 may be removed to define a barrier layer 250 on the bottom of the opening 214 of the substrate 210 .

[0172] Please refer to Fig. 8A and Figure 8B , a process P1 may be performed. The opening 214 may be enlarged. The opening 214 may include an extension 214e below the surface 210s2 of the substrate 210. The extension 214e may protrude toward the word lines 232a and 232b. In some embodiments, the process P1 may include an annealing technique (or etching technique). In some embodiments, the process P1 may include a hydrogen (H2) annealing technique. In some embodiments, the gas 282 of the annealing technique may include hydrogen or other suitable gases. The barrier layer 250 may be configured to prevent the depth of the opening 214 from expanding. The barrier layer 250 may block the gas 282.

[0173] Please refer to Fig.9A and Fig. 9B, the mask 272 may be removed. An isolation layer 222 may be formed. The isolation layer 222 may include a fuse medium 2221 formed in the opening 214 and an upper layer 2222 formed on the surface 210s1 of the substrate 210. The fuse medium 2221 may be formed on the barrier layer 250. The fuse medium 2221 may have a surface 222s2 protruding toward the word lines 232a and 232b. The manufacturing technology of the mask 272 may include ALD, CVD, PVD, LPCVD, PECVD or other suitable processes.

[0174] Please refer to Fig. 10A and Fig. 10B , a conductive layer 224' may be formed. The conductive layer 224' may be formed on the isolation layer 222. The conductive layer 224' may be formed in the opening 214 and define an air gap 216 in the substrate 210. The manufacturing technology of the conductive layer 224' may include PVD, CVD, ALD, LPCVD, PECVD or other suitable processes.

[0175] Please refer to Fig.11A and Fig. 11B , a doped region 240 can be formed. In some embodiments, a blanket implantation technique can be performed to form the doped region 240. That is, no mask or shield is required to form the doped region 240. Therefore, the cost can be reduced. The doped region 240 may include a doped region 242a, a doped region 242b, a doped region 244a, and a doped region 244b. The source / drain features of the transistors 230a and 230b can be defined. The channel between the transistor 230a (or the transistor 230b) and the fuse structure 220 can be defined.

[0176] Please refer to Fig. 12A and Fig. 12B , the conductive layer 224' may be patterned to define a metallization layer 224. The metallization layer 224 may include a fuse electrode 2241 formed in the opening 214 and an upper plate portion 2242 formed on the surface 210s1 of the substrate 210. The fuse electrode 2241 may have a surface 224s2 protruding toward the word lines 232a and 232b. The metallization layer 224 may include a portion 2242a extending between the word lines 232a and 232b. The metallization layer 224 may include a portion 2242b parallel to the word lines 232a and 232b. The metallization layer 224 may include a portion 2242c parallel to the portion 2242a.

[0177] Please refer to Fig.13A and Fig. 13BA dielectric structure 260 may be formed to cover the substrate 210 and the metallization layer 224. The dielectric structure 260 may be fabricated using CVD, PVD, ALD, LPCVD, PECVD or other suitable processes.

[0178] Please refer to Fig.14A and Fig. 14B , a conductive contact 262a, a conductive contact 262b, a conductive contact 266, a conductive layer 264a, a conductive layer 264b, and a conductive layer 268 can be formed. As a result, a semiconductor device structure such as Figure 2A and Figure 2B A semiconductor device structure 200 is shown.

[0179] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a fuse structure and a first word line. The fuse structure includes a fuse electrode disposed in the substrate. The first word line is electrically coupled to the fuse structure. The first word line is disposed in the substrate and is spaced apart from the fuse electrode of the fuse structure. The fuse electrode has a side surface protruding toward the first word line.

[0180] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a fuse structure and a first word line. The fuse structure includes a fuse electrode disposed in the substrate. The first word line is electrically coupled to the fuse structure. A horizontal distance between the fuse electrode of the fuse structure and the first word line changes along a direction away from the substrate.

[0181] Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The method includes providing a substrate; forming a first word line and a second word line in the substrate; forming an opening extending from an upper surface of the substrate and located between the first word line and the second word line; forming an insulating layer in the opening; and forming a metallization layer above the insulating layer to define a fuse structure.

[0182] The embodiments of the present disclosure provide a semiconductor element structure. The semiconductor element structure includes a substrate, a fuse structure, a first word line and a second word line. The first word line is electrically coupled to the fuse structure. In addition, the first word line is electrically coupled to the second word line in parallel. As a result, a relatively large drive current can be generated. The fuse electrode of the fuse structure has a side surface that protrudes toward the first word line and the second word line. The semiconductor element structure can have a relatively small resistance value between the fuse structure and the first word line (or the second word line). Therefore, the fuse structure can be blown with a smaller voltage. Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure defined by the appended claims. For example, many of the processes discussed above can be implemented in different ways and replaced by other processes or combinations thereof.

[0183] Furthermore, the scope of the present disclosure is not intended to be limited to the specific embodiments of the processes, machines, manufactures, and compositions of matter, means, methods, and steps described in the specification. As will be readily understood from this disclosure by those of ordinary skill in the art, processes, machines, manufactures, compositions of matter, devices, methods, or steps currently existing or to be developed in the future that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, devices, methods, or steps within their scope.

[0184] It should be understood that in the description of this disclosure, an xyz coordinate system is assumed, where x and y refer to dimensions in a plane parallel to the main surface of the structure, and z refers to a dimension perpendicular to the plane. When two features have approximately the same x and y coordinates, the two features are aligned in the topographic structure or one feature is located above the other feature in the topographic structure.

[0185] It should be understood that in the description of the present disclosure, the term "about" is used to change the quantity of the ingredients, components or reactants of the present disclosure, meaning, for example, the quantitative changes that may occur by typical measurements and liquid handling procedures used to prepare concentrates or solutions. Furthermore, inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the composition or implement the method, etc. may cause changes. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

[0186] It should be understood that in the description of the present disclosure, some elements (such as the substrate and the first dielectric layer) in the top view schematic diagram may be omitted for clarity.

[0187] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0188] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device structure, comprising: a base; a fuse structure, including a fuse electrode, disposed in the substrate; a first word line electrically coupled to the fuse structure, wherein the first word line is disposed in the substrate and spaced apart from the fuse electrode of the fuse structure; as well as The fuse electrode has a side surface protruding toward the first word line.

2. The semiconductor device structure as claimed in claim 1, wherein the fuse structure comprises a fuse medium, the fuse electrode is separated from the substrate, and the fuse medium has a side surface protruding toward the first word line.

3. The semiconductor device structure as claimed in claim 1, further comprising an air gap surrounded by the fuse electrode. 4 . The semiconductor device structure as claimed in claim 1 , further comprising a second word line electrically connected to the fuse structure. 5 . The semiconductor device structure as claimed in claim 4 , wherein the first word line is electrically connected in parallel to the second word line. 6 . The semiconductor device structure as claimed in claim 4 , further comprising a metallization layer disposed on the substrate and electrically connected to the fuse electrode of the fuse structure, wherein the metallization layer vertically overlaps the first word line. 7 . The semiconductor device structure as claimed in claim 6 , wherein the metallization layer vertically overlaps the second word line. 8 . The semiconductor device structure as claimed in claim 6 , wherein the metallization layer has a first portion and a second portion, the first portion extends along a first direction, and the second portion extends along a second direction different from the first direction. 9 . The semiconductor device structure as claimed in claim 1 , further comprising a barrier layer disposed below the fuse electrode of the fuse structure. 10 . The semiconductor device structure as claimed in claim 1 , wherein a lower surface of the fuse electrode is substantially parallel to an upper surface of the substrate. 11 . The semiconductor device structure as claimed in claim 1 , further comprising a doped region disposed in the substrate and contacting the side surface of the first word line.

12. A semiconductor device structure, comprising: a base; a fuse structure, including a fuse electrode, disposed in the substrate; as well as a first word line electrically coupled to the fuse structure; A horizontal distance between the fuse electrode of the fuse structure and the first word line changes along a direction away from the substrate.

13. The semiconductor device structure as claimed in claim 12, further comprising a second word line electrically connected to the fuse structure. 14 . The semiconductor device structure as claimed in claim 13 , wherein the first word line is electrically connected in parallel to the second word line. 15 . The semiconductor device structure as claimed in claim 13 , further comprising an air gap disposed between the first word line and the second word line. 16 . The semiconductor device structure as claimed in claim 13 , further comprising a metallization layer disposed on the substrate and electrically connected to the fuse electrode of the fuse structure, wherein the metallization layer vertically overlaps the first word line. 17 . The semiconductor device structure as claimed in claim 16 , wherein the metallization layer has a first portion and a second portion, the first portion extending between the first word line and the second word line, and the second portion being substantially orthogonal to the first portion. 18 . The semiconductor device structure as claimed in claim 16 , wherein the metallization layer vertically overlaps the second word line.

19. The semiconductor device structure as claimed in claim 16, wherein the fuse electrode has a side surface protruding toward the first word line. 20 . The semiconductor device structure as claimed in claim 19 , wherein the fuse electrode has a lower surface substantially parallel to an upper surface of the substrate.

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