Two-dimensional matrix addressable VCSEL array

Abstract

A matrix addressable VCSEL array includes a substrate, a VCSEL block, and a dielectric filling structure. Each block can be addressed individually, and each block contains one or more VCSEL units. The VCSEL cell includes a contact layer on the substrate. The VCSEL unit also includes a first reflective region, an active region, a second reflective region, and a metal layer on the contact layer. The dielectric filling structure is located between two adjacent blocks and penetrates through the first reflection region, the second reflection region, the active region and the contact layer in the direction perpendicular to the substrate.

Description

Technical Field

[0001] The present invention relates to a vertical cavity surface emitting laser (VCSEL) array, and in particular to a two-dimensional (2D) matrix addressable VCSEL array. Background Art

[0002] Compared to edge-emitting semiconductor lasers with horizontal Fabry-Perot resonators and cut faces as mirrors, VCSELs have vertical cavities and emit circular beams perpendicular to the surface. VCSELs have many advantages over edge-emitting semiconductor lasers, such as small size, small beam spot, stable wavelength, narrow spectral width, fast rise time, and low difficulty in manufacturing two-dimensional addressable arrays.

[0003] VCSELs and their arrays have become an indispensable player in consumer electronics, industrial fields, and the automotive industry. In particular, VCSEL arrays provide a suitable light source for real-time high-resolution three-dimensional (3D) sensing. Applications include facial recognition using structured light and optical detection and ranging (lidar) for self-driving cars. In some cases, VCSEL channels in a one-dimensionally addressable (1D) VCSEL array can be addressed individually. However, for large arrays, one-dimensionally addressable (1D) VCSEL arrays are both inefficient and often impractical. In this case, the VCSEL array can be controlled by matrix addressing. Therefore, there is a need for a two-dimensional (2D) matrix-addressable VCSEL array and an economical manufacturing method thereof. Summary of the invention

[0004] The present invention discloses a method and apparatus for a matrix-addressable VCSEL array. In one aspect, the VCSEL array includes a substrate, a VCSEL block, and a dielectric filling structure. Each block is individually addressable and includes one or more VCSEL units. Each VCSEL unit includes a contact layer located on the substrate, a first reflection region located on the contact layer, a second reflection region located on the first reflection region, an active region located between the first and second reflection regions, and a metal layer located on the second reflection region. The dielectric filling structure is located between two adjacent blocks and passes through the first and second reflection regions, the active region, and the contact layer in a direction perpendicular to the substrate.

[0005] In another aspect, a VCSEL array includes a substrate, a VCSEL block, and an isolation structure. Each block is individually addressable and includes one or more VCSEL units. Each VCSEL unit includes a contact layer located on the substrate, a first reflection area located on the contact layer, a second reflection area located on the first reflection area, an active area located between the first and second reflection areas, and a metal layer located on the second reflection area. The isolation structure is located between two adjacent blocks, includes an ion implantation area and a dielectric filling structure, and passes through the first and second reflection areas, the active area, and the contact layer in a direction perpendicular to the substrate. The dielectric filling structure passes through the second reflection area and the active area, and is arranged above the ion implantation area in this direction.

[0006] In another aspect, a method for manufacturing a VCSEL array includes forming a contact layer on a substrate and forming a VCSEL unit on the substrate. Forming each VCSEL unit includes forming a first reflective region on the contact layer, forming an active region on the first reflective region, forming a second reflective region on the active region, and forming a metal layer on the second reflective region. The method also includes forming an isolation trench and filling the isolation trench to form a dielectric filling structure. The isolation trench passes through the first and second reflective regions, the active region, and the contact layer in a direction perpendicular to the substrate. The dielectric filling structure electrically isolates the contact layer into a plurality of blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The subject matter of the invention is distinctly claimed and particularly pointed out in the claims.The above and other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.

[0008] Figure 1 An embodiment according to the present invention schematically shows a cross-sectional view of a VCSEL array at a certain stage in the manufacturing process.

[0009] Figure 2 and Figure 3 According to an embodiment of the present invention, a schematic diagram of the metal layer after deposition is shown. Figure 1 Cross-sectional and top-down views of the VCSEL array shown.

[0010] Figure 4 and Figure 5 According to an embodiment of the present invention, a schematic diagram is shown after the etching process. Figure 2 and Figure 3 Cross-sectional and top-down views of the VCSEL array shown.

[0011] Figure 6 According to an embodiment of the present invention, the oxidation process is schematically shown. Figure 4 and Figure 5 A cross-sectional view of a VCSEL array is shown.

[0012] Figure 7 According to an embodiment of the present invention, Figure 6 A cross-sectional view of a VCSEL array shown at a certain stage in the manufacturing process.

[0013] Figure 8 and Fig. 9 According to an embodiment of the present invention, Figure 7 Cross-sectional and top-down views of a VCSEL array at a certain stage in the fabrication process are shown.

[0014] Fig.10 and Fig.11 According to an embodiment of the present invention, Figure 7 The cross-sectional view and top view of the VCSEL array are shown after ion implantation.

[0015] Fig. 12A and 12B According to an embodiment of the present invention, Fig.10 and Fig.11 Cross-sectional view and top view of the VCSEL array after the filling process.

[0016] Fig.13 According to an embodiment of the present invention, Figure 8 and Fig. 9 A top view of a VCSEL array at a certain stage in the manufacturing process is shown.

[0017] Fig.14 According to an embodiment of the present invention, Fig.13 Electrical connections and terminals of the VCSEL array shown.

[0018] Fig.15 A schematic flow chart of a manufacturing process of a VCSEL array is schematically shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following is a detailed description of the present invention, including diagrams and examples, which further illustrate the objectives, technical solutions and advantages of the present invention. The same reference numbers in the accompanying drawings are used to refer to the same or similar blocks. It should be noted that the exemplary embodiments discussed in this specification are only used to illustrate the present invention, and the present invention is not limited to the disclosed embodiments.

[0020] Figure 1 A cross-sectional view of a VCSEL array 100 at a certain manufacturing stage according to an embodiment of the present invention is shown. Figure 1 The cross-sectional views in the other figures of this specification are located in the XZ plane. The top view of this specification is located in the XY plane. Figure 1As shown, the VCSEL array 100 includes an active region 101, a top reflection region 102, a bottom reflection region 103, and an n + Layer 104. In some cases, n + The thickness of layer 104 may be about 2 to 4 microns. Optionally, a spacer layer (not shown) may be disposed between active region 101 and bottom reflective region 103. + Layer 104, bottom reflection region 103, active region 101 and top reflection region 102 may be sequentially grown on substrate 105. Substrate 105 and the layers grown thereon extend in a horizontal direction, parallel to the XY plane, and perpendicular to the Z axis. Active region 101 may include a multiple quantum well (MQW) structure. Top reflection region 102 and bottom reflection region 103 are electrical conductors. Top reflection region 102 may include a p-type distributed Bragg reflector (DBR), and bottom reflection region 103 may include an n-type DBR. Figure 1 As shown, n + Layer 104 is located between the bottom reflective region 103 and the substrate 105 and acts as a contact layer. In some embodiments, the contact layer may be located between the active region 101 and the bottom reflective region 103. In some other embodiments, the contact layer may be located inside the bottom reflective region 103. For example, the reflective region 103 may include two reflective sub-regions, and the contact layer may be located between the two reflective sub-regions.

[0021] The substrate 105 may be a conductive, semi-insulating or insulating semiconductor substrate, for example, including a III-V compound, such as gallium arsenide (GaAs), indium phosphide (InP) or gallium nitride (GaN). Based on the GaAs material system, the output wavelength range of the VCSEL array 100 may be 880 to 1100 nanometers; based on the InP material system, it may be 1200 to 1700 nanometers; based on the GaN material system, it may be 400 to 550 nanometers.

[0022] The VCSEL array 100 may represent a top-emitting VCSEL structure, where an output beam is emitted through a top surface when current is applied. Alternatively, the VCSEL array 100 may also have a bottom-emitting VCSEL structure, where an output beam is emitted through a substrate 105 and a bottom surface. In the following description, the VCSEL array 100 takes a top-emitting VCSEL structure as an example.

[0023] Between the top reflective region 102 and the bottom reflective region 103, for example, between the top reflective region 102 and the active region 101, a high aluminum content layer 106 is formed. The aluminum content of the layer 106 is relatively high, and is used to form an oxide layer and oxide holes. The DBR (distributed Bragg reflector), the active region, the high aluminum content layer and the n+ layer 104 can be epitaxially grown on the top surface of the substrate 105. The epitaxial growth can be achieved by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).

[0024] Figure 2 and Figure 3 A cross-sectional view and a top view of the VCSEL array 100 after deposition of the metal layer 107 are schematically shown. Figure 2 for Figure 3 AA' line view. After the top reflection area 102 is completed, metal deposition is performed to form a metal layer 107. The metal layer 107 can be a thin gold layer or a nickel / gold layer, having a ring or annular shape. Therefore, the metal layer 107 can also be called a metal ring 107. The metal ring 107 grows on the top reflection area 102. For example, a layer of photoresist can be deposited on the top surface of the VCSEL array 100. Block areas of the photoresist layer can be exposed and developed, while the unexposed and undeveloped blocks are removed. Then, the metal ring 107 can be deposited in the areas where the photoresist layer is removed, respectively, by a stripping process. In some aspects, the metal layer can be deposited by chemical vapor deposition (CVD), molecular beam epitaxy (MBE) or electron beam physical vapor deposition (EBPVD).

[0025] After the growth of the metal ring 107 is completed, a deposition process is performed to grow a dielectric layer 108 (e.g., a silicon nitride layer) on the top surface of the array 100 by CVD or atomic layer deposition (ALD). The layer 108 covers the metal ring 107 and certain other areas of the array 100. In some aspects, the layer 108 has a thickness equal to the half-wave optical thickness of the laser wavelength and acts as a transparent passivation layer to protect the metal ring 107 and reduce reflections from the top surface. In other aspects, an additional dielectric layer (not shown) may be deposited on the layer 108. In these cases, the layer 108 and the additional dielectric layer together form a transparent passivation layer.

[0026] like Figure 2 and Figure 3 As shown, layer 108 covers metal rings 107. The areas of layer 108 covering metal rings 107 form protruding ring structures 109, which reflect the pattern and arrangement of metal rings 107 of VCSEL array 100. Take VCSEL array 100 including VCSELs 1-16 as an example. Figure 2 and Figure 3The number, size and shape of VCSELs in other figures of this specification, the size and pattern of metal ring 107, and the size and arrangement of VCSEL array 100 are for illustrative and descriptive purposes only. VCSEL array 100 may also have other applicable VCSELs, metal rings, sizes, patterns and arrangements according to different aspects of the present invention.

[0027] Figure 4 and Figure 5 The cross-sectional view and the top view of the VCSEL array 100 after the etching process according to an embodiment of the present invention are schematically shown. Figure 4 for Figure 5 BB' line view. The etching process can be a dry etching (e.g., reactive ion etching (RIE)) or a combination of dry and wet etching processes. The etching process creates a trench 110 and a VCSEL step on the substrate 105. In some aspects, the bottom of the trench 110 reaches a position between the active area 101 and the bottom reflective area 103. In other aspects, the bottom of the trench 110 reaches a position in the bottom reflective area 103.

[0028] The VCSEL step and the trench 110 are configured for an oxidation process. On the sidewalls of the VCSEL step, the active region 101 , the top reflective region 102 and the end of the high aluminum content layer 106 are exposed, while the metal ring 107 is covered and protected by the dielectric layer 108 .

[0029] Figure 6 The schematic diagram shows a cross-sectional view of a VCSEL array 100 after an oxidation process according to an embodiment of the present invention. After the end of the high aluminum content layer 106 is exposed on the step sidewall, a timed oxidation process can be performed in a steam environment or a dry oxygen environment at a high temperature (e.g., 400 degrees Celsius). The block high aluminum content layer 106 will be oxidized to form an oxide layer 111. The oxidation rate is strongly related to the aluminum content. For example, the layer 106 may contain Al 0.9 Ga 0.1 As or AlAs. Some incompletely oxidized areas of layer 106 form circular oxide holes 112, which provide electrical and optical confinement for the VCSEL. Sixteen oxide holes 112 are fabricated, corresponding to VCSELs 1-16. Figure 6 An output window 113 is also shown within the metal layer ring. The oxide aperture 112, metal ring 107, and output window 113 are concentric in the Z direction of the VCSEL. The terms "VCSEL," "VCSEL unit," and "VCSEL emitter" used herein have the same meaning and refer to one VCSEL unit in the array 100.

[0030] Figure 7A cross-sectional view of a VCSEL array 100 at a certain stage in the manufacturing process according to an embodiment of the present invention is schematically shown. After the oxide hole 112 is formed, the space around the VCSEL step, including the trench 110, is filled with a dielectric material 114. The dielectric material 114 may include, for example, silicon oxide or silicon nitride. In some embodiments, a thin dielectric layer, such as a silicon oxide layer or a silicon nitride layer (not shown) may be deposited on the sidewalls of the VCSEL step. The thin dielectric layer may be used to prevent electrical leakage. In some cases, after the thin dielectric layer is formed, the dielectric material 114 may be deposited on the thin dielectric layer to fill the trench 110, and then planarized. In other cases, after the thin dielectric layer is formed, the dielectric material 114 may not be deposited on the thin dielectric layer to fill the trench 110. In this case, the space around the VCSEL step remains empty, and the VCSEL step can be separated by filling the trench with air or an inert gas (such as nitrogen). In the following description, the space surrounding the VCSEL step is exemplarily filled with the dielectric material 114 .

[0031] Figure 8 and Fig. 9 The cross-sectional view and the top view of the VCSEL array 100 at a certain stage of the manufacturing process according to an embodiment of the present invention are schematically shown. Figure 8 for Fig. 9 After the dielectric material 114 is deposited, an isolation trench (not shown) is formed by dry etching (e.g., reactive ion etching (RIE)) or a combination of dry etching and wet etching processes. The isolation trench extends horizontally along the Y direction. In the Z direction, the isolation trench penetrates the layer made of the dielectric material 114, that is, through the top reflective region 102 and the active region 101. In the vertical direction, the isolation trench also penetrates the bottom reflective region 103 and the active region 101. + The dielectric layer 104 is deposited into the substrate 105. Afterwards, one or more dielectric materials (e.g., silicon oxide and silicon nitride) are deposited to form a dielectric filling structure 115 to fill the isolation trench. The filling structure 115 not only provides isolation function, but also facilitates planarization and deposition of additional metal layers on the VCSEL array. In some embodiments, before the filling structure 115 is formed, a thin dielectric layer may be deposited on the sidewalls of the isolation trench. In this way, the thin dielectric layer extends vertically and is located between the filling structure 115 and the active area 101, the top reflective area 102, the bottom reflective area 103 and the n + Between layers 104.

[0032] like Figure 8 and Fig. 9 As shown, the filling structure 115 extends horizontally along the Y direction and completely passes through the top reflection area 102, the active area 101, the bottom reflection area 103 and the n +The bottom of the filling structure 115 is deep into the substrate 105. The filling structure 115 is n + Layer 104 is cut and electrically isolated into two blocks. Filling structure 115 separates array 100 into two VCSEL blocks along the X direction and is located between the two VCSEL blocks. + The shapes, patterns, and sizes of the layer blocks and VCSEL blocks are for illustration only. The VCSELs in each VCSEL block have n + The layer block serves as a common cathode. Since the substrate 105 is semi-insulating or insulating (eg, resistivity greater than 107Ωm), the common cathodes of the two VCSEL regions are electrically isolated.

[0033] In other cases, the isolation trenches may not be etched. Instead, ion implantation may be performed to + Layer 104 is cut and electrically isolated into two blocks, transforming array 100 into two VCSEL blocks. However, the manufacturing cost of the ion implantation method may be higher than the isolation trench method. In addition, the reliability of the filling structure 115 at high temperature is much better than that of the ion implantation area. In addition, it is possible to check whether the filling structure 115 has achieved the design goal after the etching step and before the complete process is completed. However, the isolation effect of ion implantation can usually be evaluated only after all processes are completed.

[0034] Fig.10 and Fig.11 The cross-sectional view and the top view of the VCSEL array 100 after ion implantation according to an embodiment of the present invention are schematically shown. Fig.10 for Fig.11 DD' line view. Fig.10 and Fig.11 Shown with Figure 8 and Fig. 9 Another embodiment different from the embodiment shown. Optionally, in the Figure 7 After the dielectric material 114 is deposited as shown, a trench 116 can be formed by dry etching (e.g., RIE) or a combination of dry etching and wet etching processes. The trench 116 extends horizontally along the Y direction. In the Z direction, the trench 116 penetrates the layer made of the dielectric material 114, that is, through the top reflection area 102 and the active area 101. In some embodiments, the trench 116 may reach the bottom reflection area 103. Optionally, the trench 116 may reach the layer between the active area 101 and the bottom reflection area 103. After etching the trench 116, the trench 116 can be used as an isolation area for an ion implantation process. An ion implantation area 117 is formed below the trench 116. The ion implantation area 117 vertically penetrates the bottom reflection area 103 and the n+ layer 104 and enters the substrate 105. In the horizontal direction, the ion implantation area 117 extends along the Y direction, similar to the trench 116.

[0035] Fig. 12A and Fig. 12B The cross-sectional view and the top view of the VCSEL array 100 after the filling process according to the embodiment of the present invention are schematically shown. Fig. 12A for Fig. 12B EE' view. After the ion implantation is completed, one or more dielectric materials (e.g., silicon oxide and silicon nitride) are deposited to fill the trench 116 to form a dielectric filling structure 118. Similar to the filling structure 115, the filling structure 118 provides an isolation function and facilitates planarization and the formation of additional metal layers on the VCSEL array. Optionally, before forming the filling structure 118, a thin dielectric layer can be deposited on the sidewalls of the trench 116. The thin dielectric layer extends in the vertical and horizontal directions and is located between the filling structure 118 and the active area 101, the top reflection area 102 and the ion implantation area 117.

[0036] like Fig. 12A and Fig. 12B As shown, the position and extension range of the filling structure 118 are similar or identical to those of the trench 116. For example, the filling structure 118 extends in the Y direction in the horizontal direction. In the Z direction, the filling structure 118 completely passes through the top reflection area 102 and the active area 101, and then passes through the bottom reflection area 103. The filling structure 118 is formed on the top surface of the ion implantation area 117. The filling structure 118 and the ion implantation area 117 are stacked in the vertical direction to form an isolation structure (not shown). The isolation structure includes the stacked filling structure 118 and the ion implantation area 117, which completely passes through the top reflection area 102, the active area 101, the bottom reflection area 103 and the n in the vertical direction. + The bottom of the isolation structure penetrates the substrate 105. Similar to the filling structure 115, the isolation structure + Layer 104 is electrically cut and separated into two groups of electrically isolated blocks, separating array 100 into two VCSEL blocks along the X direction and located between the two VCSEL blocks. As shown below, these VCSEL blocks may be referred to as columns of array 100 in some cases. In other cases, the VCSEL blocks may also be referred to as rows of array 100. Each group of n + The layer block can serve as a common cathode for the group of VCSELs. Since the substrate 105 is semi-insulating or insulating, the common cathodes of the two VCSEL blocks are electrically isolated. Since the ion implantation is performed through the trench 116, the implantation depth is reduced compared to the above ion implantation process. Therefore, the cost of ion implantation may be reduced.

[0037] Fig.13 A top view of a VCSEL array 100 at a certain stage in the manufacturing process is schematically shown according to an embodiment of the present invention. Fig. 912, a filling structure 115 and an isolation structure with a filling structure 118 are respectively manufactured. In addition, selected metal rings 107 may be connected to a common anode. Fig. 9 Taking the case in FIG. 10 as an example, the method shown below is also applicable to the case in FIG. 12 . The dielectric layer 108 is selectively etched to expose the block area of ​​the metal ring 107. In order to enable the VCSEL array 100 to be addressed in a matrix manner, a metal material is deposited by, for example, a CVD process to form a connection layer 119. The connection layer 119 can be a thin gold layer or a Ni / Au layer that connects the metal ring 107 to the adjacent metal ring 107. The selected metal rings 107 are electrically connected together through a plurality of connection layers 119. Fig.13 As shown, the metal ring (i.e. anode) connecting the two blocks corresponds to n + The VCSELs in the VCSEL array 100 can be viewed as columns extending in the Y direction and rows extending in the X direction. The cathodes of the VCSELs in the columns are connected to a common cathode (i.e., n + The anodes of the VCSELs in the row are connected to a common anode through the connection layer 119. The columns and rows form a matrix. Therefore, the array 100 becomes addressable in a matrix.

[0038] 12, after the fill structures 118 are fabricated, a connection layer may be deposited to connect selected metal rings 107 from a row. Thus, in a similar manner, the connection layer is used to define the rows of the array 100, while the isolation structures, particularly the ion implanted regions 117, are used to define the columns of the array 100.

[0039] Fig.141 is a diagram of schematic electrical connections and terminals of a VCSEL array 100 according to an embodiment of the present invention. The array 100 can be viewed as a 2x 2 matrix. Cathode terminals N1 and N2 are connected to the common cathodes of the VCSELs in two columns, respectively. Anode terminals P1 and P2 are connected to the common anodes of the VCSELs in two rows, respectively. A filling structure 115 is located in the X direction to separate two columns or VCSELs in two columns. Similarly, an ion implantation region 117 (or an isolation structure) is located in the X direction to separate two columns or VCSELs in two columns. The array 100 includes four regions that can be addressed by anode and cathode terminals. For example, VCSELs 1, 2, 5, and 6 form a region that can be powered simultaneously by cathode terminal N1 and anode terminal P1. The filling structure 115 is located between two adjacent regions in the X direction, or between VCSELs in two adjacent regions in the X direction. In a similar manner, the ion implantation region 117 (or a filling structure 118 or an isolation structure) is located between two adjacent regions in the X direction, or between VCSELs in two adjacent regions in the X direction. Compared with one-dimensional addressing of each VCSEL block, the two-dimensional matrix addressing method requires fewer metal lines and may make the packaging of the VCSEL array 100 more compact. Optionally, the VCSEL array may include a matrix addressable block including one or more VCSEL units. The arrangement of columns and rows in the VCSEL array (e.g., the number of columns and rows, the number and arrangement of VCSEL units in the columns and rows) can be determined according to actual needs.

[0040] In certain embodiments, such as Figure 2 The 104 layers shown may be p + Layers, instead of n as described above + In this case, the bottom reflection region 103 may include a p-type DBR, and the top reflection region 102 may include an n-type DBR. Fig.14 N1 and N2 in the circuit become anode terminals, and P1 and P2 become cathode terminals. + Change the layer to p + When the layers are formed, the above manufacturing method can remain unchanged or similar.

[0041] Fig.15 FIG. 2 is a flow chart of a schematic manufacturing process 200 of a matrix addressable VCSEL array according to an embodiment of the present invention. The process 200 begins by providing a semi-insulating or insulating semiconductor substrate (such as a semiconductor wafer). In step 201, an n-type semiconductor substrate is formed by epitaxial growth on the substrate. +layer as a contact layer. In step 202, multiple layers are formed as a bottom reflection region by epitaxial growth on the contact layer. The bottom reflection region includes a DBR structure. In step 203, an active region is formed by epitaxial growth on the bottom reflection region. The active region may include a quantum well structure, such as an MQW configuration. In addition, multiple layers are formed as a top reflection region by epitaxial growth on the active region. The top reflection region includes another DBR structure. In some aspects, a high aluminum content layer is formed between the top reflection region and the active region. The aluminum content of the high aluminum content layer is relatively higher than that of the other epitaxial layers.

[0042] In step 204, a metal layer is deposited as a p-metal onto the top reflective region. In some cases, the metal layer forms a ring structure for each VCSEL unit, which may be referred to as a metal ring. The metal ring surrounds the output window of the VCSEL unit.

[0043] In addition, a dielectric layer (such as a silicon nitride layer) is deposited on the top surface of the VCSEL array. The dielectric layer covers the metal ring and the output window. In some embodiments, the dielectric layer is formed as a transparent layer of the output window.

[0044] In step 205, etching is performed to form a VCSEL step and a groove around the VCSEL step. The end of the high aluminum content layer is exposed on the side wall of the step. In the horizontal plane, the groove surrounds or surrounds each VCSEL step. The depth of the groove is set to expose the high aluminum content layer on the side wall of the step. In some aspects, the groove may vertically pass through the top reflective area and the active area. As needed, the groove may pass through the top reflective area and the active area and go deep into the bottom reflective area.

[0045] In step 206, an oxidation process (e.g., using hot water vapor) is performed to oxidize the exposed high aluminum content layer through the trench. The oxidation process forms an oxide layer and an oxide hole. In some cases, the oxide hole may have a circular structure and is made for each VCSEL unit. The oxide hole may have other shapes as needed.

[0046] In step 207, a thin dielectric film (e.g., a silicon oxide film or a silicon nitride film) is deposited to cover and protect the sidewalls of the steps and the grooves. Next, an etching process is performed to etch out the isolation grooves. The isolation grooves extend deep into the substrate, penetrate the active area, the top and bottom reflective areas, and the n+ contact layer, and separate the contact layer into electrically independent blocks. Further, another thin dielectric film (e.g., a silicon nitride film) is deposited to cover and protect the sidewalls of the isolation grooves. Next, a material such as a polymer or gold can be deposited on the thin dielectric film to fill the isolation grooves and form a planarization structure for subsequent processes.

[0047] In step 208, the block dielectric layer is etched away to form openings to expose certain blocks of metal rings. Certain openings connect two metal rings of adjacent VCSELs. Further, a metal connection layer is deposited in the openings to electrically connect selected metal rings. The VCSELs of the metal rings connected together by the connection layer form a row of the VCSEL array. As mentioned above, the connection layer is used to electrically connect the metal rings in a row of the VCSEL array. In some cases, the contact layer blocks are used to electrically connect the VCSELs in a column of the VCSEL array. In other cases, the contact layer blocks and the metal layer directly deposited on the contact layer are used together to electrically connect the VCSELs in a column of the VCSEL array. The rows and columns of the VCSEL array can also be referred to as the rows and columns of the matrix.

[0048] The matrix-addressable VCSEL array illustrated above corresponds to a top-emitting VCSEL. In some other embodiments, the above VCSEL structure can be modified to make a matrix-addressable bottom-emitting VCSEL array. The bottom-emitting VCSEL array can be packaged using a mature flip-chip method.

[0049] As shown above, the dielectric fill structure can be used to separate the n+ contact layer into multiple blocks. Compared with the method of separating the contact layer using ion implantation, the manufacturing cost of the matrix addressable VCSEL array may be reduced. In addition, in some embodiments, the ion implantation is performed through the trench. The contact layer is separated into blocks through the shallow ion implantation area. This may also save manufacturing costs.

[0050] Although specific embodiments of the present invention have been disclosed, it will be appreciated by those skilled in the art that these specific embodiments may be modified without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should not be limited to the specific embodiments. In addition, the appended claims are intended to cover all applications, modifications and embodiments within the scope of the present invention.

Claims

1. A vertical cavity surface emitting laser (VCSEL) array, comprising: - substrate; - Multiple blocks, each block is individually addressable and includes one or more VCSEL cells, each VCSEL cell includes: - a contact layer on the substrate, - a first reflective area on the contact layer, - a second reflection area on the first reflection area, - an active area between the first reflective area and the second reflective area, - a metal layer on the second reflective area; - a dielectric filling structure located between two adjacent blocks of the plurality of blocks, wherein the dielectric filling structure passes through the first reflective region, the second reflective region, the active region, and the contact layer in a direction perpendicular to the substrate.

2. The VCSEL array according to claim 1, characterized in that: The contact layer is an n+ layer.

3. The VCSEL array according to claim 1, characterized in that: The contact layers of the VCSEL units of each block are connected to a common cathode.

4. The VCSEL array according to claim 1, characterized in that: The metal layers of the VCSEL units in each block are connected to a common anode.

5. The VCSEL array according to claim 1, characterized in that: The multiple blocks form a two-dimensional (2D) matrix addressable array.

6. The VCSEL array according to claim 1, characterized in that: The dielectric fill structure includes one or more dielectric materials. 7 . The VCSEL array according to claim 1 , further comprising a dielectric layer, wherein the dielectric layer is located between the active region and the dielectric filling structure and extends along the direction.

8. A vertical cavity surface emitting laser (VCSEL) array, comprising: - substrate; - Multiple blocks, each block is individually addressable and includes one or more VCSEL cells, each VCSEL cell includes: - a contact layer on the substrate, - a first reflective area on the contact layer, - a second reflection area on the first reflection area, - an active area between the first reflective area and the second reflective area, - An isolation structure located between two adjacent blocks of the plurality of blocks, the isolation structure comprising an ion implantation region and a dielectric filling structure, and passing through a first reflective region, a second reflective region, an active region and a contact layer in a direction perpendicular to the substrate, the dielectric filling structure passing through the second reflective region and the active region and covering the ion implantation region in the direction.

9. The VCSEL array according to claim 8, characterized in that: The contact layer is an n+ layer.

10. The VCSEL array according to claim 8, characterized in that: The contact layers of the VCSEL units of each block are connected to a common cathode.

11. The VCSEL array according to claim 8, characterized in that: The metal layers of the VCSEL units in each block are connected to a common anode.

12. The VCSEL array according to claim 8, characterized in that: The multiple blocks form a two-dimensional (2D) matrix addressable array.

13. The VCSEL array according to claim 8, characterized in that: The ion implantation region passes through the contact layer along the direction. 14 . The VCSEL array according to claim 8 , further comprising a dielectric layer, wherein the dielectric layer is located between the active region and the dielectric filling structure and extends along the direction.

15. A method of manufacturing a vertical cavity surface emitting laser (VCSEL) array, comprising: forming a contact layer over the substrate; A plurality of VCSEL units are formed on the substrate, wherein forming each VCSEL unit comprises: forming a first reflective region on the contact layer, forming an active region on the first reflective region, forming a second reflective region on the active region, and forming a metal layer on the second reflective area; forming an isolation trench, wherein the isolation trench passes through the first reflective region, the second reflective region, the active region, and the contact layer in a direction perpendicular to the substrate; and The isolation trench is filled to form a dielectric filling structure, wherein the dielectric filling structure electrically isolates the contact layer into a plurality of blocks.

16. The method according to claim 15, characterized in that: The contact layer is an n+ layer.

17. The method according to claim 15, characterized in that: The plurality of blocks correspond to a plurality of columns of the VCSEL array, and the VCSEL units of each column are connected to a common cathode.

18. The method according to claim 15, further comprising forming a plurality of connection layers, wherein the VCSEL units connected by the plurality of connection layers form a plurality of rows of a VCSEL array, and a metal layer of the VCSEL units in each row is connected to a common anode.

19. The method according to claim 15, characterized in that: The dielectric fill structure includes one or more dielectric materials.

20. The method of claim 15, further comprising forming a dielectric layer on sidewalls of the isolation trench before filling the isolation trench to form the dielectric filling structure.

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