Charge domain signed multiplication, multi-bit multiplication and accumulation circuit and chip thereof

Abstract

The present invention belongs to the field of integrated circuits, and specifically relates to a charge domain signed multiplication, multi-bit multiplication and accumulation operation circuit and its chip. The charge domain signed multiplication is composed of 8 PMOS tubes P1~P8, 13 NMOS tubes N1~N13, and a capacitor C; wherein P1~P5 and N1~N7 constitute a sign bit operation unit, and the remaining elements constitute a value bit operation unit. The circuit divides the multiplication between signed numbers into two stages, firstly performing the multiplication operation of the sign bit bracket in 12T-SRAM, outputting the result to 9T1C-SRAM, and then performing the multiplication operation between the value bits. The charge domain signed multi-bit multiplication and accumulation operation circuit is obtained by improving the SRAM circuit with 12T-SRAM and 9T1C-SRAM as basic units. The present invention solves the problem that the existing CIM circuit is difficult to realize multiplication or Mac operation with both input and weight as signed numbers.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a charge domain signed multiplication and multi-bit multiplication-accumulation operation circuit and a chip thereof. Background Art

[0002] With the development of artificial intelligence technology, edge AI devices have an increasing demand for energy efficiency. In the traditional von Neumann architecture, the memory and processor are separated, and the frequent data transmission between them limits energy efficiency. In contrast, the Computing In Memory (CIM) architecture combines storage units with computing units, and uses parallel computing in the storage array to reduce the energy consumption caused by data movement and improve computing speed.

[0003] The existing in-memory computing architecture is roughly divided into analog domain, digital domain, and time domain. The analog domain can be divided into current domain and charge domain. Due to the channel length modulation effect and the excessive discharge of transistors into the linear region, the current domain leads to uneven discharge speed, which brings great nonlinearity to the calculation results and cannot open multiple rows for calculation. The charge domain uses anti-PVT MOM capacitors to calculate through the principle of capacitive coupling, which has higher linearity and energy efficiency than the current domain. There are still some challenges in the existing charge domain CIM design. For example, in neural networks, in order to meet the requirements of calculation accuracy in complex application scenarios, it is common to quantize both inputs and weights into a signed integer. However, the existing charge domain CIM only supports BNN, MAC operations with signed input and unsigned weights, or unsigned input and signed weights. Summary of the invention

[0004] In order to overcome the problem that the existing charge domain CIM circuit is difficult to implement multiplication or Mac operation when both the input and the weight are signed numbers, the present invention provides a charge domain signed multiplication and multi-bit multiplication-accumulation operation circuit and a chip thereof.

[0005] The technical solution provided by the present invention is:

[0006] A charge domain signed multiplication circuit is used to perform multiplication operations between signed input numbers and signed weights, and is composed of 8 PMOS transistors P1-P8, 13 NMOS transistors N1-N13, and a capacitor C. Among them, P1-P5 and N1-N7 constitute a sign bit operation unit, and the remaining components constitute a value bit operation unit. The circuit connection relationship is:

[0007] P1~P2 and N1~N4 constitute a 6T-SRAM unit including storage nodes Q1 and QB1 in the sign bit operation unit. The drain of N5 and the source of P3 are connected to S_INB, the drain of N6 and the source of P4 are connected to S_IN; the sources of N6 and N5, the drains of P3 and P4 are connected to the gates of N7 and P5; the drain of N7 is connected to IN-, and the source of P5 is connected to IN+.

[0008] P6~P7 and N8~N11 constitute a 6T-SRAM unit including storage nodes Q2 and QB2 in the numerical bit operation unit. The drains of P5 and N12 are connected to the sources of P8 and N7; the gate of N12 is connected to the storage node Q2, and the gates of P8 and N13 are connected to the storage node QB2; the sources of N12 and N13 and the drain of P8 are connected to the upper plate of capacitor C, the calculation bit line MBL is connected to the lower plate of the capacitor, and the drain of N13 is connected to 1 / 2VDD.

[0009] The two groups of storage nodes in the sign bit operation unit and the value bit operation unit are used to store the sign bit and value bit of the weight respectively. S_IN and S_INB are used to input the sign bit of the encoded input number; IN+ and IN- are used to input the value bits of the encoded positive input number and negative input number respectively; MBL is used to output the result of the multiplication operation.

[0010] In the charge domain signed multiplication circuit of the present invention, when S_IN=1, S_INB=0, it indicates that the sign of the input number is positive; when S_IN=0, S_INB=1, it indicates that the sign of the input number is negative. When Q1=1, QB1=0, it indicates that the sign of the weight is positive; when Q1=0, QB1=1, it indicates that the sign of the weight is negative; when Q2=1, QB2=0, it indicates that the value of the weight is "1"; when Q2=0, QB2=1, it indicates that the value of the weight is "0".

[0011] In the charge domain signed multiplication circuit of the present invention, when the signed product of the input number and the weight is positive, the sign bit operation unit selects the positive input number of IN+ input; when the signed product of the input number and the weight is negative, the == sign bit operation unit selects the negative input number of IN- input.

[0012] In the charge domain signed multiplication circuit of the present invention, when the bit line voltage of the calculation bit line of the MBL is 1 / 2VDD, it means that the product result is 0. When the bit line voltage is 0-1 / 2VDD, it means that the product result is a negative value; when the bit line voltage is 1 / 2VDD-VDD, it means that the product result is a positive value; the numerical values ​​of positive and negative values ​​are related to the voltage of the bit line voltage.

[0013] As a further improvement of the present invention, the numerical bits IN+ and IN- of the input number are encoded by a bidirectional DAC. When the numerical bits of the input number IN are M bits, the bidirectional DAC includes a positive DAC composed of M+2 capacitors and a negative DAC composed of M+2 capacitors. The ratio of the capacitance values ​​of the capacitors in the positive DAC and the negative DAC is 1:1:2…:2 M-1 :2 M .

[0014] Among them, the upper plate of the capacitor with the largest capacitance value in the positive DAC is connected to VDD, the upper plate of the capacitor with the smallest capacitance value is grounded, and the upper plates of the remaining capacitors are connected to the lowest bit to the highest bit of the input number in order from small to large capacitance value. The upper plate of the capacitor with the largest capacitance value in the negative DAC is grounded, the capacitor with the smallest capacitance value is connected to VDD, and the upper plates of the remaining capacitors are connected to the lowest bit to the highest bit of the input number in order from small to large capacitance value. The lower plates of each capacitor in the positive DAC are connected to each other and serve as the output end of the encoding result of the positive input number; the lower plates of each capacitor in the negative DAC are connected to each other and serve as the output end of the encoding result of the negative input number.

[0015] The present invention also includes a charge domain signed multi-bit multiplication and accumulation operation circuit, which includes an operation array, a numerical input module, a symbol input module, a capacitor weighted network, a data output module, and peripheral circuits related to realizing the data storage function.

[0016] The operation array is composed of a sign column and multiple value columns. The sign column is composed of multiple sign bit operation units in the aforementioned charge domain signed multiplication circuit arranged in rows; the value column is composed of multiple value bit operation units in the aforementioned charge domain signed multiplication circuit arranged in rows. The sign bit operation units or value bit operation units in the same column share the bit lines BL, BLB and the calculation bit line MBL; the source of N7 and the drain of P5 in the sign bit operation unit of each row are connected to the source of N12 and P8 in the value bit operation unit of the same row.

[0017] The numerical input module is composed of several bidirectional DACs arranged in rows as in the aforementioned charge domain signed multiplication circuit. Each bidirectional DAC is electrically connected to the sign bit operation unit of the corresponding row and is used to generate an analog quantity corresponding to the numerical bit of the encoded input number.

[0018] The sign input module is electrically connected to the S_IN and S_INB ports of each sign bit operation unit in the sign column, and is used to input the sign bit of the encoded input number. The capacitor weighted network is electrically connected to the calculation bit line MBL of each calculation column in the operation array, and weights the calculation result of each column. The data output module is composed of multiple ADC circuits and is used to perform analog-to-digital conversion on the calculation result output by the capacitor weighted network.

[0019] As a further improvement of the present invention, each row in the operation array is used as a basic unit for implementing a multiplication operation between a multi-bit signed input number and a multi-bit signed weight;

[0020] The sign bit of the input number is input through the S_IN and S_INB ports; the numerical bit of the input number is input through IN+ and IN- after being encoded. The sign bit of the weight is pre-stored on the storage nodes Q1 and QB1 of the sign bit operation unit; the numerical bit of the weight is pre-stored on the storage nodes Q2 and QB2 of each numerical bit operation unit with different weights. The operation result is accumulated to the capacitor weighted network through the calculation bit line MBL of each column, and then quantized and output.

[0021] As a further improvement of the present invention, several rows in the operation array are used together as basic units for implementing MAC operations between multi-bit signed input numbers and multi-bit signed weights.

[0022] Each row of the operation array completes its own multiplication operation independently, and then accumulates the multiplication results of each row into a capacitor weighted network to implement multiplication and accumulation operations, and then quantizes and outputs the final MAC operation results.

[0023] As a further improvement of the present invention, assuming that the numerical value of the weight supported by the circuit is N bits, the capacitor weighted network is composed of N+1 capacitors; the ratio of the capacitance values ​​of each capacitor is 1:1:2…:2 N-2 :2 N-1 Among them, the upper plate of one of the capacitors with the lowest capacitance value is grounded, and the upper plates of the remaining capacitors are connected to the calculation bit lines MBL with weights from low to high in the order of capacitance value from high to low; the lower plates of each capacitor are connected to each other and serve as the output end of the weighted result.

[0024] The present invention also includes a CIM chip, which is encapsulated by the aforementioned charge domain signed multi-bit multiplication-accumulation operation circuit.

[0025] The technical solution provided by the present invention has the following beneficial effects:

[0026] The present invention utilizes the designed 12T-SRAM unit and 9T1C-SRAM unit to realize the multiplication and multiplication-accumulation operation of signed input and signed weight. This new logic circuit creatively divides the multiplication between signed numbers into two stages, firstly performing the multiplication operation of the sign bit bracket in the 12T-SRAM, and then performing the multiplication operation between the value bits in the 9T1C-SRAM.

[0027] The present invention also designs a new CIM circuit based on the SRAM circuit by using this special logic unit and circuit principle. The CIM circuit can support large-scale multiplication and multiplication-accumulation operations between signed numbers while retaining storage functions such as completed data reading and writing, thereby overcoming the defects of nonlinearity and low parallelism in various existing CIM circuits; and solving the problem that the existing circuit cannot realize Mac operations on signed numbers in hardware, and thus cannot adapt to the computing requirements of specific neural networks.

[0028] In addition, the CIM circuit provided by the present invention supports full array parallel computing, can perform up to 1024 MAC operations in one computing cycle, has extremely high throughput and energy efficiency, and the choice of charge domain also makes the calculation result have better linearity. This CIM circuit can especially meet the requirements for calculation accuracy in complex application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a circuit schematic diagram of the charge domain signed multiplication circuit provided in Example 1 of the present invention.

[0030] Figure 2 4 is a circuit diagram of a bidirectional DAC used in the charge domain signed multiplication circuit in Embodiment 1 of the present invention.

[0031] Figure 3 This is a circuit schematic diagram of a charge domain signed multi-bit multiplication-accumulation operation circuit provided in Embodiment 2 of the present invention.

[0032] Figure 4 It is a circuit diagram of a circuit for implementing 4-bit signed weighted multiplication and multiplication-accumulation operations between signed inputs provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0034] Example 1

[0035] This embodiment provides a charge domain signed multiplication circuit, which is used to perform multiplication operations between signed input numbers and signed weights, including multiplication operations between two-bit (1-bit sign bit + 1-bit value bit) input numbers and two-bit (1-bit sign bit + 1-bit value bit) weights, and multiplication operations between multi-bit (1-bit sign bit + 2 or more bits of value bits) input numbers and two-bit (1-bit sign bit + 1-bit value bit) weights.

[0036] Specifically, Figure 1 As shown, the charge domain signed multiplication circuit is composed of 8 PMOS tubes P1~P8, 13 NMOS tubes N1~N13, and a capacitor C. Among them, P1~P5 and N1~N7 constitute the sign bit operation unit, and the remaining P6~P8, N8~N13 and capacitor C constitute the value bit operation unit. The circuit connection relationship of the charge domain signed multiplication circuit is as follows:

[0037] In the sign bit operation unit (abbreviated as 12T-SRAM), P1~P2 and N1~N4 constitute a 6T-SRAM unit including storage nodes Q1 and QB1. Specifically, P1, P2, N1, and N2 constitute a mutually coupled latch, including two storage nodes Q1 and QB1; the source of N3 is connected to the storage node Q1, the drain of N3 is connected to the bit line BL, and the gates of N3 and N4 are connected to the word line WL; the source of N4 is connected to the storage node QB1, and the drain of N4 is connected to the bit line BLB. The drain of N5 and the source of P3 are connected to S_INB, and the drain of N6 and the source of P4 are connected to S_IN; the sources of N6 and N5, the drains of P3 and P4 are connected to the gates of N7 and P5; the drain of N7 is connected to IN-, and the source of P5 is connected to IN+.

[0038] In the numerical bit operation unit (9T1C-SRAM), P6~P7 and N8~N11 constitute a 6T-SRAM unit including storage nodes Q2 and QB2. Specifically, P6, P7, N8, and N9 constitute a mutually coupled latch, including two storage nodes Q2 and QB2; the source of N10 is connected to the storage node Q2, the drain of N10 is connected to the bit line BL, and the gate of N10 is connected to the word line WL; the source of N11 is connected to the storage node QB2, the drain of N11 is connected to the bit line BL, and the gate of N11 is connected to the word WL. The drains of P5 and N12 are connected to the sources of P8 and N7; the gate of N12 is connected to the storage node Q2, and the gates of P8 and N13 are connected to the storage node QB2; the sources of N12 and N13 and the drain of P8 are connected to the upper plate of the capacitor C, the calculation bit line MBL is connected to the lower plate of the capacitor, and the drain of N13 is connected to 1 / 2VDD.

[0039] When the circuit performs multiplication, the two groups of storage nodes in the sign bit operation unit and the value bit operation unit are used to pre-store the sign bit and value bit of the weight respectively. Specifically, when Q1=1, QB1=0, it means that the sign of the weight is positive; when Q1=0, QB1=1, it means that the sign of the weight is negative. When Q2=1, QB2=0, it means that the value of the weight is "1"; when Q2=0, QB2=1, it means that the value of the weight is "0". S_IN and S_INB are used to input the sign bit of the encoded input number; when S_IN=1, S_INB=0, it means that the sign of the input number is positive; when S_IN=0, S_INB=1, it means that the sign of the input number is negative. IN+ and IN- are used to input the value bits of the encoded positive input number and negative input number respectively. MBL is used to output the result of the multiplication operation.

[0040] In the charge domain signed multiplication circuit provided in this embodiment, the multiplication operation task between the signed input number and the signed weight is divided into the following two stages:

[0041] The first stage is completed in the sign bit operation unit. In this stage, the sign bit operation unit performs an XOR operation on the sign bit of the input number input through S_IN and S_INB and the sign bit of the weight pre-stored in Q1 and QB1 through the logic unit composed of N5~N7, P3~P5, and then obtains the sign bit of the final product result. Then, according to the sign of the product result, the numerical bits of the encoded positive input number and negative input number input through IN+ and IN- are selected and transmitted to the numerical bit operation unit. Specifically, in the charge domain signed multiplication circuit of this embodiment, when the signed product of the input number and the weight is positive, the sign bit operation unit selects the positive input number input through IN+; the corresponding voltage of the positive input number input through the IN+ port is greater than or equal to 1 / 2VDD. When the signed product of the input number and the weight is negative, the sign bit operation unit selects the negative input number input through IN-, and the corresponding voltage of the negative input number input through the IN- port is less than 1 / 2VDD. IN+ is a voltage greater than 1 / 2VDD, so it is transmitted using a P tube; IN- is a voltage less than 1 / 2VDD, so it is transmitted using an N tube.

[0042] The second stage is completed in the numerical bit operation unit. In this stage, the numerical bits of the weights pre-stored in Q1 and QB1 will be multiplied with the numerical bits of the input number "with the product result sign bit" transmitted from the sign bit operation unit in the calculation unit composed of P8, N12, N13 and capacitor C. The charge representing the multiplication result will be accumulated on capacitor C and output to the outside through the calculation bit line CBL. Specifically, when the bit line voltage of the calculation bit line of MBL is 1 / 2VDD, it means that the product result is 0. When the bit line voltage is between 0 and 1 / 2VDD, it means that the product result is negative. When the bit line voltage is between 1 / 2VDD and VDD, it means that the product result is positive. The numerical values ​​of positive and negative values ​​in the product result are related to the voltage of the bit line voltage.

[0043] The following is a detailed description of the operation logic of the charge domain signed multiplication circuit in two stages with specific data:

[0044] In the first stage, the combination Figure 1 From the circuit on the left, we can see that the 12T-SRAM unit implements the sign bit judgment of the product of the input and the weight and selects the positive and negative input logic according to the sign bit as follows:

[0045] (1) When Q=1, QB=0 and S_IN=1, S_INB=0, the sign bit of the weight is "+", and the sign bit of the input number is "+". At this time, the transmission gate formed by N5 and P3 is turned on, and the transmission gate formed by N6 and P4 is turned off. S_INB=0 is transmitted to the gates of N7 and P5, P5 is turned on, and the IN+ input is selected.

[0046] That is: the sign bit operation unit realizes that "the product of a positive number and a positive number is a positive number."

[0047] (2) When Q=1, QB=0 and S_IN=0, S_INB=1, the sign bit of the weight is "+" and the sign bit of the input number is "-". At this time, the transmission gate formed by N5 and P3 is turned on, and the transmission gate formed by N6 and P4 is turned off. S_INB=1 is transmitted to the gates of N7 and P5, N7 is turned on, and the IN- input is selected.

[0048] That is, the sign bit operation unit realizes that "the product of a positive number and a negative number is a negative number".

[0049] (3) When Q=0, QB=1 and S_IN=1, S_INB=0, the sign bit of the weight is "-", and the sign bit of the input number is "+". At this time, the transmission gate formed by N5 and P3 is cut off, and the transmission gate formed by N6 and P4 is turned on. S_IN=1 is transmitted to the gates of N7 and P5, N7 is turned on, and the IN- input is selected.

[0050] That is, the sign bit operation unit realizes that "the product of a negative number and a positive number is a negative number".

[0051] (4) When Q=0, QB=1 and S_IN=0, S_INB=1, the sign bit of the weight is "-", and the sign bit of the input number is "-". At this time, the transmission gate formed by N5 and P3 is cut off, and the transmission gate formed by N6 and P4 is turned on. S_IN=0 is transmitted to the gates of N7 and P5, and P5 is turned on, selecting the IN+ input.

[0052] That is, the sign bit operation unit realizes that "the product of a negative number and a negative number is a positive number".

[0053] In the second stage, combined with Figure 1 From the circuit on the right, we can see that the logic of the 9T1C-SRAM unit to implement the multiplication operation between the input number and the numerical bit of the weight is as follows:

[0054] (5) When Q=1, QB=0, the value of the weight is "1". At this time, the transmission gate formed by N12 and P8 is turned on, N13 is turned off, and the analog voltage IN representing the numerical bit of the input number input from the 12T-SRAM unit is coupled to the calculation bit line MBL, that is, IN×1 is realized.

[0055] Furthermore, if the value of the input number (i.e., IN) is between 0 and 1 / 2VDD, the final product result is a negative number of the corresponding size; if the value of the input number (i.e., IN) is between 1 / 2VDD and VDD, the final product result is a positive number of the corresponding size. If the value of the input number (i.e., IN) is 1 / 2VDD, the final product result is 0.

[0056] Take the multiplication of 2-bit signed input and 2-bit signed weight as an example: Assuming IN=0V, it means that the input number with product sign is "-1", and the bit line voltage of MBL is still 0V, that is: "-1×1=-1". Assuming IN=VDD, it means that the input number with product sign is "+1", and the bit line voltage of MBL is still VDD, that is: "+1×1=+1". Assuming IN=1 / 2VDD, it means that the input number with product sign is "0", and the bit line voltage of MBL is still 1 / 2VDD, that is: "0×1=0".

[0057] (6) When Q=0, QB=1, the value of the weight is "0". At this time, the transmission gate formed by N12 and P8 is cut off, N13 is turned on, and the analog voltage of 1 / 2VDD is coupled to the calculation bit line MBL. At this time, no matter what the value of the input number is, the calculation bit line MBL will always remain at 1 / 2VDD, that is, IN×0 is realized.

[0058] Still taking the multiplication of 2-bit signed input and 2-bit signed weight as an example: no matter IN=0V, IN=1 / 2VDD, or IN=VDD, MBL will always keep 1 / 2VDD unchanged, that is, "-1×0=0", "0×0=0", "+1×0=0".

[0059] Accordingly, combined with the above circuit principle, it can be known that when the circuit performs the multiplication operation of the input number IN and the weight 1, the voltage of the calculation bit line MBL can follow the analog value of IN. Therefore, if the voltages of different amplitudes are encoded as different numerical bits of the multi-bit input number, the above operation process still holds. That is, the charge domain signed multiplication circuit can complete the signed multiplication operation between the multi-bit (greater than 2) input number and the two-bit weight.

[0060] In order to realize encoding of the values ​​of input numbers with different multi-bits, this embodiment is as follows: Figure 1 A bidirectional DAC is further designed for the charge domain signed multiplication circuit. The bidirectional DAC can convert the digital quantity (multi-bit number) of input numbers with different signs into analog quantity (voltage) of corresponding amplitude, and input it into the charge domain signed multiplication circuit through IN+ or IN- port.

[0061] The bidirectional DAC includes a positive DAC composed of a plurality of capacitors, and a negative DAC composed of a plurality of capacitors. The positive DAC converts a positive input number into an analog voltage of a corresponding magnitude, and the negative DAC converts a negative input number into an analog voltage of a corresponding magnitude. The positive DAC and the negative DAC are both capacitor arrays, and the number and size of the capacitors in the capacitor array are related to the number of bits of the multi-bit input number. Specifically, when the numerical bit of the input number IN is M bits, the bidirectional DAC includes a positive DAC composed of M+2 capacitors, and a negative DAC composed of M+2 capacitors. The ratio of the capacitance value of each capacitor in the positive DAC and the negative DAC is 1:1:2…:2 M-1 :2 M .

[0062] Among them, the upper plate of the capacitor with the largest capacitance value in the positive DAC is connected to VDD, the upper plate of the capacitor with the smallest capacitance value is grounded, and the upper plates of the remaining capacitors are connected to the lowest bit to the highest bit of the input number in order from small to large capacitance value. The upper plate of the capacitor with the largest capacitance value in the negative DAC is grounded, the capacitor with the smallest capacitance value is connected to VDD, and the upper plates of the remaining capacitors are connected to the lowest bit to the highest bit of the input number in order from small to large capacitance value. The lower plates of each capacitor in the positive DAC are connected to each other and serve as the output end of the encoding result of the positive input number; the lower plates of each capacitor in the negative DAC are connected to each other and serve as the output end of the encoding result of the negative input number.

[0063] like Figure 2As shown in the figure, taking a bidirectional DAC using a 4-bit signed input number as an example, the numerical bit part of the 4-bit input number is 3 bits, recorded as "IN <2> IN <1> IN <0> "At this time, the bidirectional DAC used in the operation is composed of 10 capacitors, and the positive DAC and the negative DAC are each composed of 5 capacitors. The capacitance values ​​of each capacitor from left to right are also 8C, 4C, 2C, 1C, and 1C respectively. At this time, in the positive DAC, the upper plate of the 8C capacitor is connected to VDD, and the upper plates of the 4C, 2C, and 1C capacitors are connected to IN2, IN2, and IN0 respectively; the upper plate of the last IC capacitor is grounded; in addition, the lower plates of each capacitor are connected and connected to the IN+ port. In the negative DAC, the upper plate of the 8C capacitor is grounded, and the upper plates of the 4C, 2C, and 1C capacitors are connected to IN2, IN2, and IN0 respectively; the upper plate of the last IC capacitor is connected to VDD; in addition, the lower plates of each capacitor are connected and connected to the IN- port.

[0064] According to the potential of the upper and lower plates of each capacitor in the capacitor array, under the coupling effect of the capacitor array:

[0065] When the 3-bit number is: <2> IN <1> IN <0> ”, the output voltage of the positive DAC is:

[0066]

[0067] Right now:

[0068]

[0069] It can be seen that the larger the value of the 3-bit number, the larger the amplitude of the positive DAC output voltage.

[0070] When the 3-bit number is: <2> IN <1> IN <0> ", the output voltage of the negative DAC is:

[0071]

[0072] Right now:

[0073]

[0074] It can be seen that the larger the value of the 3-bit input number, the smaller the amplitude of the negative DAC output voltage.

[0075] Example 2

[0076] The scheme in Example 1 provides a charge domain signed multiplication circuit composed of 12T-SRAM and 9T1C-SRAM, which can realize multi-bit signed input number and multi-bit signed weight multiplication operation. On this basis, this embodiment replaces the traditional SRAM unit with only data storage function with the newly designed 12T-SRAM and 9T1C-SRAM unit in Example 1 based on the SRAM circuit architecture, and then designs a new circuit with a logical operation function of retaining data storage function and having multi-bit signed multiplication and multiply-accumulate (MAC) operation function.

[0077] Specifically, this embodiment further provides a charge domain signed multi-bit multiplication-accumulation operation circuit, such as Figure 3 As shown, it includes a calculation array, a numerical input module, a symbol input module, a capacitor weighted network, and a data output module. In addition, the circuit also includes various peripheral circuits related to the realization of data storage functions, including a timing control circuit, a precharge circuit, a word line driver and decoder, ..., an ADC array, and so on.

[0078] The operation array is composed of a sign column and a plurality of value columns. The sign column is formed by arranging a plurality of sign bit operation units in the charge domain signed multiplication circuit of Example 1 in rows. The value column is formed by arranging a plurality of value bit operation units in the charge domain signed multiplication circuit of Example 1 in rows. In the operation array, the sign bit operation units or value bit operation units in the same column share the bit lines BL, BLB and the calculation bit line MBL. The source of N7 and the drain of P5 in the sign bit operation unit of each row are connected to the source of N12 and P8 in the value bit operation unit of the same row. In each row of the operation array, the source of N7 and the drain of P5 in the sign bit operation unit are connected and serve as the output terminal OUT of the sign multiplication operation result. The source of N12 and P8 in the value bit operation unit is connected and serves as the input terminal IN for receiving the sign operation result. The OUT of the sign bit operation unit of each row in the operation array is connected to the IN of all the value bit operation units in the same row.

[0079] The numerical input module is composed of several bidirectional DACs arranged in rows as in the aforementioned charge domain signed multiplication circuit. Each bidirectional DAC is electrically connected to the sign bit operation unit of the corresponding row and is used to generate an analog quantity corresponding to the numerical bit of the encoded input number.

[0080] The sign input module is electrically connected to the S_IN and S_INB ports of each sign bit operation unit in the sign column, and is used to input the sign bit of the encoded input number. The encoding logic of the sign input module can be implemented using a specific logic circuit, and its main function is to set S_IN to a high level and S_INB to a low level when the sign of the input number is "+". On the contrary, if the sign of the input number is "-", S_IN is set to a low level and S_INB is set to a high level.

[0081] The capacitor weighting network is electrically connected to the calculation bit lines MBL of each calculation column in the operation array, and weights the calculation results of each column. In practical applications, the capacitor weighting network is a capacitor array composed of multiple capacitors of different sizes. The number and capacitance value of the capacitors in the capacitor array are mainly related to the number of bits of the weight in the multiplication or multiplication-accumulation operation to be completed. For example, assuming that the numerical bit of the weight supported by the circuit is N bits, the capacitor weighting network is composed of N+1 capacitors; the ratio of the capacitance values ​​of each capacitor is 1:1:2…:2 N-2 :2 N-1 Among them, the upper plate of one of the capacitors with the lowest capacitance value is grounded, and the upper plates of the remaining capacitors are connected to the calculation bit lines MBL with weights from low to high in the order of capacitance value from high to low; the lower plates of each capacitor are connected to each other and serve as the output end of the weighted result. Specifically, Figure 4 The main structure of a circuit that can realize the multiplication and accumulation operation between 4-bit signed weights and multi-bit signed input numbers, wherein the capacitor weighted network is composed of 4 capacitors, and the ratio of the capacitance values ​​of each capacitor is: 1:1:2:4, wherein the upper plate of one 1C capacitor is grounded, and the upper plates of the remaining capacitors are connected to the calculation bit lines MBL with weights from low to high in the order of capacitance values ​​from large to small. <1> 、MBL <2> and MBL <3> superior.

[0082] The data output module is composed of a plurality of ADC circuits and is used to perform analog-to-digital conversion on the operation results output by the capacitor weighted network. The data output module can be implemented by using various existing ADC circuits.

[0083] The charge domain signed multi-bit multiplication-accumulation operation circuit provided in this embodiment has data storage function and logic operation function. Among them, the 6T-SRAM part in each 12T-SRAM or 9T1C-SRAM in the operation array is used as a basic unit for performing data storage function, and the functional logic of this part is completely consistent with the classic SRAM circuit using 6T-SRAM unit, and the storage nodes Q and QB in each 6T-SRAM can be used to store and maintain data, and the word line WL and the bit lines BL and BLB can be used to realize the reading and writing of data.

[0084] The logic operation function can be divided into two main functions: multiplication operation between multi-bit signed input numbers and multi-bit signed weights, and multiplication and accumulation operation between multi-bit signed input numbers and multi-bit signed weights. Specifically, each row in the operation array is used as a basic unit to implement the multiplication operation between multi-bit signed input numbers and multi-bit signed weights. Among them, the sign bit of the input number is input through the S_IN and S_INB ports; the numerical bit of the input number is input through IN+ and IN- after encoding. The sign bit of the weight is pre-stored on the storage nodes Q1 and QB1 of the sign bit operation unit; the numerical bit of the weight is pre-stored on the storage nodes Q2 and QB2 of each numerical bit operation unit with different weights. The operation result is accumulated to the capacitor weighted network through the calculation bit line MBL of each column, and then quantized and output.

[0085] Several rows in the operation array serve as the basic unit for implementing MAC operations between multi-bit signed input numbers and multi-bit signed weights. Each row of the operation array independently completes its own multiplication operation, and then accumulates the multiplication results of each row into the capacitor weighted network to implement multiplication and accumulation operations, and then quantizes the final MAC operation results for output.

[0086] based on Figure 3 The circuit design shown in the figure, this embodiment further provides a CIM chip, which is composed of Figure 3 The CIM chip has complete data storage function and supports multiplication or multiplication-accumulation operation between signed input numbers and signed weights.

[0087] Simulation test

[0088] In order to verify the performance of the charge domain signed multiplication and multi-bit multiplication and accumulation circuit provided in this example, the technicians used Figure 3 Taking the circuit design with a computing array size of 64×64 as an example, the circuit was simulated and tested using Virtuoso simulation software. The simulation environment of the experimental process is: 28nm CMOS process, 27℃, power supply voltage 0.9V, TT process corner.

[0089] This experiment evaluates the circuit's operation performance by testing the linearity between the theoretical operation results and the actual operation results in the circuit. During the experiment, the circuit function was verified by combining three cases with different signs in the results, and the data was recorded.

[0090] (1.1) Case 1: The product of input and weight is either positive or negative. The experimental results of this case are shown in Table 1:

[0091] Table 1: Results of multiplication and accumulation when the product is both positive and negative

[0092]

[0093] Specifically, the weight stored in rows 0 to 15 is 1001, the input is 0010, the product sign is negative, and the final input of the DAC is 01011 (the final input is the signal level connected to each capacitor upper plate from high to low in the DAC, and the bit weights are 8 4 2 1 1 from high to low). At this time, the output of the DAC is:

[0094] .

[0095] The weight stored in rows 16 to 31 is 0101, the input is 0101, the product sign is positive, the final input of the DAC is 11010, and the output of the DAC is:

[0096] .

[0097] The weight stored in rows 32 to 47 is 0011, the input is 1110, the product sign is negative, the final input of the DAC is 00011, and the output of the DAC is:

[0098] .

[0099] The weight stored in lines 48 to 63 is 1111, the input is 1011, the product sign is positive, the final input of the DAC is 10110, and the output of the DAC is:

[0100] .

[0101] After being processed by the capacitor weighted network, the ideal output voltage of the multiplication and accumulation result is:

[0102]

[0103] The actual output voltage is 495.6mV.

[0104] (1.2) Case 2: The product of the input and the weight is all positive. The experimental results of this case are shown in Table 2:

[0105] Table 2: Results of multiplication and accumulation operations when the product is only positive

[0106]

[0107] Combined with the data in Table 2, it can be seen that in the second case, the ideal output voltage of the multiplication and accumulation result is 566mV, while the actual output voltage is 566.6mV.

[0108] (1.3) Case 3: The product of input and weight is all negative. The experimental results of this case are shown in Table 3:

[0109] Table 3: Results of multiplication and accumulation operations when the product is only negative

[0110]

[0111] Combined with the data in Table 3, it can be seen that in the second case, the ideal output voltage of the multiplication and accumulation result is 334mV, while the actual output voltage is 336.9mV.

[0112] In the above three cases, the deviation between the actual output and the theoretical output is less than 0.87% at the highest and only 0.02% at the lowest. Therefore, the simulation results of the experiment show that the linearity of the calculation result of the multiplication and accumulation operation of the circuit designed by the present invention is very good. The calculation accuracy of the circuit.

[0113] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A charge domain signed multiplication circuit for performing a multiplication operation between a signed input number and a signed weight, characterized in that: It consists of 8 PMOS transistors P1~P8, 13 NMOS transistors N1~N13, and a capacitor C; among them, P1~P5 and N1~N7 constitute the sign bit operation unit, and the remaining components constitute the value bit operation unit; the circuit connection relationship is: P1~P2 and N1~N4 constitute a 6T-SRAM unit including storage nodes Q1 and QB1 in the sign bit operation unit; the drain of N5 and the source of P3 are connected to S_INB, the drain of N6 and the source of P4 are connected to S_IN; the sources of N6 and N5, the drains of P3 and P4 are connected to the gates of N7 and P5; the drain of N7 is connected to IN-, and the source of P5 is connected to IN+; P6~P7 and N8~N11 constitute a 6T-SRAM unit including storage nodes Q2 and QB2 in the numerical bit operation unit; the drains of P5 and N12 are connected to the sources of P8 and N7; the gate of N12 is connected to the storage node Q2, and the gates of P8 and N13 are connected to the storage node QB2; the sources of N12 and N13 and the drain of P8 are connected to the upper plate of the capacitor C, the calculation bit line MBL is connected to the lower plate of the capacitor, and the drain of N13 is connected to 1 / 2VDD; Among them, the two groups of storage nodes in the sign bit operation unit and the value bit operation unit are respectively used to pre-store the sign bit and value bit of the weight; S_IN and S_INB are used to input the sign bit of the encoded input number; IN+ and IN- are respectively used to input the value bits of the encoded positive input number and negative input number; MBL is used to output the result of the multiplication operation.

2. The charge domain signed multiplication circuit according to claim 1, characterized in that: When S_IN=1, S_INB=0, it means the sign of the input number is positive; when S_IN=0, S_INB=1, it means the sign of the input number is negative; when Q1=1, QB1=0, it means the sign of the weight is positive; when Q1=0, QB1=1, it means the sign of the weight is negative; When Q2=1, QB2=0, it means the value of the weight is "1"; when Q2=0, QB2=1, it means the value of the weight is "0".

3. The charge domain signed multiplication circuit according to claim 1, wherein: When the signed product of the input number and the weight is positive, the sign bit operation unit selects the positive input number of IN+ input; when the signed product of the input number and the weight is negative, the sign bit operation unit selects the negative input number of IN- input.

4. The charge domain signed multiplication circuit according to claim 3, characterized in that: When the bit line voltage of the calculated bit line of MBL is 1 / 2VDD, it indicates that the product result is 0; when the bit line voltage is 0-1 / 2VDD, it indicates that the product result is a negative value; when the bit line voltage is 1 / 2VDD-VDD, it indicates that the product result is a positive value.

5. The charge domain signed multiplication circuit according to claim 4, characterized in that: The numerical bits IN+ and IN- of the input number are encoded by a bidirectional DAC; when the numerical bits of the input number IN are M bits, the bidirectional DAC includes a positive DAC composed of M+2 capacitors and a negative DAC composed of M+2 capacitors; wherein the ratio of the capacitance values ​​of the capacitors in the positive DAC and the negative DAC is 1:1:2…:2 M-1 :2 M ; Among them, the upper plate of the capacitor with the largest capacitance value in the positive DAC is connected to VDD, the upper plate of the capacitor with the smallest capacitance value is grounded, and the upper plates of the remaining capacitors are connected to the lowest bit to the highest bit of the input number in order from small to large capacitance values; the upper plate of the capacitor with the largest capacitance value in the negative DAC is grounded, the capacitor with the smallest capacitance value is connected to VDD, and the upper plates of the remaining capacitors are connected to the lowest bit to the highest bit of the input number in order from small to large capacitance values; the lower plates of each capacitor in the positive DAC are connected to each other and serve as the output end of the encoding result of the positive input number; the lower plates of each capacitor in the negative DAC are connected to each other and serve as the output end of the encoding result of the negative input number.

6. A charge domain signed multi-bit multiplication-accumulation circuit, characterized in that: It includes: An operation array, which is composed of a sign column and a plurality of value columns; the sign column is formed by arranging a plurality of sign bit operation units in the charge domain signed multiplication circuit as claimed in any one of claims 1 to 5 in rows; the value column is formed by arranging a plurality of value bit operation units in the charge domain signed multiplication circuit as claimed in any one of claims 1 to 5 in rows; the sign bit operation units or value bit operation units in the same column share the bit lines BL, BLB and the calculation bit line MBL; the source of N7 and the drain of P5 in the sign bit operation unit of each row are connected to the source of N12 and P8 in the value bit operation unit of the same row; A numerical input module, which is composed of a plurality of bidirectional DACs in the charge domain signed multiplication circuit as claimed in claim 5 arranged in rows, each bidirectional DAC being electrically connected to a sign bit operation unit of a corresponding row and used to generate an analog value corresponding to a numerical bit of an encoded input number; A sign input module, which is electrically connected to the S_IN and S_INB ports of each sign bit operation unit in the sign column and is used to input the sign bit of the encoded input number; A capacitance weighting network, which is electrically connected to the calculation bit lines MBL of each calculation column in the operation array and weights the calculation result of each column; A data output module, which is composed of a plurality of ADC circuits and is used to perform analog-to-digital conversion on the operation result output by the capacitor weighted network; And peripheral circuits related to realizing data storage functions.

7. The charge domain signed multi-bit multiplication-accumulation circuit according to claim 6, characterized in that: Each row in the operation array is used as a basic unit for implementing a multiplication operation between a multi-bit signed input number and a multi-bit signed weight; Among them, the sign bit of the input number is input through the S_IN and S_INB ports; the numerical bit of the input number is input through IN+ and IN- after being encoded; the sign bit of the weight is pre-stored on the storage nodes Q1 and QB1 of the sign bit operation unit; the numerical bit of the weight is pre-stored on the storage nodes Q2 and QB2 of each numerical bit operation unit with different weights; the operation result is accumulated to the capacitor weighted network through the calculation bit line MBL of each column, and then quantized and output.

8. The charge domain signed multi-bit multiplication-accumulation circuit according to claim 7, characterized in that: Several rows in the operation array together serve as a basic unit for implementing a MAC operation between a multi-bit signed input number and a multi-bit signed weight; Each row of the operation array completes its own multiplication operation independently, and then accumulates the multiplication results of each row into a capacitor weighted network to implement multiplication and accumulation operations, and then quantizes and outputs the final MAC operation results.

9. The charge domain signed multi-bit multiplication-accumulation operation circuit according to claim 7, characterized in that: The numerical value of the weight supported by the circuit is N bits, and the capacitor weighted network is composed of N+1 capacitors; the ratio of the capacitance values ​​of each capacitor is 1:1:2…:2 N-2 :2 N-1 ; Among them, the upper plate of one of the capacitors with the lowest capacitance value is grounded, and the upper plates of the remaining capacitors are connected to the calculation bit lines MBL with weights from low to high in order of capacitance value from high to low; the lower plates of each capacitor are connected to each other and serve as the output end of the weighted result.

10. A CIM chip, characterized in that: It is encapsulated by the charge domain signed multi-bit multiplication-accumulation operation circuit as described in any one of claims 6 to 9.

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