Acceleration unit, computing device, system on chip and data transmission acceleration method

Abstract

The embodiment of the invention provides an acceleration unit, a computing device, a system on chip and a data transmission acceleration method, and the acceleration unit comprises a receiving subunit which is used for receiving a network message through a network; the message writing subunit is used for writing the network message into a target memory buffer area through a target transmission channel, the target transmission channel is determined from at least two transmission channels, and the target memory buffer area is determined from a plurality of memory buffer areas distributed by a host; the queue writing subunit is used for at least writing address information of a target memory buffer area into a target entry in a completion queue through a target transmission channel after the network message is written into the target memory buffer area, and enabling the state updating information to indicate that the target entry is updated; and the message receiving end on the host reads the network messages from the plurality of memory buffer areas according to the completion queue and the state updating information and the sequence of receiving the network messages by the receiving subunits. According to the scheme, the efficiency of writing the network message into the memory can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to an acceleration unit, a computing device, a system on chip, and a data transmission acceleration method. Background Art

[0002] In the cloud computing scenario, the network needs to be virtualized. The host builds multiple virtual machines (VMs). After receiving the network message, the infrastructure processor (IPU) writes the network message into the memory buffer allocated by the virtual machine. Then the virtual machine can read the network message from the memory buffer and perform corresponding processing.

[0003] Currently, when an infrastructure processor writes network packets to a memory buffer, a packet group is written to the memory buffer via a high-speed serial bus (peripheral component interconnect express, PCIe) link.

[0004] However, when a message group includes a large number of network messages, it takes a long time to write the network messages into the memory buffer through a PCIe link, so the efficiency of writing the network messages into the memory buffer is low. Summary of the invention

[0005] In view of this, embodiments of the present application provide an acceleration unit, a computing device, a system on chip, and a data transmission acceleration method to at least solve or alleviate the above-mentioned problems.

[0006] According to the first aspect of an embodiment of the present application, an acceleration unit is provided, comprising: a receiving subunit, for receiving a network message through a network; a message writing subunit, for writing the network message into a target memory buffer through a target transmission channel, wherein the target transmission channel is determined from at least two transmission channels, and the target memory buffer is determined from a plurality of memory buffers allocated by a host; a queue writing subunit, for writing at least the address information of the target memory buffer into a target entry in a completion queue through the target transmission channel after the network message is written into the target memory buffer, and making status update information indicate that the target entry has been updated, so that a message receiving end on the host reads the network message from the plurality of memory buffers according to the completion queue and the status update information, in the order in which the network message is received by the receiving subunit.

[0007] According to a second aspect of an embodiment of the present application, a host is provided, comprising: an allocation subunit, for allocating multiple memory buffers, wherein the memory buffers are used to cache network messages sent by an acceleration unit through at least two transmission channels; a reading subunit, for reading address information cached in a completion queue according to status update information, and reading network messages from the multiple memory buffers according to the address information and in the order in which the acceleration unit receives the network messages, and updating the status update information of the corresponding entry in the completion queue to not being updated after reading the network message.

[0008] According to a third aspect of an embodiment of the present application, a computing device is provided, comprising: a processing unit for constructing a host, the host being used to allocate multiple memory buffers; and an acceleration unit according to the first aspect above.

[0009] According to a fourth aspect of an embodiment of the present application, a system on chip is provided, comprising an acceleration unit according to the first aspect above.

[0010] According to a fifth aspect of an embodiment of the present application, there is provided a server deployed in a data center and provided with an acceleration unit as described in the first aspect above.

[0011] According to a sixth aspect of an embodiment of the present application, a data center is provided, comprising a server according to the fifth aspect above.

[0012] According to the seventh aspect of the embodiment of the present application, there is provided an Internet network, comprising: a message receiving device and at least one message sending device; the message receiving device comprises an acceleration unit as described in the first aspect above; the message sending device is connected to the acceleration unit included in the message receiving device through a network, and the message sending device is used to send a message sent to a message receiving end on the message receiving device to the acceleration unit.

[0013] According to an eighth aspect of an embodiment of the present application, a data transmission acceleration method is provided, including: an allocation subunit, used to allocate multiple memory buffers, and the memory buffers are used to cache network packets sent by the acceleration unit through at least two transmission channels; a reading subunit, used to read network packets from the multiple memory buffers according to status update information and a completion queue, in the order in which the acceleration unit receives the network packets, wherein the status update information is used to indicate an updated entry in the completion queue, and the memory buffer corresponding to the address information cached in the updated entry has been written to the network packet.

[0014] According to the scheme provided by the embodiment of the present application, after the receiving subunit receives the network message, the message writing subunit can select the target transmission channel from at least two channels to write the network message into the target memory buffer, and the queue writing subunit can write at least the address information of the memory buffer into the completion queue through the target transmission channel after the network message is written, and make the status update information indicate that the target entry has been updated, and then the network message receiving end on the host can read the network message from the memory buffer in the order of receiving the network message according to the completion queue and the status update information, thereby realizing the transmission of the network message. Since the target transmission channel is selected from at least two transmission channels, different network messages can be transmitted through different transmission channels. Compared with transmitting the network message through a single channel, the time consumed by transmitting the same number of network messages through multiple channels is shorter, thereby improving the transmission efficiency of the network message, and since the status update information is provided, the network message receiving end can read the network message in the order in which the receiving subunit receives the network message, realizing the multi-channel transmission of the network message while maintaining the order of the network message, avoiding the disorder caused by the multi-channel transmission of the network message, thereby improving the efficiency of writing the network message into the memory buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0016] Figure 1 is a schematic diagram of a data center according to an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of a server according to an embodiment of the present application;

[0018] Figure 3 is a schematic diagram of an Internet network according to an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of an acceleration unit according to an embodiment of the present application;

[0020] Figure 5 It is a schematic diagram of using multiple channels to write network messages in the related art;

[0021] Figure 6 It is a schematic diagram of using multiple channels to write network messages in one embodiment of the present application;

[0022] Figure 7is a schematic diagram of transmitting network messages and address information through different transmission channels according to an embodiment of the present application;

[0023] Figure 8 is a schematic diagram of an acceleration unit according to another embodiment of the present application;

[0024] Fig. 9 is a schematic diagram of an acceleration unit according to another embodiment of the present application;

[0025] Fig.10 It is a schematic diagram of using multiple channels to write network messages in another embodiment of the present application;

[0026] Fig.11 is a schematic diagram of a write completion queue according to an embodiment of the present application;

[0027] Fig.12 is a schematic diagram of a host provided by an embodiment of the present application;

[0028] Fig.13 It is a flow chart of a method for accelerating message transmission according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0030] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0031] Infrastructure Processor: Infrastructure Processing Units (IPU) is a special processor designed for cloud data centers. It connects to physical computing, storage, and network resources, quickly cloudifies and performs hardware acceleration, and connects to the cloud operating system to manage and control the servers in the cloud data center. The infrastructure processor can solve the problem of data migration bandwidth and can also cloudify and virtualize the data center.

[0032] Host: A host is a cloud server, physical server, or virtual host that has a virtualized environment deployed. A host can create multiple virtual machines and provide software and hardware support for the operation of virtual machines. A host can also include a bare metal server, which is a hardware device with the characteristics of a traditional physical server and the virtualization function of cloud computing technology. It is a combination of hardware and software advantages.

[0033] Virtual Machine: A virtual machine (VM) is a complete computer system that is simulated by software and has complete hardware system functions and runs in an isolated environment.

[0034] Message receiving end: The message receiving end is the main body on the host that receives and processes network messages. The message receiving end can be a virtual machine or a bare metal server. After the network message is stored in the memory buffer, the virtual network card can notify the message receiving end that the network message has been written to the memory buffer by writing to the completion queue (CQ). Then, the message receiving end can read the network message from the memory buffer.

[0035] Memory buffer: A memory buffer is a storage space of a specified size reserved in the memory for temporary storage of input / output (I / O) data. The memory buffer in the embodiment of the present application refers to a storage space reserved in the memory for storing network messages.

[0036] System on chip: System on a chip (SoC) refers to a technology that integrates a complete system on a single chip and groups all or part of the necessary electronic circuits. The so-called complete system generally includes a processor (CPU) or an acceleration unit, memory, and peripheral circuits. SoC is developed in parallel with other technologies, such as Silicon on Insulator (SOI), which can provide enhanced clock frequencies and thus reduce the power consumption of microchips.

[0037] Data Center

[0038] Data centers are a globally collaborative network of specific devices used to transmit, accelerate, display, calculate, and store data information on the Internet network infrastructure. In the future, data centers will also become competitive assets for enterprises. With the widespread application of data centers, virtualization technology is increasingly being applied to data centers. As an important support for virtualization technology, infrastructure processors have been widely used in input / output virtualization scenarios in data centers.

[0039] In traditional large data centers, the network structure is usually as follows Figure 1As shown in the figure, it is the hierarchical inter-networking model. This model includes the following parts:

[0040] Server 140 : Each server 140 is a processing and storage entity of the data center. The processing and storage of a large amount of data in the data center are completed by these servers 140 .

[0041] Access switch 130: Access switch 130 is used to connect servers 140 to the switch in the data center. One access switch 130 connects to multiple servers 140. Access switches 130 are usually located at the top of the rack, so they are also called top of rack switches, and they are physically connected to the servers.

[0042] Aggregation switch 120: Each aggregation switch 120 connects to multiple access switches 130 and provides other services, such as firewall, intrusion detection, network analysis, etc.

[0043] Core switch 110: The core switch 110 provides high-speed forwarding for packets entering and leaving the data center, and provides connectivity for the aggregation switch 120. The network of the entire data center is divided into an L3 layer routing network and an L2 layer routing network. The core switch 110 usually provides a flexible L3 layer routing network for the network of the entire data center.

[0044] Generally, the aggregation switch 120 is the demarcation point between the L2 and L3 layer routing networks. The network below the aggregation switch 120 is the L2 network, and the network above is the L3 network. Each group of aggregation switches manages a delivery point (POD), and the POD is an independent VLAN network. The server does not need to modify the IP address and default gateway when migrating within the POD, because one POD corresponds to one L2 broadcast domain.

[0045] The spanning tree protocol (Spanning Tree Protocol, STP) is usually used between the aggregation switch 120 and the access switch 130. STP makes only one aggregation switch 120 available for a VLAN network, and other aggregation switches 120 are used only when a failure occurs. In other words, horizontal expansion cannot be achieved at the level of the aggregation switch 120, because even if multiple aggregation switches 120 are added, only one is still working.

[0046] The embodiments of the present application can be applied to input / output virtualization scenarios. A virtualization environment can be deployed on the server 140, and multiple virtual machines and / or bare metal servers can be created based on the virtualization environment. Network packets can be sent through the network between virtual machines, between virtual machines and bare metal servers, between bare metal servers, between virtual machines and clients, or between bare metal servers and clients.

[0047] server

[0048] The computing device in the embodiment of the present application may be a server 140 included in a data center. The server 140 is a real processing device in the data center. Figure 2 The structure block diagram of the inside of a server 140 is shown. The server 140 includes a memory 210, a processing unit cluster 270 and an acceleration unit cluster 280 connected by a bus. The processing unit cluster 270 includes a plurality of processing units 220. The acceleration unit cluster 280 includes a plurality of acceleration units 230. The acceleration unit 230 in the embodiment of the present application is mainly a special processor designed to accelerate the writing of network packets into the memory, which can be embodied as a graphics processing unit (GPU) specially designed for input / output virtualization, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a cloud infrastructure processor (Cloud Infrastructure Processing Units, CIPU), an infrastructure processor (IPU) or a data processing unit (DPU), etc.

[0049] The architecture design of the traditional processing unit makes the control unit and the storage unit occupy a large part of the space in the architecture, while the space occupied by the computing unit is insufficient. Therefore, it is very effective in terms of logic control, but not efficient enough in terms of large-scale parallel computing. Therefore, various special acceleration units have been developed to more effectively improve the processing speed of calculations for different functions and different fields. In the embodiment of the present application, the acceleration unit 230 is a hardware accelerator specially designed for accelerating the input / output speed of the message receiving end. After receiving the network message, the acceleration unit 230 can determine the target transmission channel from multiple transmission channels, write the network message to the memory buffer allocated by the host through the target transmission channel, and at least write the address information of the memory buffer cached with the network message through the target transmission channel to the completion queue, and update the status update information of the corresponding entry in the completion queue to updated, so that the message receiving end can read the network message in the memory buffer in order according to the status update information, and different network messages can be transmitted through different channels, thereby writing the network message to the memory buffer through multiple channels, improving the efficiency of writing the network message to the memory buffer, which will be described in detail below.

[0050] The processing unit 220 is used to construct a host, and the host may include multiple message receiving ends, and the message receiving ends perform input / output through the acceleration unit 230. For example, the message receiving end receives network messages through the acceleration unit 230. The host can be constructed based on one or more processing units 220, and the message receiving end may include multiple virtual machines. Multiple virtual machines can be created based on one processing unit 220. Multiple virtual machines created in the same host can perform input / output through one or more acceleration units 230. Multiple virtual machines that perform input / output through one acceleration unit 230 can be created based on the same processing unit 220 or based on different processing units 220. In an embodiment of the present application, the host constructed by the processing unit 220 can allocate a memory buffer. After the acceleration unit 230 writes the network message into the memory buffer, the message receiving end on the host can read the network message from the memory buffer.

[0051] The embodiment of the present application mainly focuses on the structure and configuration of the acceleration unit 230 , and the structure and configuration of the acceleration unit 230 will be described in detail hereinafter.

[0052] Internet

[0053] Figure 3 is a schematic diagram of an Internet network according to an embodiment of the present application, such as Figure 3 As shown, the internetwork includes a message receiving device 301 and at least one message sending device 302 ( Figure 3 Two message sending devices 302 are shown, but those skilled in the art should understand that the Internet may also include other numbers of message sending devices 302). The message receiving device 301 includes an acceleration unit 230, and the message sending device 302 is connected to the acceleration unit 230 included in the message receiving device 301 through a network. The message sending device 302 can send the message sent to the message receiving end on the message receiving device 301 to the acceleration unit 230.

[0054] A virtualization environment is deployed on the message receiving device 301, and multiple virtual machines and / or bare metal servers are created based on the virtualization environment. The message sending device 302 can send messages to the virtual machines and / or bare metal servers on the message receiving device 301 through the network. The message sending device 302 sends the message to be sent to the virtual machine and / or bare metal server to the acceleration unit 230 through the network, and the acceleration unit 230 sends the received message to the corresponding virtual machine and / or bare metal server.

[0055] After receiving the message, the acceleration unit 230 writes the received message into the memory buffer on the message receiving device 301 through a transmission channel (such as a PCIe channel). In the related art, the acceleration unit 230 writes data to the memory buffer through a fixed transmission channel. When the number of messages is large, the acceleration unit 230 needs to perform the write operation on each message in turn, which takes a long time and results in low efficiency of the acceleration unit 230 in transmitting messages.

[0056] In an embodiment of the present application, after receiving the message, the acceleration unit 230 determines the target transmission channel from multiple transmission channels, writes the message into the memory buffer through the target transmission channel, and then writes the address information of the memory buffer into the completion queue, and updates the status update information, so that the status update information can indicate the updated entries in the completion queue, and then the message receiving end can read the message from the memory buffer according to the completion queue in the order in which the message is received. Therefore, under the premise of ensuring the correct reading of the message, a relatively idle transmission channel can be selected to write the message into the memory buffer, thereby reducing the waiting time in the process of writing the message into the memory buffer, thereby improving the efficiency of the acceleration unit 230 in transmitting the message.

[0057] The embodiment of the present application mainly focuses on the structure and configuration of the acceleration unit 230 , and the structure and configuration of the acceleration unit 230 will be described in detail hereinafter.

[0058] Internal structure of the acceleration unit

[0059] Combine the following Figure 4 The internal structure diagram of the acceleration unit 230 shown in FIG. 2 specifically illustrates how the acceleration unit 230 works.

[0060] like Figure 4 As shown, the acceleration unit 230 includes a receiving subunit 231, a message writing subunit 232, and a queue writing subunit 233. The receiving subunit 231 can receive a network message through a network, and the message writing subunit 232 can write the network message into a target memory buffer through a target transmission channel, wherein the target transmission channel is determined from at least two transmission channels, and the target memory buffer is determined from a plurality of memory buffers allocated by the host. After the network message is written into the target memory buffer, the queue writing subunit 233 can write at least the address information of the target memory buffer into the target entry in the completion queue through the target transmission channel, and make the status update information indicate that the target entry has been updated, so that the message receiving end on the host reads the network message from the plurality of memory buffers according to the completion queue and the status update information, in the order in which the receiving subunit receives the network message.

[0061] One or more message receiving terminals are running on the host. After receiving a network message sent to a message receiving terminal, the acceleration unit 230 needs to write the network message into the memory buffer on the host, and then the corresponding message receiving terminal can read the network message from the memory buffer and perform corresponding processing according to the read network message. The host pre-allocates multiple memory buffers for caching network messages, and the memory buffers are located in the main memory (also called memory, internal memory) of the host.

[0062] The message receiving end running on the host can be connected to multiple virtual network cards, which are virtualized by the acceleration unit 230. Before receiving packets in the virtual network, the network card driver of the message receiving end can allocate one or more queues for receiving packets to the virtual network card, and each queue includes multiple memory buffers. When the virtual network card receives a network message, it can write the received network message into the queue allocated to it, and then the message receiving end to which the virtual network card belongs can read the network message from the queue.

[0063] After the network card driver on the host allocates a memory buffer for the message receiving end, the host will store the address of the memory buffer in the submission queue (SQ). The submission queue includes multiple data, each of which includes the address of a memory buffer, and the position of each data in the submission queue indicates the writing order of the corresponding memory buffer. After receiving the network message, the acceleration unit 230 will determine the writing order of each memory buffer according to the submission queue and write the network message into multiple memory buffers.

[0064] After receiving the network message, the message writing subunit 232 writes the network message into the target memory buffer through the target transmission channel. The target transmission channel is determined from at least two transmission channels. The transmission channel in the embodiment of the present application can be a PCIe channel, thereby realizing fast data transmission. After the network message is written into the target memory buffer, the queue writing subunit 233 can write at least the address of the memory buffer into which the network message is written into the completion queue (Completion Queue, CQ) through the target transmission channel. After the network message is written into the memory buffer, the message receiving end can find the memory buffer that caches the network message according to the address recorded in the completion queue, and read the network message from the memory buffer.

[0065] Figure 5 FIG. 1 shows a schematic diagram of using multiple channels to write network messages in the related art. Figure 5As shown, after the host allocates the memory buffer, the address of the memory buffer is stored in the submission queue (SQ). The submission queue records the addresses of memory buffers S0 to S4. It can be seen from the submission queue that when writing network messages to the memory buffer, the memory buffer is written in the order from S0 to S4. The address of S0 is Desc0, the address of S1 is Desc1, the address of S2 is Desc2, the address of S3 is Desc3, and the address of S4 is Desc4. The acceleration unit 230 receives network message 0, network message 1, network message 2, and network message 3 in sequence. Network message 0 and network message 3 are written into the memory buffer through the transmission channel L1, and network message 1 and network message 2 are written into the memory buffer through the transmission channel L2.

[0066] In the related technology, if multi-channel transmission of network messages is adopted, it may happen that network message 3 has been written into memory buffer S3 through transmission channel L1, while network message 2 transmitted through transmission channel L2 is still in transmission and network message 2 has not yet been written into memory buffer S2. At this time, since network message 3 has been written into memory buffer S3, the entry corresponding to memory buffer S3 in the completion queue is updated to address Desc3 of memory buffer S3. The message receiving end believes that all entries above the entry at address Desc3 in the completion queue have been updated. At this time, the first 4 entries in the completion queue will be read. Since network message 2 is still in transmission and has not been written into the memory buffer, the message receiving end will read wrong data from memory buffer S2.

[0067] In the scheme of the embodiment of the present application, after the message writing subunit 232 writes the network message into the memory buffer, the queue writing subunit 233 writes the address information of the memory buffer into the corresponding entry in the completion queue, and updates the status update information, so that the status update information indicates that the entry has been updated, and indicates that the entry that has not written the address information of the memory buffer has not been updated. When the message receiving end reads the address information in the completion queue, it will determine whether each entry in the completion queue has been updated according to the status update information. The message receiving end reads the cached data in the updated entry according to the reading order of the completion queue. When reading the non-updated entry, it will suspend the reading of the completion queue until the non-updated entry is updated, and then continue to read the completion queue from the entry. Therefore, when the subsequent entry in the completion queue has been updated and the preceding entry has not been updated, the message receiving end will not read the subsequent entry, ensuring that the order in which the message receiving end reads the network message from the memory buffer is the same as the order in which the receiving subunit 231 receives the network message.

[0068] Figure 6FIG. 1 is a schematic diagram of an embodiment of the present application for writing network messages using multiple channels. Figure 6 As shown, after the host allocates the memory buffer, the address of the memory buffer is stored in the submission queue (SQ). The submission queue records the addresses of memory buffers S0 to S4. It can be seen from the submission queue that when writing network messages to the memory buffer, the memory buffer is written in the order from S0 to S4. The address of S0 is Desc0, the address of S1 is Desc1, the address of S2 is Desc2, the address of S3 is Desc3, and the address of S4 is Desc4. The acceleration unit 230 receives network message 0, network message 1, network message 2, and network message 3 in sequence. Network message 0 and network message 3 are written into the memory buffer through the transmission channel L1, and network message 1 and network message 2 are written into the memory buffer through the transmission channel L2.

[0069] After network message 3 is written into memory buffer S3 through transmission channel L1, network message 2 transmitted through transmission channel L2 is still being transmitted, and network message 2 has not yet been written into memory buffer S2. The entries for writing address information Desc0, Desc1, and Desc3 in the completion queue have been updated, while the entry for writing address information Desc2 has not yet been updated. When the message receiving end reads the completion queue, it reads the entries in the completion queue from top to bottom in the order shown in the figure. Since the entry for writing address information Desc2 has not yet been updated, the message receiving end will only read the first and second entries in the completion queue in sequence, and will not read the fourth entry. After reading address information Desc0 from the first entry in the completion queue, network message 0 is read from memory buffer S0 according to address information Desc0. After reading address information Desc1 from the second entry in the completion queue, network message 1 is read from memory buffer S1 according to address information Desc1.

[0070] After the message receiving end waits for the entry in the completion queue for writing the address information Desc2 to be updated, it continues to read the completion queue from the third entry until the next unupdated entry is read or the completion queue is read. In this way, network messages can be transmitted through multiple transmission channels and the network messages can be read from the memory buffer in order.

[0071] It should be noted that writing the network message into the target memory buffer and writing the address information of the target memory buffer into the completion queue need to be performed through the same transmission channel to avoid the problem of disorder of the memory buffer and the completion queue.

[0072] Figure 7Figure 1 shows a schematic diagram of transmitting network messages and address information through different transmission channels. Figure 7 As shown, the network message 0 is written into the memory buffer S0 through the transmission channel L1, and the address information Desc0 of the memory buffer S0 is written into the completion queue through the transmission channel L2. If the queue writing subunit 233 first writes the address information Desc0 into the completion queue through the transmission channel L2, and then the message writing subunit 232 writes the network message 0 into the memory buffer S0 through the transmission channel L1, a disorder problem will occur. Since the entry for writing the address information Desc0 in the completion queue has been updated, the message receiving end will read the memory buffer S0 according to the address information Desc0, but the network message 0 has not yet been written into the memory buffer S0, which will cause the message receiving end to read erroneous data.

[0073] In an embodiment of the present application, after the receiving sub-unit 231 receives the network message, the message writing sub-unit 232 can select a target transmission channel from at least two channels to write the network message into the target memory buffer. After the network message is written, the queue writing sub-unit 233 can write at least the address information of the memory buffer into the completion queue through the target transmission channel, and make the status update information indicate that the target entry has been updated. Then, the network message receiving end on the host can read the network message from the memory buffer in the order in which the network message is received according to the completion queue and the status update information, thereby realizing the transmission of the network message. Since the target transmission channel is selected from at least two transmission channels, different network messages can be transmitted through different transmission channels. Compared with transmitting network messages through a single channel, the time consumed to transmit the same number of network messages through multiple channels is shorter, thereby improving the transmission efficiency of network messages. Moreover, since status update information is provided, the network message receiving end can read the network messages in the order in which the receiving subunit 231 receives the network messages, thereby realizing multi-channel transmission of network messages while maintaining the order of network messages, avoiding the disorder caused by multi-channel transmission of network messages, thereby improving the efficiency of writing network messages into the memory buffer.

[0074] Figure 8 is a schematic diagram of an acceleration unit provided in another embodiment of the present application, such as Figure 8 As shown, the acceleration unit 230 also includes a first load balancing subunit 234, which can obtain transmission data volume information, the transmission data volume information is used to indicate the amount of data to be transmitted in the transmission channel, and determine the target transmission channel from at least two transmission channels based on the transmission data volume information.

[0075] Before the message writing subunit 232 writes the network message into the target memory buffer, the first load balancing subunit 234 can obtain the amount of data to be transmitted, and determine the target transmission channel for transmitting the network message according to the amount of data to be transmitted of each transmission channel indicated by the amount of data to be transmitted information. In one example, the transmission channel with the smallest amount of data to be transmitted can be determined as the target transmission channel.

[0076] In an embodiment of the present application, the acceleration unit 230 also includes a first load balancing sub-unit 234, which can determine the target transmission channel for transmitting the network message from at least two transmission channels based on the amount of data to be transmitted in each transmission channel, thereby writing the network message to the target memory buffer through the transmission channel with faster transmission speed, thereby improving the efficiency of writing the network message into the memory buffer.

[0077] Fig. 9 is a schematic diagram of an acceleration unit provided by another embodiment of the present application, such as Fig. 9 As shown, the acceleration unit 230 also includes a second load balancing sub-unit 235, which can obtain transmission time consumption information, where the transmission time consumption information is used to indicate the time taken for the transmission channel to complete the transmission of the data to be transmitted, and determine the target transmission channel from at least two transmission channels based on the transmission time consumption information.

[0078] Before the message writing subunit 232 writes the network message into the target memory buffer, the second load balancing subunit 235 can obtain the transmission time information, which includes the estimated time taken by each transmission channel to complete the transmission of its own amount of data to be transmitted. Since the transmission protocols and transmission rates of each transmission channel can be different, the time taken by the transmission channel with a larger amount of data to be transmitted to complete the transmission of data can be less than the time taken by the transmission channel with a smaller amount of data to be transmitted to complete the transmission of data. Therefore, the second load balancing subunit 235 obtains the transmission time information and determines the target transmission channel according to the transmission time information. In one example, the second load balancing subunit 235 can determine the transmission channel that takes the least time to complete the transmission of the data to be transmitted as the target transmission channel.

[0079] In an embodiment of the present application, the acceleration unit 230 also includes a second load balancing sub-unit 235, which can determine the target transmission channel for transmitting the network message from at least two transmission channels based on the transmission time information of each transmission channel, thereby writing the network message to the target memory buffer through the transmission channel with faster transmission speed, thereby improving the efficiency of writing the network message into the memory buffer.

[0080] Fig.10 is a schematic diagram of another embodiment of the present application using multiple channels to write network messages, such as Fig.10As shown, after the acceleration unit 230 receives network message 0, network message 1 and network message 2, the first load balancing subunit 234 or the second load balancing subunit 235 determines the transmission channel for transmitting network message 0, network message 1 and network message 2 respectively. Figure 8 As shown, the first load balancing subunit 234 or the second load balancing subunit 235 determines that network message 0 and network message 2 are transmitted through transmission channel L1, and network message 1 is transmitted through transmission channel L2. Transmission channel L1 sequentially transmits network message 0, address information Desc0 written into memory buffer S0 of network message 0, network message 2, and address information Desc2 written into memory buffer S2 of network message 2, and transmission channel L2 sequentially transmits network message 1 and address information Desc1 written into memory buffer S1 of network message 1.

[0081] In one possible implementation, the status update information includes the value of the identification bit included in each entry in the completion queue. The queue write subunit 233 can update the value of the identification bit in the target entry to a first identification value after writing the address information of the target memory buffer into the target entry. The first identification value is used to indicate that the target entry has been updated. After the target entry is read by the message receiving end, the value of the identification bit in the target entry is updated to a second identification value. The second identification value is used to indicate that the target entry has not been updated.

[0082] The status update information of the completion queue includes the value of the identification bit of each entry in the completion queue. When the message receiving end reads the address information in the completion queue, it will determine whether each entry in the completion queue has been updated based on the value of the identification bit of each entry in the completion queue. After the queue writing subunit 233 writes the address information of the memory buffer into the completion queue, it updates the value of the identification bit in the entry in the completion queue where the address information is written to the first identification value. At this time, the message receiving end can determine that the entry has been updated. After the message receiving end has read the address information in each entry and read the network message from the memory buffer based on the address information, it changes the value of the identification bit in each target entry to the second identification value, thereby indicating that the entry in the completion queue has been read by the message receiving end and is in an unupdated state.

[0083] Fig.11 is a schematic diagram of a write completion queue of an embodiment of the present application, such as Fig.11As shown, the acceleration unit 230 receives network message 0, network message 1 and network message 2 in sequence, the transmission channel L1 transmits network message 0, the address information Desc0 of the memory buffer S0 written into network message 0, network message 2, and the address information Desc2 of the memory buffer S2 written into network message 2 in sequence, the transmission channel L2 transmits network message 1, and the address information Desc1 of the memory buffer S1 written into network message 1 in sequence, at this time, network message 0 and network message 2 have been written into the memory buffer S0 and the memory buffer S2, and the address information of the memory buffer S0 and the memory buffer S2 have been written into the first entry and the third entry of the completion queue, while network message 1 has not been written into the memory buffer S1, and the second entry of the completion queue has not been updated, at this time Fig. 9 It can be seen that the flag values ​​of the first and third entries of the completion queue are 1, and the flag value of the second entry is 0. It should be understood that the above flag values ​​are only used as an example to illustrate the embodiment of the present application, and the specific values ​​are not limited to the embodiment of the present application.

[0084] In an embodiment of the present application, the status update information includes the value of the identification bit included in each entry in the completion queue. After the entry in the completion queue is updated, the value of the identification bit is updated to a first identification value. After the entry in the completion queue is read, the value of the identification bit is updated to a second identification value. Thus, the message receiving end can determine whether each entry in the completion queue is updated. Further, the message receiving end can read the network message from the memory buffer in the order in which the network message is received according to the status update information in the completion queue, thereby avoiding reading errors such as out-of-order network messages.

[0085] In a possible implementation, the status update information may indicate whether each entry in the completion queue has cached data, entries with cached data have been updated, entries without cached data have not been updated, and after the target entry is read by the message receiver, the cached data of the target entry is cleared.

[0086] When each entry in the completion queue caches the address information of the memory buffer, the current entry has been updated. When the message receiving end reads the address information in each entry and reads the network message from each memory buffer according to the address information, the cached data in the corresponding entry in the completion queue is cleared, thereby indicating that the current entry has been read by the message receiving end and is in an unupdated state.

[0087] In an embodiment of the present application, the status update information can indicate whether each entry in the completion queue has cached data. When there is cached data, the entry has been updated; when there is no cached data, the entry has not been updated. Thus, the message receiving end can determine whether each entry in the completion queue is updated. Then, the message receiving end can read the network message from the memory buffer in the order in which the network message is received based on the status update information in the completion queue, thereby avoiding reading errors such as out-of-order network messages.

[0088] In a possible implementation, the queue writing subunit 233 may determine the target entry from the completion queue according to the order in which the receiving subunit 231 receives the network messages and the order in which the entries in the completion queue are read by the message receiving end.

[0089] The queue writing subunit 233 can determine the target entry in the completion queue according to the order in which the receiving subunit 231 receives the network messages and the order in which the entries in the completion queue are read by the message receiving end. For example, the order in which the network messages are received is network message 0, network message 1, and network message 2, and the order in which the queue is read is entry 0, entry 1, and entry 2. At this time, the target entry corresponding to network message 0 is entry 0, the target entry corresponding to network message 1 is entry 1, and the target entry corresponding to network message 2 is entry 2. Therefore, the message receiving end can read network message 0, network message 1, and network message 2 in the order of entry 0, entry 1, and entry 2, thereby realizing reading network messages from multiple memory buffers in the order in which the network messages are received.

[0090] In an embodiment of the present application, the queue writing subunit 233 can determine the target entry from the completion queue according to the order in which the receiving subunit 231 receives the network messages and the order in which the entries in the completion queue are read by the message receiving end. This can write the address information of the memory buffer where the network message is located into the completion queue. Then, the message receiving end can read the network message from the memory buffer in the order in which the network message is received according to the completion queue, thereby avoiding reading errors such as out-of-order network messages.

[0091] In a possible implementation, the message writing subunit 232 may determine that the state information of the target memory buffer may include at least one of frequency information, cache information, and location information. The frequency information is used to indicate the usage frequency of the memory buffer, the cache information is used to indicate whether the data in the memory buffer is read into the cache memory, and the location information is used to indicate the message receiving end to which the memory buffer belongs.

[0092] The state information may include at least one of frequency information, cache information, and location information. For example, the state information may include frequency information and cache information, or the state information may include only location information. When the state information includes two or more of frequency information, cache information, and location information, the acceleration unit 230 determines the target memory buffer in combination with the various information included in the state information. For example, if the state information includes frequency information and cache information, the acceleration unit 230 determines the memory buffer with the highest usage frequency and the cached data read into the cache memory as the target memory buffer.

[0093] In an embodiment of the present application, by determining the target memory buffer through at least one of the frequency information, cache information and location information, a relatively efficient memory buffer can be determined according to the actual usage scenario, thereby improving the efficiency of writing network packets and further improving the efficiency of CPU accessing memory.

[0094] In one possible implementation, the message writing subunit 232 may determine a target memory buffer from multiple memory buffers based on frequency information included in the status information, and there is at least one memory buffer among the multiple memory buffers whose usage frequency is less than the usage frequency of the target memory buffer.

[0095] The usage frequency of a memory buffer is positively correlated with the CPU's read and write efficiency of the memory buffer. Relatively speaking, the higher the usage frequency of a memory buffer, the higher the CPU's read and write efficiency of the memory buffer. The frequency of a memory buffer can be the frequency or number of times the CPU reads and writes the memory buffer. Therefore, based on the frequency information of the memory buffer, a memory buffer with a higher usage frequency can be determined as a target memory buffer.

[0096] When determining the target memory buffer according to the frequency information, the memory buffer with the highest usage frequency among the available memory buffers may be determined as the target memory buffer.

[0097] In an embodiment of the present application, by determining a memory buffer with a higher usage frequency as a target memory buffer, the efficiency of writing network messages can be improved, thereby improving the efficiency of CPU accessing memory.

[0098] In a possible implementation, the message writing subunit 232 may determine, according to the cache information included in the state information, a memory buffer in which data stored in the plurality of memory buffers is read into the cache memory as a target memory buffer.

[0099] It takes hundreds of clock cycles for the CPU to read data from the main memory, and the CPU will be stuck most of the time waiting for data. However, it only takes 2-50 clock cycles for the CPU to read data from the cache memory, so the CPU can read the required data in a shorter time through the cache memory.

[0100] For the memory buffer whose data has been read into the cache memory, there is a high probability that the data cached in the memory buffer will be pre-synchronized to the cache memory, and then when the message receiving end reads the memory buffer, it can read the network message cached in the memory buffer from the cache memory, so as to improve the efficiency of the message receiving end in reading the network message.

[0101] When the state information includes cache information, the memory buffer in which the stored data has been read into the cache memory has a higher access speed for the CPU than the memory buffer in which the stored data has not been read into the cache memory. Therefore, the memory buffer in which the stored data has been read into the cache memory among the multiple memory buffers is determined as the target memory buffer.

[0102] In an embodiment of the present application, the message writing subunit 232 determines the memory buffer in which the stored data is read into the cache memory as the target memory buffer based on the status information, so that the network messages stored in the target memory buffer are likely to be pre-read into the cache memory. When the message receiving end needs to read the network messages in the target memory buffer, the network messages cached in the target memory buffer can be read from the cache memory, thereby improving the efficiency of the message receiving end in reading the network messages.

[0103] Host

[0104] Fig.12 is a schematic diagram of a host provided by an embodiment of the present application, such as Fig.12 As shown, the host 240 includes an allocating subunit 241 that allocates multiple memory buffers, and the memory buffers are used to cache network messages sent by the acceleration unit 230 through at least two transmission channels. The reading subunit 242 can read network messages from the multiple memory buffers according to the status update information and the completion queue, in the order in which the acceleration unit receives the network messages, wherein the status update information is used to indicate the updated entry in the completion queue, and the memory buffer corresponding to the cached address information in the updated entry has been written to the network message.

[0105] The allocation subunit 241 in the host can be allocated with multiple memory buffers for caching network packets. The memory buffers are located in the main memory (also called memory, internal memory) of the host. The memory buffers can cache network packets sent by the acceleration unit 230 through at least two transmission channels.

[0106] The reading subunit 242 can determine whether each entry in the completion queue is updated based on the status update information, and read the cached data in the updated entry according to the reading order of the completion queue, and read the network message from the corresponding memory buffer based on the cached data in the updated entry. When reading an unupdated entry, the reading of the completion queue is suspended until the unupdated entry is updated, and then the reading of the completion queue from the entry is continued. Therefore, when the subsequent entry in the completion queue has been updated and the preceding entry has not been updated, the subsequent entry will not be read, ensuring that the order of reading the network message from the memory buffer is the same as the order in which the acceleration unit 230 receives the network message, and after reading the network message, the status update information of the corresponding entry in the completion queue is updated to not updated, for example: the value of the identification bit of the corresponding entry in the completion queue is updated to the second identification value, or the cached data in the completion queue is cleared, etc.

[0107] In an embodiment of the present application, the allocation subunit 241 can allocate multiple memory buffers, thereby caching the network messages sent by the acceleration unit 230. The reading subunit 242 can read the cached address information in the updated entries in the completion queue based on the status update information and the completion queue. Therefore, the network messages can be read from the memory buffer indicated by the address information in the order in which the acceleration unit 230 receives the network messages, thereby avoiding reading errors such as disordered network messages. After reading the network messages, the status update information of the corresponding entries in the completion queue is updated to not updated, thereby avoiding repeated reading of network messages, thereby improving the efficiency and accuracy of reading network messages.

[0108] System on Chip

[0109] An embodiment of the present application further provides a system on chip, which includes the acceleration unit 230 in any of the above embodiments.

[0110] It should be noted that the application of the acceleration unit 230 in the embodiment of the present application is not limited to the system on chip, but can also be applied in various other suitable ways. For example, the acceleration unit 230 and the processing unit (CPU), main memory and other interactive components are deployed on a printed circuit board, and the acceleration unit 230 interacts with the processing unit (CPU), main memory, etc. through a bus on the printed circuit board.

[0111] Message transmission acceleration method

[0112] The acceleration unit 230 in the aforementioned embodiment can be applied to a network virtualization scenario to realize the transmission of network packets to the packet receiving end. The acceleration unit 230 writes the received network packets into a memory buffer allocated by the host. The following is an example of a packet transmission acceleration method to illustrate the working process of the acceleration unit 230 in a network virtualization scenario.

[0113] Fig.13 FIG. 1 is a flow chart of a method for accelerating message transmission according to an embodiment of the present application. Fig.13 As shown, the message transmission acceleration method includes the following steps:

[0114] Step 1201: receiving a network message through a network;

[0115] Step 1202: write the network message into the target memory buffer through the target transmission channel;

[0116] Wherein, the target transmission channel is determined from at least two transmission channels, and the target memory buffer is determined from a plurality of memory buffers allocated by the host;

[0117] Step 1203: After the network message is written into the target memory buffer, at least the address information of the target memory buffer is written into the target entry in the completion queue through the target transmission channel, and the status update information indicates that the target entry has been updated, so that the message receiving end on the host reads the network message from multiple memory buffers according to the completion queue and the status update information and in the order in which the receiving sub-unit receives the network message.

[0118] In the embodiment of the present application, after receiving the network message, a target transmission channel is selected from at least two channels to write the network message into the target memory buffer. After the network message is written, at least the address information of the memory buffer is written into the completion queue through the target transmission channel, and the status update information indicates that the target entry has been updated, and then the network message receiving end on the host can read the network message from the memory buffer in the order in which the network message is received according to the completion queue and the status update information, thereby realizing the transmission of the network message. Since the target transmission channel is selected from at least two transmission channels, different network messages can be transmitted through different transmission channels. Compared with transmitting the network message through a single channel, the time consumed by transmitting the same number of network messages through multiple channels is shorter, thereby improving the transmission efficiency of the network message, and since the status update information is provided, the message receiving end can read the network message in the order in which the network message is received, realizing the multi-channel transmission of the network message while maintaining the order of the network message, avoiding the disorder caused by the multi-channel transmission of the network message, thereby improving the efficiency of writing the network message into the memory buffer.

[0119] It should be noted that the message transmission acceleration method of the embodiment of the present application is a specific application of the acceleration unit 230 in the aforementioned embodiment in the network virtualization scenario. The specific message transmission acceleration method can be found in the description in the aforementioned acceleration unit embodiment, which will not be repeated here.

[0120] The commercial value of the present application embodiment

[0121] In an embodiment of the present application, after the receiving subunit receives the network message, the network message writing subunit can select a target transmission channel from at least two channels to write the network message into the target memory buffer, thereby realizing the transmission of the network message through multiple channels. The queue writing subunit can write at least the address information of the memory buffer into the completion queue through the target transmission channel after the network message is written, and make the status update information indicate that the target entry has been updated, and then the network message receiving end on the host can read the network message from the memory buffer in the order in which the network message is received according to the address information in the completion queue, thereby realizing the transmission of the network message. Since the target transmission channel is selected from at least two transmission channels, compared with the single-channel transmission of network messages in the related art, the time consumed to transmit the same number of network messages is shorter, thereby improving the transmission efficiency of the network message, and since the status update information is provided, the network message receiving end can read the network message in the order in which the network message is received by the receiving subunit, thereby realizing the multi-channel transmission of the network message while maintaining the order of the network message, avoiding the disorder caused by the multi-channel transmission of the network message, thereby improving the efficiency of writing the network message into the memory buffer. This solution can be applied to network virtualization scenarios, such as data centers, and has good market prospects.

[0122] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0123] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0124] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0125] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0126] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. An acceleration unit, comprising: A receiving subunit, used for receiving network messages through the network; A message writing subunit, used for writing the network message into a target memory buffer through a target transmission channel, wherein the target transmission channel is determined from at least two transmission channels, and the target memory buffer is determined from a plurality of memory buffers allocated by the host; The queue writing subunit is used to write at least the address information of the target memory buffer into the target entry in the completion queue through the target transmission channel after the network message is written into the target memory buffer, and make the status update information indicate that the target entry has been updated, so that the message receiving end on the host reads the network message from the multiple memory buffers according to the completion queue and the status update information and in the order in which the network message is received by the receiving subunit.

2. The acceleration unit according to claim 1, further comprising: The first load balancing subunit is used to obtain transmission data volume information, where the transmission data volume information is used to indicate the amount of data to be transmitted on the transmission channel, and determine the target transmission channel from the at least two transmission channels according to the transmission data volume information.

3. The acceleration unit according to claim 1, further comprising: The second load balancing subunit is used to obtain transmission time consumption information, where the transmission time consumption information is used to indicate the time consumption for the transmission channel to complete the transmission of the data to be transmitted, and determine the target transmission channel from the at least two transmission channels according to the transmission time consumption information.

4. The acceleration unit according to claim 1, wherein: The status update information includes the value of the flag bit included in each entry in the completion queue; The queue write sub-unit is used to update the value of the identification bit in the target entry to a first identification value after writing the address information of the target memory buffer into the target entry, wherein the first identification value is used to indicate that the target entry has been updated; after the target entry is read by the message receiving end, the value of the identification bit in the target entry is updated to a second identification value, wherein the second identification value is used to indicate that the target entry has not been updated.

5. The acceleration unit according to claim 1, wherein: The status update information is used to indicate whether each entry in the completion queue has cached data, entries with cached data have been updated, and entries without cached data have not been updated. After the target entry is read by the message receiving end, the data cached in the target entry is cleared.

6. The acceleration unit according to claim 1, wherein: The queue writing subunit is used to determine the target entry from the completion queue according to the order in which the receiving subunit receives the network messages and the order in which the entries in the completion queue are read by the message receiving end.

7. The acceleration unit according to any one of claims 1 to 6, wherein: The message writing subunit is used to determine the target memory buffer from the multiple memory buffers based on at least one of the frequency information, cache information and location information of the memory buffer, the frequency information is used to indicate the usage frequency of the memory buffer, the cache information is used to indicate whether the data in the memory buffer is read into the cache memory, and the location information is used to indicate the message receiving end to which the memory buffer belongs.

8. A host, comprising: An allocating subunit, used for allocating a plurality of memory buffers, wherein the memory buffers are used for caching network messages sent by the acceleration unit through at least two transmission channels; A reading sub-unit is used to read network messages from the multiple memory buffers according to the status update information and the completion queue, in the order in which the acceleration unit receives the network messages, wherein the status update information is used to indicate the updated entries in the completion queue, and the memory buffer corresponding to the cached address information in the updated entries has been written to the network message.

9. A computing device comprising: A processing unit for constructing a host, wherein the host is used to allocate a plurality of memory buffers; An acceleration unit according to any one of claims 1 to 7.

10. A system on chip, comprising: An acceleration unit according to any one of claims 1 to 7.

11. A server deployed in a data center, provided with an acceleration unit as claimed in any one of claims 1 to 7.

12. A data center, comprising: The server according to claim 11.

13. An Internet network comprising: A message receiving device and at least one message sending device; The message receiving device comprises an acceleration unit as described in any one of claims 1 to 7; The message sending device is connected to the acceleration unit included in the message receiving device through a network, and the message sending device is used to send the message sent to the message receiving end on the message receiving device to the acceleration unit.

14. A method for accelerating message transmission, comprising: Receiving network messages through the network; Writing the network message into a target memory buffer through a target transmission channel, wherein the target transmission channel is determined from at least two transmission channels, and the target memory buffer is determined from a plurality of memory buffers allocated by the host; After the network message is written into the target memory buffer, at least the address information of the target memory buffer is written into the target entry in the completion queue through the target transmission channel, and the status update information indicates that the target entry has been updated, so that the message receiving end on the host reads the network message from the multiple memory buffers according to the completion queue and the status update information and in the order in which the receiving sub-unit receives the network message.

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