Method for displaying power-on state of server mainboard through LED

Abstract

The invention discloses a method for displaying the power-on state of a server mainboard through an LED. The method comprises the steps that all related signals in the power-on time sequence process of the server mainboard are connected to a CPLD; sequentially numbering all related signals in the power-on time sequence process from low to high according to a time sequence; when the CPLD detects that the mainboard is not powered on, the CPLD sequentially detects whether the related signals are in an effective state or not according to a serial number sequence, and transmits a numerical value a with the minimum serial number in the signals which are not effective to a processing program; the processing program controls the power-on error lamp to flicker once and counts the flicker frequency of the CPLD heartbeat lamp, and when the count frequency reaches the value a, the processing program controls the power-on error lamp to flicker once again; according to the twinkling count of the CPLD heartbeat lamp between the two times of twinkling of the power-on error lamp, the code a of the abnormal signal generated at the earliest time in the power-on time sequence of the server mainboard is obtained, and the position of the abnormal signal in the power-on time sequence can be found.

Description

Technical Field

[0001] The invention relates to the technical field of server status detection, and in particular to a method for displaying the power-on status of a server mainboard through an LED. Background Art

[0002] Currently, most servers on the market only use a few lights to display the key stages of the server power-on status, such as RSMRST_N, S3_N, CPU_PWRGD, and PLTRST_N. After judging the status of some key signals by whether these lights are lit, a multimeter is used to measure more detailed power-on timing control signals to determine where the server's power-on process stops.

[0003] The above solution has the following problems:

[0004] 1. Only several key stages of server power-on can be displayed.

[0005] 2. While measuring with a multimeter, you also need to look for the timing diagram, schematic diagram, and PCB file for each signal, and then find the points on the PCB to measure. Sometimes you need to check multiple signals to determine the specific problem.

[0006] 3. When the motherboard is not powered on, it will be troublesome and time-consuming to locate the problem. If all the timing control signals need to be displayed through different LED signals, dozens of LED lights will be needed, which will not only increase the cost, but also waste space on the PCB and look very unsightly.

[0007] Therefore, there is an urgent need for a simple method of displaying the power-on status of a server mainboard through an LED. Summary of the invention

[0008] In order to solve the problems in the prior art, the present invention proposes a method for displaying the power-on status of a server mainboard through an LED.

[0009] The present invention is specifically implemented through the following technical solutions:

[0010] A method for displaying the power-on status of a server mainboard through an LED, the method comprising:

[0011] Connect all the related signals in the power-on sequence process of the server motherboard to the CPLD;

[0012] Number all the related signals in the power-on sequence of the server mainboard from low to high in sequence;

[0013] When the CPLD detects that the mainboard is not powered on, the CPLD will detect whether the relevant signals are in the effective state in sequence according to the numbering order, and transmit the value a with the smallest number among the ineffective signals to the processing program;

[0014] The processing program controls the power-on error light to flash once, and counts the number of flashes of the CPLD heartbeat light. When the counted number reaches the a value, the processing program controls the power-on error light to flash once again.

[0015] According to the flash count of the CPLD heartbeat light between two power-on error light flashes, the code a of the earliest abnormal signal occurring in the power-on sequence of the server mainboard is obtained, and the position of the abnormal signal in the power-on sequence can be found;

[0016] As a further improvement of the present invention, the processing program first controls the power-on error light to light up for a first preset time and then turn off to remind the server mainboard that there is an error in powering on; then, the number of times the CPLD heartbeat light flashes is counted.

[0017] As a further improvement of the present invention, the flashing of the CPLD heartbeat light is that the CPLD heartbeat light is lit for a second preset time length and then turns off.

[0018] As a further improvement of the present invention, the processing program counts the number of flashes i of the CPLD heartbeat light, and when i=a+1, the error light flashes once more and i is cleared.

[0019] As a further improvement of the present invention, when all relevant signals in the power-on sequence process of all server mainboards are normal, the power-on error light will not be lit.

[0020] As a further improvement of the present invention, the power-on error light is orange and the CPLD heartbeat light is green.

[0021] As a further improvement of the present invention, the first preset time length is 0.5 seconds, and the second preset time length is 0.5 seconds.

[0022] The beneficial effect of the present invention is that compared with the existing technology, the method of the present invention can display at which signal the power-on process of the server stops only by coordinating an error light (orange) with the heartbeat light (green) of the CPLD, which not only saves costs but also makes the PCB layout look neat. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A circuit connection diagram of the present invention;

[0024] Figure 2 It is a software flow chart of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods.

[0026] Hardware design methods, such as Figure 1 As shown, the present invention connects all relevant signals in the power-on timing process of the server motherboard to the CPLD, and then outputs the control signal of the power-on error light and the control signal of the heartbeat light through the CPLD to control the lighting status of the above two lights, and then displays the power-on status of the server through the cooperation of the above two lights.

[0027] like Figure 2 Shown is a software program design flow chart of the present invention.

[0028] All the related signals in the power-on sequence of the server mainboard are numbered in sequence from low to high.

[0029] When the CPLD detects that the mainboard is not powered on, the CPLD will detect whether these signals are in valid state in order of number, and transmit the smallest value a among the invalid signals to the power-on error light processing program (Fault_led).

[0030] The Fault_led program first controls the power-on error light to light up for the first preset time and then turn off to remind the server that there is an error in the power-on of the mainboard. The CPLD heartbeat light lights up for the second preset time and then turns off, which we call a flash. Then, the number of flashes of the CPLD heartbeat light i is counted. When i=a+1, the power-on error light flashes once again and i is cleared. When all signals are normal, the power-on error light will not be lit.

[0031] When the server motherboard designer finds that the motherboard cannot be powered on normally, he only needs to count the number of times the CPLD heartbeat light is on during the interval between the two times the power-on error light is on. He can then obtain the code a of the earliest abnormal signal that occurred in the power-on sequence, and quickly find the abnormal signal in the power-on sequence.

[0032] The present invention realizes the detection and display of the power-on status of the server through the cooperation of the hardware circuit and the CPLD, brings great convenience to the positioning of the problem that the server mainboard does not power on, and saves time and cost.

[0033] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention. For ordinary technicians in this field, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for displaying the power-on status of a server mainboard through an LED, characterized in that: The method comprises: Connect all the related signals in the power-on sequence process of the server motherboard to the CPLD; Number all the related signals in the power-on sequence of the server mainboard from low to high in sequence; When the CPLD detects that the mainboard is not powered on, the CPLD will detect whether the relevant signals are in the effective state in sequence according to the numbering order, and transmit the value a with the smallest number among the ineffective signals to the processing program; The processing program controls the power-on error light to flash once, and counts the number of flashes of the CPLD heartbeat light. When the counted number reaches the a value, the processing program controls the power-on error light to flash once again. According to the flash count of the CPLD heartbeat light between two power-on error light flashes, the code a of the earliest abnormal signal occurring in the power-on sequence of the server mainboard is obtained, and the position of the abnormal signal in the power-on sequence can be found.

2. The method according to claim 1, wherein: The processing program first controls the power-on error light to light up for a first preset time and then turn off to remind the server mainboard that there is an error in powering on; Then, count the number of times the CPLD heartbeat light flashes.

3. The method according to claim 2, wherein: The processing program counts the number of flashes of the CPLD heartbeat light, and when i=a+1, the power-on error light flashes again and i is cleared.

4. The method according to any one of claims 1 to 3, wherein: The flashing of the CPLD heartbeat light is that the CPLD heartbeat light is lit for a second preset time and then turns off.

5. The method according to claim 1, wherein: When all the related signals in the power-on sequence process of all server mainboards are normal, the power-on error light will not be lit.

6. The method according to claim 1, wherein: The power-on error light is orange, and the CPLD heartbeat light is green.

7. The method according to claim 3, wherein: The first preset time length is 0.5 seconds, and the second preset time length is 0.5 seconds.

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