Memory asynchronous interface module, parameterization design method and chip
By designing a memory asynchronous interface module, efficient asynchronous data exchange between the memory and the core is solved, the problem of large resource consumption in the existing technology is solved, circuit area and power consumption is reduced, and compatibility and module multiplexing capabilities are improved.
Patent Information
- Application Number
- CN202411232217.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2025-01-07
AI Technical Summary
When implementing asynchronous data exchange between memory and core, the prior art consumes a large resource, high circuit area and power consumption, and it is difficult to compatible with different data widths and interface modes.
Design a memory asynchronous interface module, including interface configuration registers, equivalent conversion modules, edge detection modules, counter modules, data byte assembly modules and index registers, and stores configuration information through configuration registers, supporting data width configuration and signal polarity Conversion, implements asynchronous to synchronous fast conversion and reduces the number of control signals.
It reduces circuit area and power consumption, improves memory chip compatibility and module multiplexing capabilities, supports multiple data widths and interface modes, and shortens design cycles.
Smart Images
Figure CN119272697A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of asynchronous data interface design of digital integrated circuits, and in particular to a memory asynchronous interface module, a parameterized design method, and a chip. Background Art
[0002] With the development of integrated circuit technology, more and more chips support asynchronous high-speed parallel interfaces to support the expansion of external high-speed memories.
[0003] The memory and the core need to exchange data securely and reliably, and support as high a rate as possible, so an efficient and reliable asynchronous handover method is needed to implement read and write functions.
[0004] At present, the technology often uses the synchronous conversion bridge method to convert multi-bit asynchronous data into the internal clock domain. However, this implementation method consumes a lot of resources, and the circuit area and power consumption will also be larger. Summary of the invention
[0005] Purpose of the invention: To provide a memory asynchronous interface module to solve the above problems existing in the prior art.
[0006] Technical solution: A memory asynchronous interface module is applied to a system-level chip or a memory chip. The host reads and writes the memory chip or the system-level chip register through the asynchronous interface module, and the chip completes the rapid conversion between asynchronous and synchronous through the interface module; The interface module comprises: Interface configuration registers for data width configuration, control signal polarity configuration, control signal operation method configuration (read, write individual signal control or direction and enable control), chip select control configuration, address and data multiplexing, and indexed address mode switching configuration; An equivalent conversion module for converting direction and enable signals into read and write signals; An edge detection module for generating an internal clock synchronization signal, a valid rising edge pulse, and edge detection of an input read / write signal; A counter module for sorting the address and control signals of the input sequence to realize sequence detection; A data byte assembly module for adapting the memory or register data width and assembling the input write bytes; A write data latch register for sampling and latching data from a write data interface; A read data output register for internally locking the data to be output; In multiplexing mode, a pulse detection module for address sampling signals; In multiplexing mode, the address latch register samples and latches the input address data; In the indexed addressing mode, the byte order register is used to dynamically configure the endianness of the input and output bytes; In the indexing mode, the indexing register is used to store the internal address and sample and latch the interface data.
[0007] In a further embodiment, the configuration information of the interface configuration register is stored in the register in an encoded form; The value of configuration information is obtained, including: The value of the configuration information is loaded from EEPROM (Electrically Erasable Programmable read only memory) and will not change during use, so it is used as a fixed hardware configuration. The value of the configuration information is obtained through hardware configuration. A group of pins are used to encode the configuration information by pulling up and down levels. The configuration pins are sampled during the memory power-on process, and the sampled values are stored in the interface configuration register.
[0008] Two methods can be selected, and the configuration information source is selected through separate pin configuration.
[0009] The data width is configured as 8, 16, or 32 bits of the host bus interface data interface width, which refers to the number of parallel data bits that can be transmitted when the interface sequence is enabled once.
[0010] The control signal polarity may be high effective or low effective, depending on the output sequence polarity supported by the host.
[0011] In a further embodiment, the read, write and direction enable pins of the interface module are multiplexed pins; When read / write mode is selected, two separate pins control read and write operations; Select the enable mode, one pin controls the initiation of the read and write process, and the other pin indicates the read and write direction; The data and address pins of the interface module are multiplexed pins; When the multiplexing mode is selected, the address and data pins are time-division multiplexed, and the address is latched or the read-write data is read when the corresponding control signal is valid; When the indexed addressing mode is selected, the address and data lines are separated, with a separate register provided for storing the register address, and the address line is used to select the channel group number.
[0012] In a further embodiment, the counter module is an internal counter for monitoring input and output sequences and issuing read and write operations; For the indexed address mode, the counter has a separate counter for each group of channels to achieve cross-read and write access by multiple threads without affecting each other.
[0013] In a further embodiment, the pulse detection module includes a pulse detection synchronizer; The address latch signal is sampled using a pulse detection synchronizer for address synchronization; The edge detection module includes an edge detection synchronizer; The read and write signals are sampled using an edge detection synchronizer for sampling or locking and counting functions of read and write data; the direction and enable signals are multiplexed with the read and write pins and converted internally according to the configuration information.
[0014] In a further embodiment, under typical applications, the input read / write signal frequency is less than or equal to 22M, and the signal valid time within the cycle is not less than 32ns; The pulse frequency of the input address latch signal is less than or equal to 16M, and the effective time of the signal within the cycle is not less than 10ns; The internal clock frequency of the interface module is greater than or equal to 100M. As the internal clock frequency increases, the supported interface frequency increases accordingly.
[0015] In a further embodiment, in the indexed address mode, the byte order register is only for the case in the indexed address mode, and the register is invalid when the multiplexing mode is configured; In multiplexed mode, the host provides the required byte order configuration information in the address field; The byte order register has a default value after reset, which is little endian, and has separate configuration bits for each group of channels.
[0016] A parameterized design method for a memory asynchronous interface is implemented based on the memory asynchronous interface module, comprising: The control signal polarity, control signal operation method, and chip select control are configured to not be allowed to be changed by the user, and the parameters are configured as required to set the relevant registers to fixed values without triggers; The interface data width does not need to support the full width, and the user does not need to configure relevant information. The internally designed read data output register and write data latch register width are changed to the required value to save circuit area; The number of channels in the indexed addressing mode, when the module is instantiated, the number of channel modules can be increased or decreased as needed, and the channel interface can be connected to a dedicated register or memory array for partitioned use.
[0017] A chip comprises the memory asynchronous interface module.
[0018] Beneficial effects: The present invention discloses a memory asynchronous interface module, a parameterized design method, and a chip. The interface module is applied to a system-level chip or a memory chip. The host reads and writes the memory or the system-level chip register through an asynchronous interface. The chip completes the rapid conversion between asynchronous and synchronous through the module, thereby reducing the resources consumed in the asynchronous to synchronous conversion, reducing the area and power consumption of the circuit implementation; reducing the number of required control signals, increasing the number of user-configurable contents, and improving the compatibility of the memory chip; the interface system is parameterized and modularized, and interfaces of various data widths can be adapted by changing parameters, thereby shortening the design cycle and improving the module reuse capability. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a structural block diagram of an asynchronous interface module using a memory chip as an example provided in this application.
[0020] Figure 2 This is a circuit structure block diagram of the edge detection module provided in this application.
[0021] Figure 3 This is a circuit structure block diagram of the pulse detection module provided in this application.
[0022] Figure 4 This is a data flow description block diagram using a system-on-chip as an example provided in this application. DETAILED DESCRIPTION
[0023] The present application relates to a memory asynchronous interface module, a parameterized design method, and a chip, which are explained in detail below through specific implementation methods.
[0024] A memory asynchronous interface module is provided. The device is integrated in a SoC (System on Chip), such as an MCU (Microcontroller Unit).
[0025] This module is also compatible with a variety of peripherals, such as SRAM (Static Random-Access Memory).
[0026] like Figure 1 ,The interface module contains the following sub-modules.
[0027] The interface configuration register includes data width configuration, control signal polarity configuration, control signal operation method configuration (read and write separate signal control or direction and enable control), chip select control configuration, address and data multiplexing indexing mode switching configuration. The configuration information of the interface configuration register is stored in the register in coded form.
[0028] These configuration values can be loaded through EEPROM (Electrically Erasable Programmable readonly memory), and will not change during use, and are used as fixed hardware configurations; It can also be obtained through hardware configuration. A set of pins can be used to encode configuration information by pulling up and down levels. The configuration pins are sampled during the power-on process of the memory, and the sampled values are stored in the configuration register.
[0029] Two methods can be selected, and the configuration information source is selected through separate pin configuration.
[0030] The data width is configured as 8, 16, or 32 bits of the host bus interface data interface width, which refers to the number of parallel data bits that can be transmitted when the interface sequence is enabled once.
[0031] The control signal polarity may be high effective or low effective, depending on the output sequence polarity supported by the host, and may be user-configured or set to a fixed value.
[0032] The read, write and direction enable pins of the interface are multiplexed. Users can choose to use read / write mode (two separate pins control read and write operations) or enable mode (one pin controls the initiation of the read / write process, and the other pin indicates the read / write direction), and the polarity can be freely configured; these two sets of pins are generally multiplexed, and the function depends on the user configuration.
[0033] The data and address pins of the interface are multiplexed, and the user can choose to use the multiplexing mode (the address and data pins are time-division multiplexed, and the address is latched or the read and write data is read when the corresponding control signal is valid) or the indexing mode (the address and data lines are separated, but there is a separate register for storing the register address, and the address line is used to select the channel group number).
[0034] The equivalent conversion module converts the direction and enable signals into read and write signals. When the enable signal is valid, it always indicates the start of the read and write process, and the direction signal indicates the direction of the read and write operations. This module completes the conversion to read and write signal separation, facilitates the next step of operation merging, and simplifies the logic.
[0035] The edge detection module for edge detection of read and write signals includes generating signals synchronized with the internal clock and valid rising edge pulses. The module inputs control signals and uses the internal clock for synchronous sampling. Figure 2As shown in the figure, the detector uses a three-stage D flip-flop cascade. The Q end of the second-stage flip-flop and the Q end of the third-stage flip-flop are inverted, and both enter the AND gate to generate a pulse with a valid rising edge. The Q end of the second-stage flip-flop is also used as a synchronous control signal. In typical applications, the basic requirements for using this module are that the input control signal frequency must be less than or equal to 22M, and the signal valid time within the cycle must be no less than 32ns; the internal clock frequency of the interface module must be greater than or equal to 100M. As the internal clock frequency increases, the supported interface frequency can also increase accordingly.
[0036] The write data latch register for data sampling and latching of the write data interface is a register of the data pin sampled at the invalid edge of the WR (write) signal. Usually such multi-bit data takes a long time to reach a steady state, so an additional valid signal is required to mark the data steady state and synchronize it within another module.
[0037] The read data output register is internally locked for the data to be output. When the RD (read) signal is low (read invalid state, indicating that the host is not in the read request state) during the internal clock synchronization, the corresponding register or the value of the corresponding address of the memory array is selected and locked according to the latched address. The locked value remains unchanged until the signal indicates a read request.
[0038] In multiplexing mode, the pulse detection module of the address sampling signal generates an internal clock synchronous rising edge pulse indicating that the address is valid. The module inputs the ALE (address latch enable) signal as the clock, which causes the internal one-bit flip-flop to self-flip and use the internal clock for edge detection. Figure 3 As shown, a trigger is connected in the previous stage of the edge detection synchronizer, and the inverted output of the Q end of this trigger enters the D end through a controlled selector.
[0039] The control signals are combinational logic of reset and configuration bits.
[0040] In typical applications, the basic requirement for using this module is that the pulse frequency of the input control signal must be less than or equal to 16M, and the effective time of the signal within the cycle must be no less than 10ns; The internal clock frequency of the interface module must be greater than or equal to 100M. As the internal clock frequency increases, the supported interface frequency can also increase accordingly.
[0041] In multiplex mode, the input address data is sampled and latched into the address latch register.
[0042] The data pin is sampled at the invalid edge of the ALE signal. Usually, such multi-bit data requires a long time to reach a steady state. Therefore, when the pulse output by the pulse detection synchronization module of the above-mentioned address sampling signal is valid, it marks the steady state of the data and is synchronized inside the module.
[0043] The address and control signals of the input sequence are sorted to realize the counter module of sequence detection. When the effective pulse of the control signal generated in the above-mentioned edge detection synchronization module is in the effective state, it indicates that the value in the above-mentioned address register is valid and steady-state. The module determines whether it is in the normal sequence according to the last bit of the input address. If the address input is normal, the process proceeds normally and a read-write update pulse is issued; if the address input is abnormal, the process is interrupted and the counter is reset. The write update pulse is used to issue a write operation to the memory; the read update is used for register self-update, for example, some registers or FIFOs whose read behavior will change can be connected. The counter is an internal counter and is not accessible from the outside. For this asynchronous interface in the address displacement mode, the counter has a separate counter for each group of channels to realize multi-threaded cross-read and write access, and each thread does not affect each other.
[0044] The data byte assembly module assembles the input write bytes to adapt the memory or register data width. When the valid pulse of WR synchronization is high, it indicates that the values in the above write data register and address register are valid and stable. At this time, the data in the write data register is arranged and combined in address and byte order, and the write bytes (or words and double words) are written to the registers in the module.
[0045] In indexed mode, a byte order register that dynamically configures the endianness of the input and output bytes. The byte order register is only for the indexed mode and is invalid when the multiplexed mode is configured. In multiplexed mode, the host provides the required byte order configuration information in the address field. The byte order register has a default value after reset, which defaults to little endian, and has separate configuration bits for each group of channels.
[0046] In the indexing mode, the indexing register that samples and latches the interface data is used to store the internal address. The indexing register is only for the case of indexing mode, and the register is invalid when the multiplexing mode is configured. In the multiplexing mode, the host uses the ALE signal to send the address to the slave.
[0047] This device can quickly complete the conversion between asynchronous and synchronous parallel read and write operations through configurable registers and multiplexed interfaces, and has high compatibility and flexibility. It can be implemented as a hardware interface of a memory chip, supporting the access of various host bus interface controllers; it can also be used as a slave peripheral of a SoC or a register read and write interface of a slave controller to provide reading and writing to an external host. Example
[0048] This embodiment provides a parameterized design method for a memory asynchronous interface, including: In actual ASIC design or FPGA design, internal design resources adjust parameters according to requirements. These parameters are changed when the module is instantiated and become fixed parameters after synthesis.
[0049] The interface data width does not need to support the full width, and the user does not need to configure relevant information. Therefore, the internally designed read data output register and write data latch register width can be changed to the required value to save circuit area.
[0050] The number of channels in the indexed addressing mode can be increased or decreased as needed when the module is instantiated. At the same time, the channel interface can be connected to a dedicated register or memory array for partitioned use.
[0051] The control signal polarity, control signal operation method, and chip select control configuration are not allowed to be changed by the user. The parameters can be configured as required to set the relevant registers to fixed values without triggers, which is used to save circuit area. Example
[0052] This embodiment provides a memory chip with an asynchronous interface, including: The memory asynchronous interface module described in the first embodiment is used in combination with a memory chip made of a static memory (such as SRAM, ROM, PSRAM, NOR Flash and NAND Flash memory), and the implementation method is as follows: Figure 1 ; The memory asynchronous interface module described in the first embodiment is used in combination with a slave controller chip made of a functional core and a register array, and the implementation method is as follows: Figure 4 .
[0053] The preferred specific embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above specific embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical scheme of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.
Claims
1. A memory asynchronous interface module, applied to a system-level chip or a memory chip, characterized in that: include: The host reads and writes the memory chip or the system-level chip register through the asynchronous interface module, and the chip completes the rapid conversion between asynchronous and synchronous through the interface module; The interface module comprises: Interface configuration registers for data width configuration, control signal polarity configuration, control signal operation method configuration, chip select control configuration, address and data multiplexing, and indexing mode switching configuration; An equivalent conversion module for converting direction and enable signals into read and write signals; An edge detection module for generating an internal clock synchronization signal, a valid rising edge pulse, and edge detection of an input read / write signal; A counter module for sorting the address and control signals of the input sequence to realize sequence detection; A data byte assembly module for adapting the memory or register data width and assembling the input write bytes; A write data latch register for sampling and latching data from a write data interface; A read data output register for internally locking the data to be output; In multiplexing mode, a pulse detection module for address sampling signals; In multiplexing mode, the address latch register samples and latches the input address data; In the indexed addressing mode, the byte order register is used to dynamically configure the endianness of the input and output bytes; In the indexing mode, the indexing register is used to store the internal address and sample and latch the interface data.
2. A memory asynchronous interface module according to claim 1, characterized in that: The configuration information of the interface configuration register is stored in the register in a coded form; The value of configuration information is obtained, including: The value of the configuration information is loaded from the EEPROM and does not change during use, and is used as a fixed hardware configuration; The value of the configuration information is obtained through hardware configuration. A group of pins are used to encode the configuration information by pulling up and down levels. The configuration pins are sampled during the power-on process of the memory, and the sampled values are stored in the interface configuration register.
3. The memory asynchronous interface module according to claim 1, characterized in that: The read, write and direction enable pins of the interface module are multiplexed pins; When read / write mode is selected, two separate pins control read and write operations; Select the enable mode, one pin controls the initiation of the read and write process, and the other pin indicates the read and write direction; The data and address pins of the interface module are multiplexed pins; When the multiplexing mode is selected, the address and data pins are time-division multiplexed, and the address is latched or the read / write data is read when the corresponding control signal is valid; When the indexed addressing mode is selected, the address and data lines are separated, with a separate register provided for storing the register address, and the address line is used to select the channel group number.
4. The memory asynchronous interface module according to claim 1, characterized in that: The counter module is an internal counter used to monitor input and output sequences and issue read and write operations; For the indexed address mode, the counter has a separate counter for each group of channels to achieve cross-read and write access by multiple threads without affecting each other.
5. The memory asynchronous interface module according to claim 1, characterized in that: The pulse detection module includes a pulse detection synchronizer; The address latch signal is sampled using a pulse detection synchronizer for address synchronization; The edge detection module includes an edge detection synchronizer; The read and write signals are sampled using an edge detection synchronizer for sampling or locking and counting functions of read and write data; the direction and enable signals are multiplexed with the read and write pins and converted internally according to the configuration information.
6. The memory asynchronous interface module according to claim 1, characterized in that: In typical applications, the input read / write signal frequency is less than or equal to 22M, and the signal valid time within the cycle is not less than 32ns; The pulse frequency of the input address latch signal is less than or equal to 16M, and the effective time of the signal within the cycle is not less than 10ns; The internal clock frequency of the interface module is greater than or equal to 100M. As the internal clock frequency increases, the supported interface frequency increases accordingly.
7. The memory asynchronous interface module according to claim 1, characterized in that: In the indexed address mode, the byte order register is only for the indexed address mode. When the multiplexing mode is configured, the register is invalid. In multiplexed mode, the host provides the required byte order configuration information in the address field; The byte order register has a default value after reset, which is little endian, and has separate configuration bits for each group of channels.
8. A parameterized design method for a memory asynchronous interface, implemented based on the memory asynchronous interface module according to any one of claims 1 to 7, characterized in that: include: The control signal polarity, control signal operation method, and chip select control configuration are not allowed to be changed by the user. The parameters are configured as fixed values for the relevant registers without triggers as needed; The interface data width does not need to support the full width, and the user does not need to configure relevant information. The internally designed read data output register and write data latch register width are changed to the required value to save circuit area; The number of channels in the indexed addressing mode, when the module is instantiated, the number of channel modules can be increased or decreased as needed, and the channel interface can be connected to a dedicated register or memory array for partitioned use.
9. A chip, characterized in that: A memory asynchronous interface module comprising any one of claims 1 to 7.