Display panel and display device

Abstract

The invention provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a source electrode driving circuit, a switching circuit and at least two signal transmission lines, the source driving circuit comprises at least four level conversion sub-circuits and a driving sub-circuit; the level conversion sub-circuit comprises a first control end, a first input end and a first output end; the switching circuit comprises at least two second control ends, a second input end and at least two second output ends; the at least four level conversion sub-circuits comprise at least two effective level conversion sub-circuits; any signal transmission line is electrically connected with the first output end of at least one effective level conversion sub-circuit in each source electrode driving circuit. Different signal transmission lines are electrically connected with different effective level conversion sub-circuits; one signal transmission line is electrically connected with one second control end of each switching circuit, and different signal transmission lines are electrically connected with different second control ends.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] With the rapid development of the display field, the resolution of display panels is constantly improving. For example, the current Full High Definition (FHD) resolution is 1920×1080, and the Ultra High Definition (UHD) resolution is 3840x2160, or even higher resolution display.

[0003] Taking 3840×2160 as an example, the number of data lines in the display panel includes 3840×3=11520, where "3840" represents the number of pixels in a row, and "3" represents the number of sub-pixels (red sub-pixel R, green sub-pixel G and blue sub-pixel B) included in a pixel. Taking the output channel number of a source driver circuit (Source Diver IC, referred to as SDIC) as 1920 as an example, 6 SDICs are required to meet the driving of each sub-pixel in the entire display panel. However, in the actual operation of the display panel, the simultaneous driving of 6 SDICs will bring many adverse effects such as high product cost, complex process preparation process, and difficulty in achieving UHD resolution of small-size display panels. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a display panel and a display device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a display panel, comprising a base substrate, a plurality of source driving circuits arranged on the base substrate, a switch circuit arranged corresponding to each of the source driving circuits, and at least two signal transmission lines; the source driving circuit comprises at least four level conversion sub-circuits and a driving sub-circuit; the level conversion sub-circuit comprises a first control terminal, a first input terminal and a first output terminal; the switch circuit comprises at least two second control terminals, a second input terminal and at least two second output terminals;

[0006] The at least four level conversion sub-circuits include at least two effective level conversion sub-circuits;

[0007] For any one of the signal transmission lines, it is electrically connected to the first output end of at least one of the effective level conversion sub-circuits in each of the source driving circuits; different signal transmission lines are electrically connected to different effective level conversion sub-circuits;

[0008] One of the signal transmission lines is electrically connected to one of the second control terminals of each of the switch circuits, and different signal transmission lines are electrically connected to different second control terminals;

[0009] The effective level conversion sub-circuit is configured to adjust the first signal received by the first input terminal to a second signal in response to the enable signal input by the first control terminal, and output the second signal through the first output terminal;

[0010] The driving sub-circuit is configured to output a data signal;

[0011] The switch circuit is configured to output the data signal received by the second input terminal through the second output terminal in response to a second signal input by the second control terminal.

[0012] In some embodiments, the switch circuit includes M switch transistors; M is an integer greater than or equal to 2; the number of the switch transistors is the same as the number of the signal transmission lines;

[0013] For the switch circuit, one switch transistor is electrically connected to one signal transmission line, and different switch transistors are electrically connected to different signal transmission lines.

[0014] In some embodiments, the switch circuit includes a first switch transistor and a second switch transistor; the signal transmission line includes a first transmission line and a second transmission line; the display panel further includes a plurality of data lines;

[0015] The first electrode of the first switch transistor is electrically connected to the second input terminal, the second electrode is electrically connected to one of the data lines, and the control electrode is electrically connected to the first transmission line;

[0016] The first electrode of the second switch transistor is electrically connected to the second input terminal, the second electrode is electrically connected to another data line, and the control electrode is electrically connected to the second transmission line.

[0017] In some embodiments, the orthographic projection of the switch circuit on the substrate is located between the orthographic projection of the source driver circuit on the substrate and the orthographic projection of the signal transmission line on the substrate;

[0018] A plurality of said source driving circuits are arranged side by side along a first direction; the extension direction of said signal transmission line is the first direction; said source driving circuit comprises four level conversion sub-circuits, which are divided into two groups of sub-circuit groups, each of said sub-circuit groups comprises two level conversion sub-circuits;

[0019] The orthographic projections of the two groups of sub-circuit groups on the base substrate are respectively located on two opposite sides of the orthographic projection of the driving sub-circuit on the base substrate in the first direction.

[0020] In some embodiments, for any of the source driver circuits, the level conversion sub-circuits in at least one group of the sub-circuit groups are all the effective level conversion sub-circuits;

[0021] The effective level conversion sub-circuits in the same sub-circuit group are electrically connected to different signal transmission lines.

[0022] In some embodiments, for any of the source driver circuits, the two sub-circuit groups include a first sub-circuit group and a second sub-circuit group;

[0023] The level conversion sub-circuits in the first sub-circuit group are all the effective level conversion sub-circuits;

[0024] The level conversion sub-circuits in the second sub-circuit group are all invalid level conversion sub-circuits.

[0025] In some embodiments, for any of the source driver circuits, the level conversion sub-circuits in the two sub-circuit groups are both effective level conversion sub-circuits.

[0026] In some embodiments, for a portion of the source driver circuits, the level conversion sub-circuits in one group of the sub-circuit groups are all the effective level conversion sub-circuits; for another portion of the source driver circuits, the level conversion sub-circuits in two groups of the sub-circuit groups are all the effective level conversion sub-circuits;

[0027] The effective level conversion sub-circuits in the same sub-circuit group are electrically connected to different signal transmission lines.

[0028] In some embodiments, the source driving circuit includes N, where N is an integer greater than or equal to 2; the two groups of sub-circuit groups include a first sub-circuit group and a second sub-circuit group;

[0029] For the i-th source driving circuit, the level conversion sub-circuits in the first sub-circuit group are all valid level conversion sub-circuits; the level conversion sub-circuits in the second sub-circuit group are all invalid level conversion sub-circuits; the orthographic projection of the first sub-circuit group on the substrate is located on the side of the orthographic projection of the second sub-circuit group on the substrate, away from the i+1-th source driving circuit; wherein i is an odd number between 1 and (N-1);

[0030] For the (i+1)th source driving circuit, the level conversion sub-circuits in the first sub-circuit group and the second sub-circuit group are both the effective level conversion sub-circuits;

[0031] When N is an odd number, for the Nth source driver circuit, the level conversion sub-circuits in the first sub-circuit group are all the invalid level conversion sub-circuits; and the level conversion sub-circuits in the second sub-circuit group are all the valid level conversion sub-circuits.

[0032] In some embodiments, the display panel further includes signal leads arranged in one-to-one correspondence with the first output terminals; the first output terminal is electrically connected to one of the signal transmission lines through the corresponding signal lead;

[0033] The orthographic projection of the signal lead on the base substrate is located at one of two opposite sides of the orthographic projection of the switch circuit on the base substrate in the first direction and does not overlap with the orthographic projection of the switch circuit on the base substrate.

[0034] In some embodiments, the level conversion subcircuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first amplifier, and a second amplifier;

[0035] The first transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the first node, and a control electrode electrically connected to the first control terminal;

[0036] The first electrode of the second transistor is electrically connected to the second node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the first node;

[0037] The first electrode of the third transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth node;

[0038] The first electrode of the fourth transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the third node;

[0039] The first electrode of the fifth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the output terminal of the first amplifier;

[0040] An input terminal of the first amplifier is electrically connected to the first node;

[0041] The input terminal of the second amplifier is electrically connected to the second node, and the output terminal of the second amplifier is electrically connected to the first output terminal.

[0042] In some embodiments, the display panel further comprises a timing control circuit; the timing control circuit comprises a third output terminal, and the first input terminal of each of the effective level conversion sub-circuits is electrically connected to the third output terminal;

[0043] The timing control circuit is configured to output the first signal through the third output terminal.

[0044] In some embodiments, the timing control circuit further includes at least one fourth output terminal; the fourth output terminal is electrically connected to the first control terminal of the effective level conversion sub-circuit;

[0045] The timing control circuit is further configured to output the enable signal through the fourth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

[0046] In some embodiments, the source driving circuit includes W, where W is an integer greater than or equal to 3; the two groups of sub-circuit groups include a first sub-circuit group and a second sub-circuit group; the level conversion sub-circuits in the first sub-circuit group and the second sub-circuit group are both the effective level conversion sub-circuits;

[0047] The fourth output terminals include four; the signal transmission line includes a first transmission line and a second transmission line;

[0048] For the effective level conversion sub-circuit electrically connected to the first transmission line, one of the first control terminals in the first sub-circuit group in the first source driver circuit and one of the first control terminals in the second sub-circuit group in the Nth source driver circuit are both electrically connected to the first fourth output terminal;

[0049] For the effective level conversion subcircuit electrically connected to the first transmission line, one of the first control terminals in the second subcircuit group in the first source driver circuit, one of the first control terminals in the first subcircuit group in the Nth source driver circuit, and two of the first control terminals in the kth source driver circuit are all electrically connected to the second fourth output terminal, where k is an integer between 2 and (N-1);

[0050] For the effective level conversion sub-circuit electrically connected to the second transmission line, another first control terminal in the first sub-circuit group in the first source driving circuit and another first control terminal in the second sub-circuit group in the Nth source driving circuit are both electrically connected to the third fourth output terminal;

[0051] For the effective level conversion sub-circuit electrically connected to the second transmission line, another first control terminal in the second sub-circuit group in the 1st source driving circuit, another first control terminal in the first sub-circuit group in the Nth source driving circuit, and another two first control terminals in the kth source driving circuit are all electrically connected to the 4th fourth output terminal.

[0052] In some embodiments, the fourth output terminal is connected to the first control terminal in a one-to-one correspondence.

[0053] In some embodiments, the source driving circuit includes four effective level conversion sub-circuits; the fourth output terminal includes four; the signal transmission line includes a first transmission line and a second transmission line;

[0054] For the effective level conversion subcircuit electrically connected to the first transmission line, one first control terminal in each of the source driving circuits is electrically connected to the first fourth output terminal; another first control terminal in each of the source driving circuits is electrically connected to the second fourth output terminal;

[0055] For the effective level conversion sub-circuit electrically connected to the second transmission line, a first control terminal in each of the source driving circuits is electrically connected to the third fourth output terminal; another first control terminal in each of the source driving circuits is electrically connected to the fourth fourth output terminal.

[0056] In some embodiments, the display panel further comprises a main control circuit; the main control circuit comprises a fifth output terminal, and the first control terminal of each of the effective level conversion sub-circuits is electrically connected to the fifth output terminal;

[0057] The main control circuit is configured to output the enable signal through the fifth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

[0058] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising a display panel as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 The schematic diagram of the circuit structure of a switch circuit divided into two parts;

[0060] Figure 2 is a schematic diagram of a display panel;

[0061] Figure 3 for Figure 2 A waveform diagram of a second signal at a dotted line position of a structural test;

[0062] Figure 4 A schematic diagram of a display panel provided in an embodiment of the present disclosure;

[0063] Figure 5 A schematic diagram of the direction of each signal in the circuit provided by the embodiment of the present disclosure;

[0064] Figure 6 A schematic diagram of a specific structure of a switch circuit provided in an embodiment of the present disclosure;

[0065] Figure 7 A schematic diagram of a display driving circuit provided by an embodiment of the present disclosure;

[0066] Figure 8 A schematic diagram of the position distribution of the level conversion sub-circuit provided in the embodiment of the present disclosure in the source driving circuit;

[0067] Fig. 9 A schematic diagram of the position distribution of an effective level conversion sub-circuit when three source driving circuits are provided in an embodiment of the present disclosure;

[0068] Fig.10 A schematic diagram of the position distribution of another effective level conversion sub-circuit when three source driving circuits are provided in an embodiment of the present disclosure;

[0069] Fig.11 for Fig.10 A waveform diagram of a second signal at a dotted line position of a structural test;

[0070] Fig.12 A schematic diagram of the position distribution of another effective level conversion sub-circuit when three source driving circuits are provided in an embodiment of the present disclosure;

[0071] Fig.13 A specific circuit structure diagram of a level conversion sub-circuit provided in an embodiment of the present disclosure;

[0072] Fig.14 A schematic diagram of electrical connection between a timing control circuit and a first input terminal of an effective level conversion sub-circuit provided in an embodiment of the present disclosure;

[0073] Figure 15a to Figure 15d A schematic diagram of electrical connection between a timing control circuit and a first control terminal of an effective level conversion sub-circuit provided in an embodiment of the present disclosure;

[0074] Fig.16 A schematic diagram of electrical connection between another timing control circuit and a first control terminal of an effective level conversion sub-circuit provided in an embodiment of the present disclosure;

[0075] Fig.17 A schematic diagram of electrical connection between another timing control circuit and a first control terminal of an effective level conversion sub-circuit provided in an embodiment of the present disclosure;

[0076] Fig.18 A schematic diagram of electrical connection between another timing control circuit and a first control terminal of an effective level conversion sub-circuit provided in an embodiment of the present disclosure;

[0077] Fig.19 A schematic diagram of the electrical connection between a sub-pixel of a display panel and a source driving circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0079] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0080] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0081] Taking the ultra-high-definition UHD resolution of 3840×2160 as an example, the display panel needs to integrate 6 SDICs at the same time to meet the driving of each sub-pixel in the entire display panel. However, in the actual working process of the display panel, 6 SDICs seriously increase the cost of the product, such as the cost of various materials, parts and raw materials required for the product or project; at the same time, the more SDICs, the more bonding processes, and the greater the loss of factory yield; at the same time, for small-sized display panels, such as 14-inch and 13.3-inch and smaller display panels, the lower frame space cannot accommodate 6 SDICs, making it difficult to achieve UHD resolution for such sizes.

[0082] like Figure 1 As shown, a one-to-two design of a switch circuit (MUX) 2 can be adopted to divide an output channel of a source driver circuit (SDIC) 1 into two branches, which are electrically connected to different data lines in the display panel (such as data line Data1 and data line Data2), thereby reducing the number of source driver circuits 1 by half. Taking the ultra-high-definition UHD resolution of 3840×2160 as an example, only three source driver circuits 1 are required to meet the driving conditions, thereby reducing product costs and making the circuit structure of the display panel simpler, which is convenient for small-size display panels to achieve ultra-high-definition UHD resolution.

[0083] like Figure 2 As shown, it is a schematic diagram of a display panel, which includes Q source driving circuits 1, a switching circuit 2 corresponding to each source driving circuit 1, and two signal transmission lines 3; the two signal transmission lines 3 are respectively recorded as a first transmission line 31 and a second transmission line 32; the source driving circuit 1 includes four level conversion sub-circuits 11 and a driving sub-circuit 12; the level conversion sub-circuit 11 includes a first control terminal 11a, a first input terminal 11b and at least one first output terminal 11c; the switching circuit 2 includes at least one second control terminal 2a, a second input terminal 2b and at least one second output terminal 2c.

[0084] The four level conversion sub-circuits 11 in the first source driving circuit 1 and the Qth source driving circuit 1 are divided into two sub-circuit groups, which are respectively arranged on the left and right sides of the driving sub-circuit 12, each of which includes two level conversion sub-circuits 11, wherein the level conversion sub-circuits 11 in one sub-circuit group are valid level conversion sub-circuits 110, and the level conversion sub-circuits 11 in the other sub-circuit group are invalid level conversion sub-circuits 111; for example, the level conversion sub-circuit 11 close to the left is the valid level conversion sub-circuit 110, and the level conversion sub-circuit 11 close to the right is the invalid level conversion sub-circuit 111. Q is an integer greater than or equal to 2. The level conversion sub-circuits 11 in the 2nd to (Q-1)th source driving circuits 1 are all invalid level conversion sub-circuits 111. The so-called "valid level conversion subcircuit 110" refers to a level conversion subcircuit 11 that is electrically connected to the switch circuit 2 and is used to transmit signals to the switch circuit 2; the so-called "invalid level conversion subcircuit 111" refers to a level conversion subcircuit 11 that is not electrically connected to the switch circuit 2, and each port of the invalid level conversion subcircuit 111, such as the first control terminal 11a, the first input terminal 11b and the first output terminal 11c, are in a floating state or a grounded state. In simple terms, only the level conversion subcircuit 11 in the left subcircuit group of the leftmost source driver circuit 1 and the level conversion subcircuit 11 in the right subcircuit group of the rightmost source driver circuit 1 are valid in the above-mentioned display panel.

[0085] It should be noted that in the actual production process of SDIC, it is mass production, so the circuit structure of each source driver circuit 1 is the same, regardless of whether it is valid or invalid. Only in the subsequent preparation or assembly process of the display panel will the specific valid level conversion sub-circuit 11 and invalid level conversion sub-circuit 11 be defined.

[0086] The first output terminal 11c of an effective level conversion sub-circuit 110 in the first source driving circuit 1 and the first output terminal 11c of an effective level conversion sub-circuit 110 in the Qth source driving circuit 1 are both electrically connected to the first transmission line 31; the first output terminal 11c of another effective level conversion sub-circuit 110 in the first source driving circuit 1 and the first output terminal 11c of another effective level conversion sub-circuit 110 in the Qth source driving circuit 1 are both electrically connected to the second transmission line 32. A second control terminal 2a in each switch circuit 2 is electrically connected to the first transmission line 31; another second control terminal 2a in each switch circuit 2 is electrically connected to the second transmission line 32. The effective level conversion sub-circuit 110 is configured to respond to the enable signal EN input by the first control terminal 11a, adjust the first signal V1 received by the first input terminal 11b to the second signal V2, and output it through the first output terminal 11c. The driving sub-circuit 12 is configured to output the data signal D0. The switch circuit 2 is configured to output the data signal D0 received by the second input terminal 2b through the second output terminal 2c in response to the second signal V2 inputted by the second control terminal 2a.

[0087] Since the middle source driving circuits 1 (the 2nd to (Q-1)th source driving circuits 1) are not electrically connected to the signal transmission line 3, the middle switch circuits 2 (the 2nd to (Q-1)th switch circuits 2) are switched on and off by receiving the second signal V2 provided by the effective level conversion sub-circuit 110 in the 1st source driving circuit 1 and the Qth source driving circuit 1, as shown in FIG. Figure 2 As shown, the current flows gradually from both sides to the middle.

[0088] Under low load (or high power consumption), the above display panel has no adverse effect on the final display image. However, under high load (or high power consumption), the previous display panel will cause the display effect in the middle of the display panel to be dark, affecting the quality of the display image. This is because under high load, at the middle position of the signal transmission line 3, the rising edge or falling edge of the waveform of the second signal V2 is severely deformed, that is, the delay time of the jump is long, such as Figure 3 As shown, the measurement Figure 2 The waveform of the second signal V2 at the dotted line position has a jump delay time of 830 nanoseconds (ns), which causes insufficient charging of the pixel driving circuit data signal D0 (data signal) in the middle area of ​​the display panel, resulting in a dark display effect in the middle of the display panel under high load.

[0089] In view of this, an embodiment of the present disclosure provides a display panel that adopts a one-to-many design of the switch circuit 2 to simplify the display panel and reduce costs; at the same time, it solves the problem of dark display effect in the middle of the display panel under high load.

[0090] like Figure 4 As shown, the display panel includes a base substrate, a plurality of source driving circuits 1 arranged on the base substrate, a switch circuit 2 arranged corresponding to each source driving circuit 1, and at least two signal transmission lines 3. The display panel has a display area AA and a peripheral area BB surrounding the display area AA. Optionally, the plurality of source driving circuits 1, the switch circuit 2 arranged corresponding to each source driving circuit 1, and the at least two signal transmission lines 3 are all located on one side of the peripheral area BB, and the orthographic projection of the switch circuit 2 on the base substrate is located between the orthographic projection of the source driving circuit 1 on the base substrate and the orthographic projection of the signal transmission line 3 on the base substrate.

[0091] The source driving circuit 1 includes at least four level conversion sub-circuits 11 and a driving sub-circuit 12; the level conversion sub-circuit 11 includes a first control terminal 11a, a first input terminal 11b and a first output terminal 11c; the switch circuit 2 includes at least two second control terminals 2a, a second input terminal 2b and at least two second output terminals 2c. The at least four level conversion sub-circuits 11 include at least two effective level conversion sub-circuits 110; for any signal transmission line 3, it is electrically connected to the first output terminal 11c of at least one effective level conversion sub-circuit 110 in each source driving circuit 1; different signal transmission lines 3 are electrically connected to different effective level conversion sub-circuits 110; a signal transmission line 3 is electrically connected to one of the second control terminals 2a of each switch circuit 2, and different signal transmission lines 3 are electrically connected to different second control terminals 2a.

[0092] For the source driving circuit 1 and the switch circuit 2 corresponding to the source driving circuit 1, the first output terminal 11c of the effective level conversion sub-circuit 110 is electrically connected to a second control terminal 2a in the switch circuit 2 through a signal transmission line 3, and provides a second signal V2 to the second control terminal 2a to control the switch circuit 2 to open and transmit the data signal D0 to the outside. A second output terminal 2c is electrically connected to a data line (not shown in the figure) for providing the data signal D0 to the data line.

[0093] Each source driving circuit 1 includes at least four level conversion sub-circuits 11 . For example, three source driving circuits 1 include at least twelve level conversion sub-circuits 11 .

[0094] Alternatively, if Figure 4 As shown, the source driving circuit 1 includes four level conversion sub-circuits 11; if three source driving circuits 1 are provided, a total of twelve level conversion sub-circuits 11 are included. The four level conversion sub-circuits 11 in each source driving circuit 1 include at least two effective level conversion sub-circuits 110, for example, two or four. Figure 4 Let's take two examples to illustrate.

[0095] Optionally, the number of the second control terminals 2 a in the switch circuit 2 is the same as the number of the signal transmission lines 3 .

[0096] Alternatively, if Figure 4 As shown, the display panel includes two signal transmission lines 3, which are respectively recorded as a first transmission line 31 and a second transmission line 32; wherein the first transmission line 31 is electrically connected to the first output terminal 11c of an effective level conversion subcircuit 110 in each source driving circuit 1; the second transmission line 32 is electrically connected to the first output terminal 11c of another effective level conversion subcircuit 110 in each source driving circuit 1. The switch circuit 2 includes two second control terminals 2a; the first transmission line 31 is electrically connected to one second control terminal 2a in each switch circuit 2; and the second transmission line 31 is electrically connected to the other second control terminal 2a in each switch circuit 2.

[0097] like Figure 5 As shown, the effective level conversion sub-circuit 110 is configured to respond to the enable signal EN input to the first control terminal 11a, adjust the first signal V1 received by the first input terminal 11b to the second signal V2, and output it through the first output terminal 11c; the driving sub-circuit 12 is configured to output the data signal D0; the switch circuit 2 is configured to respond to the second signal V2 input to the second control terminal 2a, and output the data signal D0 received by the second input terminal 2b through the second output terminal 2c.

[0098] like Figure 5 As shown, the driving subcircuit 12 includes a data input terminal 12a and a data output terminal 12b; the data input terminal 12a receives the image data, and after the logic processing inside the driving subcircuit 12, outputs the data signal D0 through the data output terminal 12b, and the data signal D0 represents the image data to be displayed on the display panel. The data output terminal 12b is electrically connected to the second input terminal 2b of the switch circuit 2.

[0099] The first control terminal 11a receives an enable signal EN, and the first input terminal 11b receives a first signal V1. The effective level conversion sub-circuit 110 responds to the enable signal EN and starts to adjust the received first signal V1, such as pulling it up or pulling it down, to obtain a second signal V2. The first output terminal 11c is electrically connected to the signal transmission line 3, and the second signal V2 is output through the first output terminal 11c and transmitted to the second control terminal 2a of the switch circuit 2 through the signal transmission line 3.

[0100] The second control terminal 2a receives the second signal V2, and the second input terminal 2b receives the data signal D0; the switch circuit 2 responds to the second signal V2, closes the internal switch, and outputs the data signal D0 through the second output terminal 2c. The second output terminal 2c is electrically connected to the data line in the display panel to provide the data signal D0 to the data line, thereby driving the sub-pixels of the display panel to display the picture.

[0101] In the disclosed embodiment, each source driver circuit 1 includes at least four level conversion sub-circuits 11, for example, three source driver circuits 1 include at least twelve level conversion sub-circuits 11. At least two effective level conversion sub-circuits 110 are included in at least four level conversion sub-circuits 11, which means that at least six effective level conversion sub-circuits 110 are included in three source driver circuits 1, or even more. Any signal transmission line 3 is electrically connected to at least one effective level conversion sub-circuit 110 in each source driving circuit 1, and different signal transmission lines 3 are electrically connected to different effective level conversion sub-circuits 110. Since multiple source driving circuits 1 are arranged side by side along the first direction X, the effective level conversion sub-circuits 110 on multiple source driving circuits 1 are arranged side by side along the first direction X, and the first output terminal 11c arranged thereon is electrically connected to the signal transmission line 3 nearby, so that the access points of different second signals V2 connected to the signal transmission line 3 are different, and each access point has a second control terminal 2a most adjacent to it, that is, the second control terminal 2a on the switching circuit 2 corresponding to the source driving circuit 1 connected to the access point, and the second signal V2 introduced from the access point will enter the second control terminal 2a most adjacent to it as quickly as possible. In the disclosed embodiment, each second control terminal 2a is provided with a corresponding and most adjacent access point (or an effective level conversion subcircuit 110), so as to quickly provide the second control terminal 2a with a second signal V2, so that the switch in the switch circuit 2 is quickly closed and turned on, so as to quickly output the data signal D0 to the data line on the display panel through the second output terminal 2c, thereby greatly reducing the waveform delay of the second signal V2 at the middle position of the signal transmission line 3, effectively solving the problem of insufficient charging of the data signal D0 (data signal) of the pixel driving circuit, and further eliminating the undesirable phenomenon of dark display effect of the display panel under high load.

[0102] Compared with Figure 2 The technical solution shown is that only the level conversion sub-circuit 11 in the left group of sub-circuit groups of the leftmost source driving circuit 1 and the level conversion sub-circuit 11 in the right group of sub-circuit groups of the rightmost source driving circuit 1 are effective. In the embodiment of the present disclosure, each source driving circuit 1 includes at least one effective level conversion sub-circuit 110, and the signal transmission line 3 is electrically connected to a first output terminal 11c in each effective level conversion sub-circuit 110, so that the access points of the signal transmission line 3 are expanded to at least n, where n is the number of source driving circuits 1, thereby increasing the transmission speed of the second signal V2 on the signal transmission line 3, thereby shortening the time for each second control terminal 2a to receive the second signal V2, greatly reducing the waveform delay (delay) phenomenon of the second signal V2 in the middle position of the signal transmission line 3, and solving the problem of dark display effect in the middle of the display panel under high load.

[0103] In some embodiments, Figure 6 As shown, the switch circuit 2 includes M switch transistors T0; the signal transmission lines 3 include M; wherein M is an integer greater than or equal to 2; for the switch circuit 2, one switch transistor T0 is electrically connected to one signal transmission line 3, and different switch transistors T0 are electrically connected to different signal transmission lines 3. Exemplarily, the switch circuit 2 adopts a one-to-two design scheme, in which case M can be 2, the switch circuit 2 includes 2 switch transistors T0; the signal transmission lines 3 include 2, which are respectively recorded as a first transmission line 31 and a second transmission line 32.

[0104] The display panel further includes a plurality of data lines Data. The data line Data is located in the display area AA and extends to the peripheral area BB, and is electrically connected to the second electrode of the switch transistor T0 for transmitting a data signal D0 to the pixel driving circuit to drive the sub-pixel to display a picture.

[0105] In this embodiment, a signal transmission line 3 corresponding to each data signal D0 in the switching circuit 2 (that is, each switching transistor T0) is set to improve the stability of the second signal V2 on the signal transmission line 3 under high load, and ensure that each switching transistor T0 responds to the second signal V2 received by each switching transistor and is turned on synchronously.

[0106] Optionally, the switch circuit 2 includes a plurality of switch transistors T0 , and the plurality of switch transistors T0 are arranged side by side along the first direction X.

[0107] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. Among them, N-type thin film transistors refer to N-type ion doping in the active layer of the thin film transistor; P-type thin film transistors refer to P-type ion doping in the active layer of the thin film transistor. The working level signal of the N-type thin film transistor is a high level signal; the working level signal of the P-type thin film transistor is a low level signal. Taking the switching transistor T0 as a P-type thin film transistor as an example, the effective level conversion subcircuit 110 pulls the first signal V1 up to the second signal V2, wherein the first signal V1 is a low level signal and the second signal V2 is a high level signal. Afterwards, the switching transistor T0 is turned on in response to the high level signal and outputs the data signal D0 through the second output terminal 2c. Taking the switch transistor T0 as an N-type thin film transistor as an example, the effective level conversion sub-circuit 110 pulls the first signal V1 down to the second signal V2, wherein the first signal V1 is a high level signal and the second signal V2 is a low level signal. Afterwards, the switch transistor T0 is turned on in response to the low level signal and outputs the data signal D0 through the second output terminal 2c. In the following embodiments, the switch transistor T0 is described as a P-type thin film transistor as an example, but the present disclosure is not limited to a P-type thin film transistor, and may also be an N-type thin film transistor.

[0108] In some embodiments, Figure 7 As shown, the switch circuit 2 includes a first switch transistor T01 and a second switch transistor T02; the signal transmission line 3 includes two, respectively denoted as a first transmission line 31 and a second transmission line 32; wherein the first electrode of the first switch transistor T01 is electrically connected to the second input terminal 2b, the second electrode is electrically connected to a data line Data1, and the control electrode is electrically connected to a signal transmission line 3 (such as the first transmission line 31); the first electrode of the second switch transistor T02 is electrically connected to the second input terminal 2b, the second electrode is electrically connected to another data line Data2, and the control electrode is electrically connected to another signal transmission line 3 (such as the second transmission line 32). Here, the first electrode of the first switch transistor T01 and the second electrode of the second switch transistor T02 are connected in series.

[0109] The first transmission line 31 is electrically connected to the control electrode of the first switch transistor T01; the second transmission line 32 is electrically connected to the control electrode of the second switch transistor T02; the first switch transistor T01 responds to the second signal V2 provided by the first transmission line 31, the first electrode and the second electrode are turned on, and the data signal D0 is output through the second output terminal 2c. The second switch transistor T02 responds to the second signal V2 provided by the second transmission line 32, the first electrode and the second electrode are turned on, and the data signal D0 is output through another second output terminal 2c.

[0110] In addition, in addition to the one-to-two design scheme described above, the switch circuit 2 can also adjust the number of switch transistors T0 in the switch circuit 2 according to the actual resolution of the display panel. For example, the switch circuit 2 can also adopt a one-to-three, one-to-four, one-to-five, or one-to-six design scheme, and the principle is the same as the one-to-two design scheme described above, and the embodiments of the present disclosure will not list them one by one.

[0111] In some embodiments, Figure 8 As shown, a plurality of source driving circuits 1 are arranged side by side along a first direction X; the extension direction of the signal transmission line 3 is the first direction X; the source driving circuit 1 includes four level conversion sub-circuits 11, which are divided into two groups of sub-circuit groups 100, and each group of sub-circuit groups 100 includes two level conversion sub-circuits 11; the positive projections of the two groups of sub-circuit groups 100 on the substrate substrate are respectively located on two opposite sides of the positive projection of the driving sub-circuit 12 on the substrate substrate in the first direction X, so as to facilitate the subsequent signal lead 4 to bypass the switch circuit 2 and be electrically connected to the signal transmission line 3, so as to avoid generating unnecessary parasitic capacitance and affecting signal transmission.

[0112] Taking three source driver circuits 1 as an example, if only one level conversion sub-circuit 11 in one sub-circuit group 100 in each source driver circuit 1 is a valid level conversion sub-circuit 110, then the three source driver circuits 1 include three valid sub-circuit groups 100. If the level conversion sub-circuit 11 in two sub-circuit groups 100 in each source driver circuit 1 are both valid level conversion sub-circuit 110, then the three source driver circuits 1 include six valid sub-circuit groups 100. If the level conversion sub-circuit 11 in two sub-circuit groups 100 in one source driver circuit 1 are both valid level conversion sub-circuit 110, the level conversion sub-circuit 11 in one sub-circuit group 100 in one source driver circuit 1 is a valid level conversion sub-circuit 110, and the level conversion sub-circuit 11 in one sub-circuit group 100 in the last source driver circuit 1 is a valid level conversion sub-circuit 110, then the three source driver circuits 1 include four valid sub-circuit groups 100. If the level conversion sub-circuits 11 in two groups of sub-circuit groups 100 in two source driver circuits 1 are both valid level conversion sub-circuits 110, and the level conversion sub-circuit 11 in one group of sub-circuit groups 100 in one source driver circuit 1 is a valid level conversion sub-circuit 110, then the three source driver circuits 1 include five valid sub-circuit groups 100.

[0113] In some embodiments, Fig. 9 or Fig.10 As shown, for any source driving circuit 1 , the level conversion sub-circuits 11 in at least one group of sub-circuit groups 100 are all effective level conversion sub-circuits 110 ; the effective level conversion sub-circuits 110 in the same group of sub-circuit groups 100 are electrically connected to different signal transmission lines 3 .

[0114] In some embodiments, Fig. 9 As shown, for any source driver circuit 1, the two sub-circuit groups 100 include a first sub-circuit group 1001 and a second sub-circuit group 1002; the level conversion sub-circuits 11 in the first sub-circuit group 1001 are all valid level conversion sub-circuits 110; and the level conversion sub-circuits 11 in the second sub-circuit group 1002 are all invalid level conversion sub-circuits 111. Fig. 9 In the figure, the first sub-circuit group 1001 is on the left, and the second sub-circuit group is on the right. Of course, the first sub-circuit group 1001 can also be on the right, and the second sub-circuit group can be on the left.

[0115] The positive projection of the first sub-circuit group 1001 on the substrate is located on one of the two opposite sides of the positive projection of the driving sub-circuit 12 on the substrate in the first direction X, so as to bypass the switch circuit 2 and be electrically connected to the signal transmission line 3 to avoid generating unnecessary parasitic capacitance and affecting signal transmission.

[0116] Alternatively, if Fig. 9As shown, the display panel also includes a signal lead 4 arranged in a one-to-one correspondence with the first output terminal 11c; optionally, the extension direction of the signal lead 4 is the second direction Y, and the first direction X and the second direction Y are arranged crosswise, for example, the first direction X is perpendicular to the second direction Y. The first output terminal 11c is electrically connected to the signal transmission line 3 through the corresponding signal lead 4; the connection node between the signal lead 4 and the signal transmission line 3 is the first input node N1; the connection node between the second control terminal 2a and the signal transmission line 3 is the second input node N2. There is a second input node N2 between two adjacent first input nodes N1 on the signal transmission line 3. There is a first input node N1 between two adjacent second input nodes N2 on the signal transmission line 3.

[0117] Optionally, for the same signal transmission line 3 , the distances between adjacent first input nodes N1 are equal; and the distances between adjacent second input nodes N2 are equal.

[0118] In this embodiment, the first input nodes N1 on the left and right sides of the second input node N2 introduce the second signal V2, and transmit it in opposite directions to the second input node N2 located in the middle position at the same time, so that the second signals V2 introduced by the two first input nodes N1 can be quickly converged at the second input node N2, thereby quickly providing the second signal V2 to the second control terminal 2a corresponding to the second input node N2, so that the switching transistor T0 is quickly closed and turned on, so as to quickly output the data signal D0 to the data line on the display panel through the second output terminal 2c, which greatly reduces the waveform delay of the second signal V2 on the signal transmission line 3, effectively solves the problem of insufficient charging of the data signal D0 (data signal) of the pixel driving circuit in the display panel, and further eliminates the undesirable phenomenon of dark display effect of the display panel under high load.

[0119] In some embodiments, Fig.10 As shown, for any source driving circuit 1 , the level conversion sub-circuits 11 in the two sub-circuit groups 100 are both effective level conversion sub-circuits 110 .

[0120] The orthographic projections of the first sub-circuit group 1001 and the second sub-circuit group 1002 on the substrate are located on two opposite sides of the orthographic projection of the driving sub-circuit 12 on the substrate in the first direction X, so as to bypass the switch circuit 2 and be electrically connected to the signal transmission line 3, thereby avoiding the generation of unnecessary parasitic capacitance and affecting signal transmission.

[0121] Alternatively, if Fig.10As shown, the display panel also includes a signal lead 4 arranged in one-to-one correspondence with the first output terminal 11c; the first output terminal 11c is electrically connected to the signal transmission line 3 through the corresponding signal lead 4; the connection node between the signal lead 4 and the signal transmission line 3 is the first input node N1; the connection node between the second control terminal 2a and the signal transmission line 3 is the second input node N2. The signal transmission line 3 includes a plurality of electrically connected sub-segments 30; the sub-segments 30 are arranged in one-to-one correspondence with the source driving circuit 1, and for any sub-segment 30, it includes two first input nodes N1, and a second input node N2 located between the two first input nodes N1. Specifically, for any sub-segment 30, it includes a first input node N1 connected to two effective level conversion sub-circuits 110 on the source driving circuit 1, and a second input node N2 connected to the switch circuit 2, and the second input node N2 is between the two first input nodes N1.

[0122] In this embodiment, the signal transmission line 3 includes a sub-segment 30 that is arranged in a one-to-one correspondence with the source driving circuit 1. The second input node N2 in the sub-segment 30 is located between the two first input nodes N1, and the distances to the two first input nodes N1 are approximately equal. The second signal V2 introduced from the first input node N1 will quickly enter the second input node N2 adjacent to it. For any sub-segment 30, the second signal V2 introduced from the two first input nodes N1 is simultaneously transmitted toward the second input node N2 located in the middle position, so that the second signals V2 introduced from the two first input nodes N1 quickly converge at the second input node N2, thereby quickly providing the second signal V2 to the second control terminal 2a corresponding to the second input node N2, so that the switching transistor T0 is quickly closed and turned on, so as to quickly output the data signal D0 to the data line on the display panel through the second output terminal 2c, which greatly reduces the waveform delay of the second signal V2 on the sub-segment 30. Fig.11 As shown, the measurement Fig.10 The waveform of the second signal V2 at the dotted line position has a jump delay time shortened to 340 nanoseconds (ns). Figure 2 The waveform of the second signal V2 at the dotted line position of the structure shown in the present disclosure greatly reduces the waveform delay of the second signal V2, effectively solves the problem of insufficient charging of the data signal D0 (data signal) of the pixel driving circuit in the display panel, and further eliminates the undesirable phenomenon of dark display effect of the display panel under high load.

[0123] In some embodiments, Fig.12As shown, for a part of the source driving circuits 1, the level conversion sub-circuits 11 in one group of sub-circuit groups 100 are all effective level conversion sub-circuits 110; for another part of the source driving circuits 1, the level conversion sub-circuits 11 in two groups of sub-circuit groups 100 are all effective level conversion sub-circuits 110. The effective level conversion sub-circuits 110 in the same group of sub-circuit groups 100 are electrically connected to different signal transmission lines 3 (i.e., the first transmission line 31 and the second transmission line 32).

[0124] Optionally, the source driving circuit 1 includes N source driving circuits, where N is an integer greater than or equal to 2. For example, N is 2, 3, 4, 5, 6, 7, 8, 9 or 10.

[0125] like Fig.12 As shown, the two groups of sub-circuit groups 100 include a first sub-circuit group 1001 and a second sub-circuit group 1002; for the i-th source driving circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 are all effective level conversion sub-circuits 110; the level conversion sub-circuits 11 in the second sub-circuit group 1002 are all invalid level conversion sub-circuits 111; the positive projection of the first sub-circuit group 1001 on the substrate substrate is located at the positive projection of the second sub-circuit group 1002 on the substrate substrate, away from the i+1-th source driving circuit 1 one side; wherein i is an odd number from 1 to (N-1); for the i+1th source driver circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 and the second sub-circuit group 1002 are both valid level conversion sub-circuits 110; when N is an odd number, for the Nth source driver circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 are both invalid level conversion sub-circuits 111; and the level conversion sub-circuits 11 in the second sub-circuit group 1002 are both valid level conversion sub-circuits 110.

[0126] Taking N as 3 as an example, for the first source driver circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 are all valid level conversion sub-circuits 110, and the level conversion sub-circuits 11 in the second sub-circuit group 1002 are all invalid level conversion sub-circuits 111; for the second source driver circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 and the second sub-circuit group 1002 are all valid level conversion sub-circuits 110; for the third source driver circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 are all invalid level conversion sub-circuits 110, and the level conversion sub-circuits 11 in the second sub-circuit group 1002 are all valid level conversion sub-circuits 111.

[0127] In this embodiment, by setting part of the level conversion sub-circuits 11 as effective level conversion sub-circuits 110, and the remaining part of the level conversion sub-circuits 11 still as invalid effective level conversion sub-circuits 111, the waveform of the second signal under high power consumption can be improved to a certain extent, and at the same time, the power consumption of the effective level conversion sub-circuits 110 is not increased when a large number of effective level conversion sub-circuits 110 are introduced, that is, the power consumption of the remaining part of the level conversion sub-circuits is saved.

[0128] Alternatively, if Fig.12 As shown, the display panel further includes a signal lead 4 arranged in one-to-one correspondence with the first output terminal 11c; the first output terminal 11c is electrically connected to the signal transmission line 3 through the corresponding signal lead 4; the connection node between the signal lead 4 and the signal transmission line 3 is the first input node N1; the connection node between the second control terminal 2a and the signal transmission line 3 is the second input node N2. The first input node N1 connected to the effective level conversion subcircuit 110 of the first source driving circuit 1 on the signal transmission line 3 is located on the second input node N2 connected to the first switch circuit 2 on the signal transmission line 3, away from the first input node N1 connected to the effective level conversion subcircuit 110 of the second source driving circuit 1 on the signal transmission line 3. The second input node N2 connected to the second switch circuit 2 on the signal transmission line 3 is located between the two first input nodes N1 connected to the two effective level conversion subcircuits 110 of the second source driving circuit 1 on the signal transmission line 3. The first input node N1 on the signal transmission line 3 connected to the effective level conversion sub-circuit 110 of the third source driving circuit 1 is located on the second input node N2 on the signal transmission line 3 connected to the third switching circuit 2, away from the side of the first input node N1 on the signal transmission line 3 connected to the effective level conversion sub-circuit 110 of the second source driving circuit 1.

[0129] In this embodiment, the first input nodes N1 on the left and right sides of the second input node N2 introduce the second signal V2, and transmit it in opposite directions to the second input node N2 located in the middle position at the same time, so that the second signals V2 introduced by the two first input nodes N1 can be quickly converged at the second input node N2, thereby quickly providing the second signal V2 to the second control terminal 2a corresponding to the second input node N2, so that the switching transistor T0 is quickly closed and turned on, so as to quickly output the data signal D0 to the data line on the display panel through the second output terminal 2c, which greatly reduces the waveform delay of the second signal V2 on the sub-segment 30, effectively solves the problem of insufficient charging of the data signal D0 (data signal) of the pixel driving circuit in the display panel, and further eliminates the undesirable phenomenon of dark display effect of the display panel under high load.

[0130] In some embodiments, Figures 9 to 12As shown, the orthographic projection of the signal lead 4 on the substrate is located on one of the two opposite sides of the orthographic projection of the switch circuit 2 on the substrate in the first direction X, and does not overlap with the orthographic projection of the switch circuit 2 on the substrate, which can effectively avoid the switch circuit 2 and prevent the generation of parasitic capacitance between the signal lead 4 and the switch transistor T0 (active layer, control electrode, first electrode and second electrode), thereby affecting the transmission stability of the second signal V2.

[0131] In some embodiments, Fig.13 As shown, the level conversion sub-circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first amplifier U1 and a second amplifier U2. The first electrode of the first transistor M1 is electrically connected to the first input terminal 11b, the second electrode is electrically connected to the first node P1, and the control electrode is electrically connected to the first control terminal 11a; the first electrode of the second transistor M2 is electrically connected to the second node P2, the second electrode is electrically connected to the first power supply terminal VSS, and the control electrode is electrically connected to the first node P1; the first electrode of the third transistor M3 is electrically connected to the second power supply terminal VDD, the second electrode is electrically connected to the third node P3, and the control electrode is electrically connected to the fourth node P4; the first electrode of the fourth transistor M4 is electrically connected to the second power supply terminal VDD, the second electrode is electrically connected to the fourth node P4, and the control electrode is electrically connected to the third node P3; the first electrode of the fifth transistor M5 is electrically connected to the fourth node P4, the second electrode is electrically connected to the first power supply terminal VSS, and the control electrode is electrically connected to the output terminal of the first amplifier U1; the input terminal of the first amplifier U1 is electrically connected to the first node P1; the input terminal of the second amplifier U2 is electrically connected to the second node P2, and the output terminal is electrically connected to the first output terminal 11c.

[0132] The first transistor M1 is turned on in response to the enable signal EN, and writes the first signal V1 from the first input terminal 11b to the first node P. The first amplifier U1 is connected to the first reference voltage terminal, which is used to provide the first reference signal VGL, that is, a low-level signal, to the first amplifier U1. The first reference signal VGL is used to instruct the first amplifier U1 to pull down the first signal V1, for example, from 0V to -8V. The second amplifier U2 is connected to the second reference voltage terminal, which is used to provide the second reference signal VGH, that is, a high-level signal, to the second amplifier U2. The second reference signal VGH is used to instruct the second amplifier U2 to pull up the first signal V1, for example, from 0V to +8V.

[0133] In some embodiments, Fig.14 As shown, the display panel also includes a timing control circuit 5 (TCON); the timing control circuit 5 includes a third output terminal 5a, and the first input terminal 11b of each effective level conversion sub-circuit 110 is electrically connected to the third output terminal 5a; the timing control circuit 5 is configured to output the first signal V1 through the third output terminal 5a.

[0134] In some embodiments, Figure 15a to Figure 15d ,or Fig.16 As shown, the timing control circuit 5 also includes at least one fourth output terminal 5b; the fourth output terminal 5b is electrically connected to the first control terminal 11a of the effective level conversion sub-circuit 110; the timing control circuit 5 is also configured to output an enable signal EN through the fourth output terminal 5b to control whether the effective level conversion sub-circuit 110 outputs the second signal V2.

[0135] The level conversion sub-circuits 11 in the source driving circuit 1 are all effective level conversion sub-circuits 110. Optionally, in low power consumption mode, the timing control circuit 5 can control part of the effective level conversion sub-circuits 110 to pull up the first signal V1 to the second signal V2 and output it through the enable signal EN; at the same time, control another part of the effective level conversion sub-circuits 110 not to process the first signal V1 (that is, no output or output the first signal V1), or pull the first signal V1 to a lower level. Optionally, in high power consumption mode, the timing control circuit 5 can control all effective level conversion sub-circuits 110 to pull up the first signal V1 to the second signal V2 through the enable signal EN. Optionally, different power consumption modes can be customized, not limited to only low power consumption and high power consumption. In different power consumption modes, the timing control circuit 5 can analyze the complexity of the display screen, and according to the correspondence between the preset complexity and the power consumption mode, control at least part of the effective level conversion sub-circuit 110 through the enable signal EN to pull the first signal V1 up to the second signal V2, and the remaining effective level conversion sub-circuit 110 does not process the first signal V1, or pulls the first signal V1 to a lower level.

[0136] Exemplarily, the enable signal EN can be a square wave signal, wherein a low level is a valid level, controlling the effective level conversion subcircuit 110 to output the second signal V2, and a high level is an invalid level, controlling the effective level conversion subcircuit 110 to have no output, or to output the first signal V1, or to output a signal with a lower level than the first signal V1.

[0137] In this embodiment, the timing control circuit 5 controls whether the effective level conversion sub-circuit 110 outputs the second signal V2, thereby realizing dynamic adjustment of low power consumption and high power consumption. In the low power consumption mode, part of the effective level conversion sub-circuit 110 can be turned off, thereby saving the power consumption of the source driving circuit 1.

[0138] Alternatively, if Figure 15a to Figure 15dAs shown, the timing control circuit 5 includes a plurality of fourth output terminals 5b, the number of the fourth output terminals 5b is less than the number of the first control terminals 11a, and some of the fourth output terminals 5b are connected to a plurality of second control terminals 2a. The timing control circuit 5 can adapt to the high power consumption mode and the low power consumption mode by selecting some of the fourth output terminals 5b to output the enable signal EN of the valid level and selecting other fourth output terminals 5b to output the enable signal EN of the invalid level. The number of the fourth output terminals 5b is less than the number of the first control terminals 11a, which can save the occupation of the output terminals of the timing control circuit 5. Alternatively, a timing control circuit 5 with fewer output terminals is selected to save the cost of parts.

[0139] Specifically, the source driving circuit 1 includes W, where W is an integer greater than or equal to 3; the two sub-circuit groups 100 include a first sub-circuit group 1001 and a second sub-circuit group 1002; the level conversion sub-circuits 11 in the first sub-circuit group 1001 and the second sub-circuit group 1002 are both effective level conversion sub-circuits 110. Influenced by the limited interface of some timing control circuits 5, the fourth output terminal 5b includes four; the signal transmission line 3 includes a first transmission line 31 and a second transmission line 32.

[0140] like Fig.15a As shown, for the effective level conversion sub-circuit 110 electrically connected to the first transmission line 31, a first control terminal 11a in the first sub-circuit group 1001 in the first source driver circuit 1, and a first control terminal 11a in the second sub-circuit group 1002 in the Nth source driver circuit 1, are both electrically connected to the first fourth output terminal 5b1.

[0141] like Fig.15b As shown, for the effective level conversion sub-circuit 110 electrically connected to the first transmission line 31, a first control terminal 11a in the second sub-circuit group 1002 in the first source driving circuit 1, a first control terminal 11a in the first sub-circuit group 1001 in the Nth source driving circuit 1, and two first control terminals 11a in the kth source driving circuit 1 are all electrically connected to the second fourth output terminal 5b2. k is an integer between 2 and (N-1).

[0142] like Fig.15c As shown, for the effective level conversion sub-circuit 110 electrically connected to the second transmission line 32, another first control terminal 11a in the first sub-circuit group 1001 in the 1st source driver circuit 1, and another first control terminal 11a in the second sub-circuit group 1002 in the Nth source driver circuit 1, are both electrically connected to the third fourth output terminal 5b3.

[0143] like Fig.15dAs shown, for the effective level conversion sub-circuit 110 electrically connected to the second transmission line 32, another first control terminal 11a in the second sub-circuit group 1002 in the 1st source driver circuit 1, another first control terminal 11a in the first sub-circuit group 1001 in the Nth source driver circuit 1, and another two first control terminals 11a in the kth source driver circuit 1 are all electrically connected to the 4th fourth output terminal 5b2.

[0144] Exemplarily, W is 3, 4, 5, 6, 7, 8, 9 or 10.

[0145] Alternatively, if Fig.16 As shown, the timing control circuit 5 includes a plurality of fourth output terminals 5b, and the fourth output terminals 5b are arranged one-to-one with the first control terminal 11a, and the two are electrically connected. In different power consumption modes (low power consumption mode and high power consumption mode), the timing control circuit 5 can selectively control at least part of the fourth output terminals 5b to output the enable signal EN. For example, in the high power consumption mode, the timing control circuit 5 can selectively control all the fourth output terminals 5b to output the enable signal EN of the continuous effective level; in the low power consumption mode, the timing control circuit 5 can selectively control a small number (for example, 2, 3 or 4) of the fourth output terminals 5b to output the enable signal EN of the continuous effective level.

[0146] Alternatively, if Fig.17 As shown, the timing control circuit 5 includes a fourth output terminal 5b, which is electrically connected to all the first control terminals 11a, and is used to simultaneously provide the second signal V2 to each first control terminal 11a. In the high power consumption mode, the timing control circuit 5 can control all the enable signals EN to be continuously valid level signals, so as to control the valid level conversion sub-circuit 110 to continuously output the second signal V2, thereby continuously turning on the switch transistor T0, and further continuously outputting the data signal D0.

[0147] In some embodiments, Fig.18 As shown, the display panel also includes a main control circuit 6; the main control circuit 6 includes a fifth output terminal 6a, and the first control terminal 11a of each effective level conversion sub-circuit 110 is electrically connected to the fifth output terminal 6a; the main control circuit 6 is configured to output an enable signal EN through the fifth output terminal 6a to control whether the effective level conversion sub-circuit 110 outputs the second signal V2.

[0148] Optionally, the main control circuit 6 may be configured to continuously output the enable signal EN to control the effective level conversion sub-circuit 110 to continuously output the second signal V2 , thereby continuously turning on the switch transistor T0 , and further continuously outputting the data signal D0 .

[0149] Optionally, the wiring between the main control circuit 6 and the source driving circuit (SDIC) 1 is carried by a flexible printed circuit board (FPC), and the main control circuit 6 is carried by a printed circuit board (PCB). When the display panel is assembled, the printed circuit board (PCB) is bent to the backlight side of the display panel.

[0150] In some embodiments, the wiring between the source driver circuit (SDIC) 1 and the switching circuit 2 is carried by a flexible printed circuit board (FPC), and the source driver circuit (SDIC) 1 and the main control circuit 6 are carried by a printed circuit board (PCB). When the display panel is assembled, the printed circuit board (PCB) is bent to the backlight side of the display panel.

[0151] In some embodiments, Fig.19 As shown, the display panel also includes a sub-pixel 7 located in the display area AA, and a pixel driving circuit (shown in the figure) for driving the sub-pixel 7. The display panel also includes a plurality of gate lines Gate extending along a first direction X, and a plurality of data lines Data extending along a second direction Y. Optionally, the sub-pixels 7 are arranged in an array, the first direction X is the row direction, and the second direction Y is the column direction. The gate line Gate is used to provide a gate drive signal to a switch sub-circuit in the pixel driving circuit, and the data line Data is used to provide a data signal D0 to a switch sub-circuit in the pixel driving circuit to drive the sub-pixel 7 of the display panel to display a picture.

[0152] In some embodiments, the control electrode of the switch transistor T0 is in the same layer as the control electrode of the switch transistor (not shown in the figure) in the switch subcircuit in the pixel driving circuit, and the two can be prepared at the same time. The first electrode and the second electrode of the switch transistor T0 are in the same layer as the first electrode and the second electrode of the switch transistor in the switch subcircuit in the pixel driving circuit, and the two can be prepared at the same time.

[0153] In some embodiments, the control electrode of the switch transistor T0 and the signal transmission line 3 are both located in the same conductive layer.

[0154] In some embodiments, the signal transmission line 3 and the signal lead line 4 are both located in the same conductive layer.

[0155] In some embodiments, the display panel is an organic light-emitting diode (OLED) display panel.

[0156] Of course, the display panel involved in the embodiments of the present disclosure may also be a quantum dot light emitting diode (QLED) display panel or a micro light emitting diode (Micro LED) display panel, etc.

[0157] The display panel provided by the embodiment of the present disclosure fully utilizes the characteristic that both sides of the SDIC have the level conversion sub-circuit 11, and fully utilizes the idle level conversion sub-circuit 11 in the SDIC as the effective level conversion sub-circuit 110, thereby increasing the access points on the signal data line, such as the first node N1 between two adjacent SDICs, thereby reducing the waveform delay of the second signal V2 on the signal transmission line 3, effectively solving the problem of insufficient charging of the data signal D0 (data signal) in the pixel driving circuit, thereby eliminating the undesirable phenomenon of dark display effect of the display panel under high load; at the same time, it ensures that the large-size display panel with a one-to-two design of the switch circuit 2 can still maintain a high-quality display screen under a high-load screen, thereby improving the application prospects of large-size OLED display panels and greatly reducing the costs of various materials, parts and raw materials required for the product.

[0158] In addition, the embodiment of the present disclosure further provides a display device, which includes the display panel in the above embodiment. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.

[0159] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, comprising a base substrate, a plurality of source driving circuits arranged on the base substrate, a switch circuit arranged corresponding to each of the source driving circuits, and at least two signal transmission lines; the source driving circuit comprises at least four level conversion sub-circuits and a driving sub-circuit; the level conversion sub-circuit comprises a first control terminal, a first input terminal and a first output terminal; the switch circuit comprises at least two second control terminals, a second input terminal and at least two second output terminals; The at least four level conversion sub-circuits include at least two effective level conversion sub-circuits; For any one of the signal transmission lines, it is electrically connected to the first output end of at least one of the effective level conversion sub-circuits in each of the source driving circuits; different signal transmission lines are electrically connected to different effective level conversion sub-circuits; One of the signal transmission lines is electrically connected to one of the second control terminals of each of the switch circuits, and different signal transmission lines are electrically connected to different second control terminals; The effective level conversion sub-circuit is configured to adjust the first signal received by the first input terminal to a second signal in response to the enable signal input by the first control terminal, and output the second signal through the first output terminal; The driving sub-circuit is configured to output a data signal; The switch circuit is configured to output the data signal received by the second input terminal through the second output terminal in response to a second signal input by the second control terminal.

2. The display panel according to claim 1, wherein: The switch circuit includes M switch transistors; M is an integer greater than or equal to 2; the number of the switch transistors is the same as the number of the signal transmission lines; For the switch circuit, one switch transistor is electrically connected to one signal transmission line, and different switch transistors are electrically connected to different signal transmission lines.

3. The display panel according to claim 2, wherein: The switch circuit includes a first switch transistor and a second switch transistor; the signal transmission line includes a first transmission line and a second transmission line; the display panel also includes a plurality of data lines; The first electrode of the first switch transistor is electrically connected to the second input terminal, the second electrode is electrically connected to one of the data lines, and the control electrode is electrically connected to the first transmission line; The first electrode of the second switch transistor is electrically connected to the second input terminal, the second electrode is electrically connected to another data line, and the control electrode is electrically connected to the second transmission line.

4. The display panel according to claim 1, wherein: The orthographic projection of the switch circuit on the base substrate is located between the orthographic projection of the source driving circuit on the base substrate and the orthographic projection of the signal transmission line on the base substrate; A plurality of said source driving circuits are arranged side by side along a first direction; the extension direction of said signal transmission line is the first direction; said source driving circuit comprises four level conversion sub-circuits, which are divided into two groups of sub-circuit groups, each of said sub-circuit groups comprises two level conversion sub-circuits; The orthographic projections of the two groups of sub-circuit groups on the base substrate are respectively located on two opposite sides of the orthographic projection of the driving sub-circuit on the base substrate in the first direction.

5. The display panel according to claim 4, wherein: For any of the source driving circuits, the level conversion sub-circuits in at least one group of the sub-circuit groups are all the effective level conversion sub-circuits; The effective level conversion sub-circuits in the same sub-circuit group are electrically connected to different signal transmission lines.

6. The display panel according to claim 5, wherein: For any of the source driving circuits, the two sub-circuit groups include a first sub-circuit group and a second sub-circuit group; The level conversion sub-circuits in the first sub-circuit group are all the effective level conversion sub-circuits; The level conversion sub-circuits in the second sub-circuit group are all invalid level conversion sub-circuits.

7. The display panel according to claim 5, wherein: For any of the source driving circuits, the level conversion sub-circuits in the two sub-circuit groups are both effective level conversion sub-circuits.

8. The display panel according to claim 4, wherein: For a part of the source driving circuits, the level conversion sub-circuits in one group of the sub-circuit groups are all the effective level conversion sub-circuits; for another part of the source driving circuits, the level conversion sub-circuits in two groups of the sub-circuit groups are all the effective level conversion sub-circuits; The effective level conversion sub-circuits in the same sub-circuit group are electrically connected to different signal transmission lines.

9. The display panel according to claim 8, wherein: The source driving circuits include N, where N is an integer greater than or equal to 2; the two sub-circuit groups include a first sub-circuit group and a second sub-circuit group; For the i-th source driving circuit, the level conversion sub-circuits in the first sub-circuit group are all valid level conversion sub-circuits; the level conversion sub-circuits in the second sub-circuit group are all invalid level conversion sub-circuits; the orthographic projection of the first sub-circuit group on the substrate is located on the side of the orthographic projection of the second sub-circuit group on the substrate, away from the i+1-th source driving circuit; wherein i is an odd number between 1 and (N-1); For the (i+1)th source driving circuit, the level conversion sub-circuits in the first sub-circuit group and the second sub-circuit group are both the effective level conversion sub-circuits; When N is an odd number, for the Nth source driver circuit, the level conversion sub-circuits in the first sub-circuit group are all the invalid level conversion sub-circuits; and the level conversion sub-circuits in the second sub-circuit group are all the valid level conversion sub-circuits.

10. The display panel according to any one of claims 4 to 9, wherein: The display panel further comprises signal leads arranged in one-to-one correspondence with the first output terminals; the first output terminal is electrically connected to one of the signal transmission lines via the corresponding signal lead; The orthographic projection of the signal lead on the base substrate is located at one of two opposite sides of the orthographic projection of the switch circuit on the base substrate in the first direction and does not overlap with the orthographic projection of the switch circuit on the base substrate.

11. The display panel according to any one of claims 1 to 9, wherein: The level conversion subcircuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first amplifier and a second amplifier; The first transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the first node, and a control electrode electrically connected to the first control terminal; The first electrode of the second transistor is electrically connected to the second node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth node; The first electrode of the fourth transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the third node; The first electrode of the fifth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the output terminal of the first amplifier; An input terminal of the first amplifier is electrically connected to the first node; The input terminal of the second amplifier is electrically connected to the second node, and the output terminal of the second amplifier is electrically connected to the first output terminal.

12. The display panel according to any one of claims 4 to 9, wherein: The display panel further comprises a timing control circuit; the timing control circuit comprises a third output terminal, and the first input terminal of each of the effective level conversion sub-circuits is electrically connected to the third output terminal; The timing control circuit is configured to output the first signal through the third output terminal.

13. The display panel according to claim 12, wherein: The timing control circuit further comprises at least one fourth output terminal; the fourth output terminal is electrically connected to the first control terminal of the effective level conversion sub-circuit; The timing control circuit is further configured to output the enable signal through the fourth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

14. The display panel according to claim 13, wherein: The source driving circuits include W, where W is an integer greater than or equal to 3; the two sub-circuit groups include a first sub-circuit group and a second sub-circuit group; the level conversion sub-circuits in the first sub-circuit group and the second sub-circuit group are both effective level conversion sub-circuits; The fourth output terminals include four; the signal transmission line includes a first transmission line and a second transmission line; For the effective level conversion sub-circuit electrically connected to the first transmission line, one of the first control terminals in the first sub-circuit group in the first source driver circuit and one of the first control terminals in the second sub-circuit group in the Nth source driver circuit are both electrically connected to the first fourth output terminal; For the effective level conversion subcircuit electrically connected to the first transmission line, one of the first control terminals in the second subcircuit group in the first source driver circuit, one of the first control terminals in the first subcircuit group in the Nth source driver circuit, and two of the first control terminals in the kth source driver circuit are all electrically connected to the second fourth output terminal, where k is an integer between 2 and (N-1); For the effective level conversion sub-circuit electrically connected to the second transmission line, another first control terminal in the first sub-circuit group in the first source driving circuit and another first control terminal in the second sub-circuit group in the Nth source driving circuit are both electrically connected to the third fourth output terminal; For the effective level conversion sub-circuit electrically connected to the second transmission line, another first control terminal in the second sub-circuit group in the 1st source driving circuit, another first control terminal in the first sub-circuit group in the Nth source driving circuit, and another two first control terminals in the kth source driving circuit are all electrically connected to the 4th fourth output terminal.

15. The display panel according to claim 13, wherein: The fourth output terminal is connected to the first control terminal in a one-to-one correspondence.

16. The display panel according to claim 13, wherein: The source driving circuit includes four effective level conversion sub-circuits; the fourth output terminal includes four; the signal transmission line includes a first transmission line and a second transmission line; For the effective level conversion subcircuit electrically connected to the first transmission line, one first control terminal in each of the source driving circuits is electrically connected to the first fourth output terminal; another first control terminal in each of the source driving circuits is electrically connected to the second fourth output terminal; For the effective level conversion sub-circuit electrically connected to the second transmission line, a first control terminal in each of the source driving circuits is electrically connected to the third fourth output terminal; another first control terminal in each of the source driving circuits is electrically connected to the fourth fourth output terminal.

17. The display panel according to claim 1, wherein: The display panel further comprises a main control circuit; the main control circuit comprises a fifth output terminal, and the first control terminal of each of the effective level conversion sub-circuits is electrically connected to the fifth output terminal; The main control circuit is configured to output the enable signal through the fifth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

18. A display device, wherein: The invention comprises the display panel according to any one of claims 1 to 17.

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