Memory array circuit, ternary content addressable memory and operation method thereof

Abstract

The invention provides a ternary content addressable memory which comprises a first memory unit and a second memory unit, and the second memory unit is electrically connected with the first memory unit. The first memory unit comprises a control transistor and a first impedance variable passive element, and one end of the first impedance variable passive element is electrically connected with a grid electrode of the control transistor. The second memory unit comprises a data transistor and a second impedance variable passive element, the data transistor is connected in series with the control transistor, and one end of the second impedance variable passive element is electrically connected with the grid electrode of the data transistor. Through the technical scheme of the invention, the ternary content addressable memory is a non-volatile ternary content addressable memory, the stability is high, the memory window is wider, and the energy consumption is reduced.

Description

Technical Field

[0001] The present invention relates to a storage circuit and an operating method thereof, and in particular to a memory array circuit, a ternary content addressable memory and an operating method thereof. Background Art

[0002] With the vigorous development of the semiconductor industry, semiconductor components are constantly being innovated. In many application fields, ternary content addressable memory (TCAM) is widely used in various electronic products.

[0003] Traditionally, ternary content addressable memory is usually implemented by two static random access memory (SRAM) cells with additional matching logic elements. However, SRAM-TCAM not only takes up more than ten transistors to represent the search, but it is also energy-consuming due to the volatility of SRAM. Therefore, based on the above reasons, a new ternary content addressable memory is needed to improve the problems of the previous technology. Summary of the invention

[0004] The present invention provides a memory array circuit, a ternary content addressable memory and an operation method thereof, which improve the problems of the prior art.

[0005] In one embodiment of the present invention, the ternary content addressable memory proposed by the present invention comprises a first memory unit and a second memory unit, wherein the second memory unit is electrically connected to the first memory unit. The first memory unit comprises a control transistor and a first variable impedance passive element, wherein one end of the first variable impedance passive element is electrically connected to the gate of the control transistor; the second memory unit comprises a data transistor and a second variable impedance passive element, wherein the data transistor is connected in series to the control transistor, and one end of the second variable impedance passive element is electrically connected to the gate of the data transistor.

[0006] In one embodiment of the present invention, a source / drain of the control transistor is electrically connected to the bit line, another source / drain of the control transistor is electrically connected to a source / drain of the data transistor, another source / drain of the control transistor and the source / drain of the data transistor are electrically connected to the matching line, and another source / drain of the data transistor is electrically connected to the data line.

[0007] In one embodiment of the present invention, the other end of the first variable impedance passive element is electrically connected to the control line, and the other end of the second variable impedance passive element is electrically connected to the word line.

[0008] In one embodiment of the present invention, the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to the word line.

[0009] In one embodiment of the present invention, each of the first variable impedance passive element and the second variable impedance passive element may be a variable resistor, a variable capacitor, or a capacitive element with electron trapping capability and a fixed dielectric constant.

[0010] In one embodiment of the present invention, the memory array circuit proposed by the present invention includes a plurality of ternary content addressable memories, the plurality of ternary content addressable memories are arranged in an array, each of the plurality of ternary content addressable memories includes a first memory unit and a second memory unit, the second memory unit is electrically connected to the first memory unit. The first memory unit includes a control transistor and a first variable impedance passive element, one end of the first variable impedance passive element is electrically connected to the gate of the control transistor; the second memory unit includes a data transistor and a second variable impedance passive element, the data transistor is connected in series with the control transistor, and one end of the second variable impedance passive element is electrically connected to the gate of the data transistor.

[0011] In one embodiment of the present invention, a source / drain of the control transistor is electrically connected to one of a plurality of bit lines, another source / drain of the control transistor is electrically connected to a source / drain of the data transistor, another source / drain of the control transistor and the source / drain of the data transistor are electrically connected to one of a plurality of match lines, another source / drain of the data transistor is electrically connected to one of a plurality of data lines, a plurality of bit lines and a plurality of data lines are electrically connected to a first circuit, and a plurality of match lines are electrically connected to a second circuit.

[0012] In one embodiment of the present invention, the other end of the first variable impedance passive element is electrically connected to one of a plurality of control lines, the other end of the second variable impedance passive element is electrically connected to one of a plurality of word lines, the plurality of control lines are electrically connected to the fourth circuit, and the plurality of word lines are electrically connected to the third circuit.

[0013] In one embodiment of the present invention, the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are both electrically connected to one of a plurality of word lines, and the plurality of word lines are electrically connected to the third circuit.

[0014] In one embodiment of the present invention, the present invention provides an operation method of a ternary content addressable memory. The ternary content addressable memory includes a first memory unit and a second memory unit. The first memory unit includes a control transistor and a first variable impedance passive element. One end of the first variable impedance passive element is electrically connected to a gate of the control transistor. The second memory unit includes a data transistor and a second variable impedance passive element. The data transistor is connected in series with the control transistor. One end of the second variable impedance passive element is electrically connected to a gate of the data transistor. The operation method includes the following steps: when searching the ternary content addressable memory, a working voltage is applied to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element, and a current value of a bit line is read to determine whether the first memory unit is in a related mode or an irrelevant mode, wherein a source / drain of the control transistor is electrically connected to the bit line. In the irrelevant mode, a channel resistance of the control transistor is in a first resistance state. In the related mode, the channel resistance of the control transistor is in a third resistance state. The channel resistance of the data transistor is in a second resistance state or a fourth resistance state. The first resistance state is greater than the second resistance state, the second resistance state is greater than the third resistance state, and the third resistance state is greater than the fourth resistance state.

[0015] In one embodiment of the present invention, another source / drain of the control transistor is electrically connected to a source / drain of the data transistor, another source / drain of the control transistor and the source / drain of the data transistor are electrically connected to a matching line, another source / drain of the data transistor is electrically connected to a data line, and the operating method further includes: when the first memory unit is in a related mode, a first voltage is applied to the data line, a second voltage complementary to the first voltage is applied to the bit line, and the information stored in the second memory unit is determined to correspond to the first search result or the second search result based on the voltage value of the matching line, and the second search result is opposite to the first search result.

[0016] In one embodiment of the present invention, the channel resistance of the data transistor is in a fourth resistance state. If the first voltage of the data line is zero voltage and the second voltage of the bit line is an operating voltage, the voltage value of the match line is approximately zero voltage, and the information stored in the second memory unit corresponds to the first search result. If the first voltage of the data line is the operating voltage and the second voltage of the bit line is zero voltage, the voltage value of the match line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result.

[0017] In one embodiment of the present invention, the channel resistance of the data transistor is in a second resistance state, if the first voltage of the data line is a zero voltage and the second voltage of the bit line is an operating voltage, the voltage value of the matching line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result, and if the first voltage of the data line is an operating voltage and the second voltage of the bit line is a zero voltage, the voltage value of the matching line is approximately a voltage lower than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the first search result.

[0018] In one embodiment of the present invention, the other end of the first variable impedance passive element is electrically connected to a control line, and the other end of the second variable impedance passive element is electrically connected to a word line. The step of applying a working voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element includes: applying a working voltage to both the control line and the word line.

[0019] In one embodiment of the present invention, the operating method further includes: when programming the first memory cell, applying a programming voltage to the control line, floating the word line, floating the match line, applying a zero voltage to the bit line, and floating the data line; when programming the second memory cell, floating the control line, applying a programming voltage to the word line, floating the match line, floating the bit line, and applying a zero voltage to the data line.

[0020] In one embodiment of the present invention, the operating method further includes: when erasing the first memory unit, applying zero voltage to the control line, floating the word line, floating the match line, applying an erase voltage to the bit line, and floating the data line; when erasing the second memory unit, floating the control line, applying zero voltage to the word line, floating the match line, floating the bit line, and applying an erase voltage to the data line.

[0021] In one embodiment of the present invention, the operating method further includes: when reading the first memory unit, applying a read voltage to the control line, applying a zero voltage to the word line, applying a zero voltage to the match line, applying a test voltage to the bit line, and applying a zero voltage to the data line; when reading the second memory unit, applying a zero voltage to the control line, applying a read voltage to the word line, applying a zero voltage to the match line, applying a zero voltage to the bit line, and applying a test voltage to the data line.

[0022] In one embodiment of the present invention, the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to a word line, and the step of applying a working voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element includes: applying the working voltage to the word line.

[0023] In one embodiment of the present invention, the operating method further includes: when programming the first memory unit and the second memory unit, applying a programming voltage to the word line, floating the match line, applying a zero voltage to the bit line, and applying a zero voltage to the data line; when erasing the first memory unit, applying a zero voltage to the word line, floating the match line, applying an erase voltage to the bit line, and floating the data line; when erasing the second memory unit, applying a zero voltage to the word line, floating the match line, floating the bit line, and applying an erase voltage to the data line.

[0024] In one embodiment of the present invention, the operating method further includes: when reading the first memory cell, applying a read voltage to the word line, floating the match line, applying a test voltage to the bit line, and applying a zero voltage to the data line; when reading the second memory cell, applying a read voltage to the word line, floating the match line, applying a zero voltage to the bit line, and applying a test voltage to the data line.

[0025] In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. Through the technical solution of the present invention, the ternary content addressable memory is a non-volatile ternary content addressable memory with high stability, a wide memory window, and energy saving.

[0026] The above description will be described in detail below with reference to implementation examples, and a further explanation will be provided for the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0028] Figure 1 is a circuit diagram of a ternary content addressable memory according to an embodiment of the present invention;

[0029] Figure 2 is a circuit diagram of a ternary content addressable memory according to another embodiment of the present invention;

[0030] Figure 3 is a diagram of setting, resetting and reading in a method of operating a ternary content addressable memory according to an embodiment of the present invention;

[0031] Figure 4 A diagram of searching in a method for operating a ternary content addressable memory according to an embodiment of the present invention;

[0032] Figure 5 is a diagram of setting, resetting and reading in a method of operating a ternary content addressable memory according to another embodiment of the present invention;

[0033] Figure 6A diagram for searching in a method for operating a ternary content addressable memory according to another embodiment of the present invention;

[0034] Figure 7 is an equivalent circuit diagram of a memory array circuit according to an embodiment of the present invention; and

[0035] Figure 8 is an equivalent circuit diagram of a memory array circuit according to another embodiment of the present invention.

[0036]

Explanation of symbols

[0037] 100, 200: Ternary content addressable memory

[0038] 110, 210: First memory unit

[0039] 111, 211: control transistor

[0040] 112, 212: first variable impedance passive element

[0041] 120, 220: Second memory unit

[0042] 121, 221: data transistor

[0043] 122, 222: second variable impedance passive element

[0044] 700, 800: memory array circuit

[0045] 710, 810: First Circuit

[0046] 720, 820: Second circuit

[0047] 730, 830: Third Circuit

[0048] 740: Fourth Circuit

[0049] BL, BL0~BL n :Bit Line

[0050] CL, CL0~CL n :Control Line

[0051] DL, DL0~DL n :Data cable

[0052] GRS: First resistance state

[0053] HRS: Second resistance state

[0054] LRS: Fourth resistance state

[0055] MRS: Third resistance state

[0056] R data :Channel resistance

[0057] R ctr :Channel resistance

[0058] V dd :Working voltage

[0059] V ERS :Erase voltage

[0060] V PGM :Programming voltage

[0061] V READ :Read voltage

[0062] V TEST :Test voltage

[0063] ML, ML0~ML n :Match Line

[0064] WL, WL0~WL n :Character Line DETAILED DESCRIPTION

[0065] In order to make the description of the present invention more detailed and complete, reference can be made to the attached drawings and various embodiments described below, in which the same numbers represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations on the present invention.

[0066] Please refer to Figure 1 , Figure 2 The technical aspect of the present invention is a ternary content addressable memory 100, 200, which can play an important role in data search and matching in modern digital computing architectures, or is widely used in related technical links. The ternary content addressable memory 100, 200 of the present technical aspect can achieve considerable technical progress and has wide industrial utilization value. The specific implementation of the ternary content addressable memory 100, 200 will be described below with reference to Figures 1 and 2.

[0067] It should be understood that various embodiments of the ternary content addressable memory 100, 200 are described in conjunction with Figures 1 and 2. In the following description, for ease of explanation, many specific details are further set to provide a comprehensive description of one or more embodiments. However, the present technology can be implemented without these specific details. In other examples, in order to effectively describe these embodiments, known structures and devices are shown in block diagram form. The term "for example" is used herein to mean "as an example, instance or illustration." Any embodiment described herein as "for example" is not necessarily to be interpreted as better or superior to other embodiments.

[0068] Figure 1 FIG. 1 is a circuit diagram of a ternary content addressable memory 100 according to an embodiment of the present invention. Figure 1 As shown, the ternary content addressable memory 100 includes a first memory unit 110 and a second memory unit 120. In terms of architecture, the second memory unit 120 is electrically connected to the first memory unit 110. When in use, the first memory unit 110 is used for control, and the second memory unit 120 is used for data storage and search. Specifically, the first memory unit 110 controls the "Care" and "Don't Care" modes; the second memory unit 120 stores some content that needs to be matched.

[0069] It should be understood that in the embodiments and claims, the description involving “electrical connection” may generally refer to one element being indirectly electrically coupled to another element through other elements, or one element being directly electrically connected to another element without going through other elements.

[0070] At Figure 1 In the embodiment, the first memory unit 110 includes a control transistor 111 and a first variable impedance passive element 112. In terms of structure, one end of the first variable impedance passive element 112 is electrically connected to the gate of the control transistor 111. Similarly, the second memory unit 120 includes a data transistor 121 and a second variable impedance passive element 122. In terms of structure, the data transistor 121 is connected in series with the control transistor 111, and one end of the second variable impedance passive element 122 is electrically connected to the gate of the data transistor 121. In practice, for example, Figure 1 In the embodiment, Figure 1 The control transistor 111 and the data transistor 121 may both be N-type field effect transistors; or, in other embodiments, the control transistor 111 and the data transistor 121 may also be P-type field effect transistors. Those skilled in the art may flexibly select the appropriate one for practical applications.

[0071] Furthermore, it should be noted that, although the terms "first", "second" ... etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the embodiment, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0072] At Figure 1In the embodiment, a source / drain of the control transistor 111 is electrically connected to the bit line BL, another source / drain of the control transistor 111 is electrically connected to a source / drain of the data transistor 121, another source / drain of the control transistor 111 and the source / drain of the data transistor 121 are electrically connected to the matching line ML, and another source / drain of the data transistor 121 is electrically connected to the data line DL.

[0073] At Figure 1 In some embodiments of the present invention, the other end of the first variable impedance passive element 112 is electrically connected to the control line CL, and the other end of the second variable impedance passive element 122 is electrically connected to the word line WL. Different variable impedance passive elements are connected through the control line CL and the word line WL, so as to facilitate the subsequent programming operations of the first memory unit 110 and the second memory unit 120.

[0074] At Figure 1 In some embodiments of the present invention, each of the first variable impedance passive element 112 and the second variable impedance passive element 122 can be a variable resistor, a variable capacitor (such as a ferroelectric capacitor), a capacitive element with electron trapping capability and a fixed dielectric constant (such as the material of a floating gate in a flash memory), or other materials with variable storage characteristics.

[0075] In summary, the present invention uses the first variable impedance passive element 112 and the second variable impedance passive element 122 to enable the ternary content addressable memory 100 to be used as a non-volatile ternary content addressable memory with high stability, a wider memory window, and energy saving.

[0076] In a controlled experiment, spin torque transfer magnetic random access memory (STT-MRAM) was used as a ternary content addressable memory, but the memory window between states "0" and "1" was narrow, resulting in degraded signal integrity and high programming current.

[0077] In a controlled experiment, a transistor was paired with a resistive random access memory (RRAM) as a ternary content addressable memory, but the limited endurance cycle and insufficient memory window of RRAM are inevitable drawbacks.

[0078] Figure 2 FIG. 2 is a circuit diagram of a ternary content addressable memory 200 according to another embodiment of the present invention. Figure 2 As shown, the ternary content addressable memory 200 includes a first memory unit 210 and a second memory unit 220. In terms of architecture, the second memory unit 220 is electrically connected to the first memory unit 210.

[0079] At Figure 1In the embodiment, the first memory unit 210 includes a control transistor 211 and a first variable impedance passive element 212. In terms of structure, one end of the first variable impedance passive element 212 is electrically connected to the gate of the control transistor 211. Similarly, the second memory unit 1220 includes a data transistor 221 and a second variable impedance passive element 222. In terms of structure, the data transistor 221 is connected in series with the control transistor 211, and one end of the second variable impedance passive element 222 is electrically connected to the gate of the data transistor 221. In practice, for example, Figure 1 In the embodiment, Figure 1 The control transistor 111 and the data transistor 221 may both be N-type field effect transistors; or, in other embodiments, the control transistor 211 and the data transistor 221 may also be P-type field effect transistors. Those skilled in the art may flexibly select the appropriate one for practical applications.

[0080] At Figure 2 In the embodiment, a source / drain of the control transistor 211 is electrically connected to the bit line BL, another source / drain of the control transistor 211 is electrically connected to a source / drain of the data transistor 221, another source / drain of the control transistor 211 and the source / drain of the data transistor 221 are electrically connected to the matching line ML, and another source / drain of the data transistor 221 is electrically connected to the data line DL.

[0081] At Figure 2 In some embodiments of the present invention, the other end of the first variable impedance passive element 212 and the other end of the second variable impedance passive element 222 are electrically connected to the word line WL. The first variable impedance passive element 212 and the second variable impedance passive element 222 share the same word line WL, so that the ternary content addressable memory 200 occupies a smaller area.

[0082] For a detailed description of the operation method of the ternary content addressable memory 100, please also refer to Figure 1 , Figure 3 . Figure 3 is a diagram of setting, resetting and reading in a method for operating a ternary content addressable memory 100 according to an embodiment of the present invention.

[0083] In the stage of setting the ternary content addressable memory 100, when programming the first memory cell 110, a programming voltage V is applied to the control line CL. PGM (e.g., about 2V to 4V), float the word line WL, float the match line ML, apply zero voltage (e.g., about 0V) to the bit line BL, and float the data line DL. Similarly, when programming the second memory cell 120, float the control line CL, apply the programming voltage V PGM, float the match line ML, float the bit line BL, and apply zero voltage to the data line DL.

[0084] In the stage of resetting the ternary content addressable memory 100, when erasing the first memory unit 110, a zero voltage is applied to the control line CL, the word line WL is floated, the match line ML is floated, and an erase voltage V is applied to the bit line BL. ERS Similarly, when erasing the second memory cell 120, the control line CL is floated, a zero voltage is applied to the word line WL, the match line ML is floated, the bit line BL is floated, and an erase voltage V is applied to the data line DL. ERS .

[0085] In the stage of reading the ternary content addressable memory 100, when reading the first memory unit 110, a read voltage V is applied to the control line CL. READ (e.g., about 0.8V), apply zero voltage to the word line WL, apply zero voltage to the match line ML, and apply a test voltage V to the bit line BL TEST Similarly, when reading the second memory cell 120, a zero voltage is applied to the control line CL, and a read voltage V is applied to the word line WL. READ , apply zero voltage to the match line ML, apply zero voltage to the bit line BL, and apply test voltage V to the data line DL TEST .

[0086] It should be understood that the "about", "approximately" or "roughly" used herein is used to modify any quantity that can be slightly changed, but such slight changes do not change its essence. If there is no special explanation in the embodiment, the error range of the value modified by "about", "approximately" or "roughly" is generally allowed within 20%, preferably within 10%, and more preferably within 5%.

[0087] For a detailed description of the operation method of the ternary content addressable memory 200, please also refer to Figure 2 , Figure 5 . Figure 5 is a diagram of setting, resetting and reading in a method for operating a ternary content addressable memory 200 according to another embodiment of the present invention.

[0088] In the stage of setting the ternary content addressable memory 200, when programming the first memory unit 110 and the second memory unit 120, a programming voltage V is applied to the word line WL. PGM(e.g., about 1.5V to 4V), float the match line ML, apply zero voltage to the bit line BL, and apply zero voltage to the data line DL. Since the first memory unit 110 and the second memory unit 120 share the same word line WL, the first memory unit 110 and the second memory unit 120 will be programmed to the same storage content together, but the first memory unit 110 and the second memory unit 120 can be erased to different degrees respectively, so that the storage content of the first memory unit 110 and the storage content of the second memory unit 120 are different.

[0089] In the stage of resetting the ternary content addressable memory 200, when erasing the first memory cell 110, a zero voltage is applied to the word line WL, the match line ML is floated, and an erase voltage V is applied to the bit line BL. ERS Similarly, when erasing the second memory cell 120, zero voltage is applied to the word line WL, the match line ML is floated, the bit line BL is floated, and an erase voltage V is applied to the data line DL. ERS (For example: about 1.5V ~ 4V).

[0090] In the stage of reading the ternary content addressable memory 200, when reading the first memory unit 110, a read voltage V is applied to the word line WL. READ (e.g. about 0.8V to 1V), float the match line ML, and apply a test voltage V to the bit line BL TEST (eg, about 0.3V to 1V), a zero voltage is applied to the data line DL. Similarly, when reading the second memory cell 120, a read voltage V is applied to the word line WL. READ , float the match line ML, apply zero voltage to the bit line BL, and apply a test voltage V to the data line DL TEST .

[0091] For a detailed description of the search phase of the operation method of the ternary content addressable memory 100, please also refer to Figure 1 , Figure 3 , Figure 4 . Figure 4 FIG. 1 is a diagram of a search in a method for operating a ternary content addressable memory 100 according to an embodiment of the present invention. Figure 1 In the embodiment, one end of the first variable impedance passive element 112 is electrically connected to the gate of the control transistor 111 , and one end of the second variable impedance passive element 122 is electrically connected to the gate of the data transistor 121 .

[0092] When searching the ternary content addressable memory 100, the other end of the first variable impedance passive element 112 and the other end of the second variable impedance passive element 122 are both applied with a working voltage V dd, and read the current value of the bit line BL to determine whether the first memory unit 110 is in the relevant mode or the irrelevant mode, wherein a source / drain of the control transistor 111 is electrically connected to the bit line BL.

[0093] Regarding the applied working voltage V dd In some embodiments of the present invention, the other end of the first variable impedance passive element 112 is electrically connected to the control line CL, and the other end of the second variable impedance passive element 122 is electrically connected to the word line WL. The other end of the first variable impedance passive element 112 and the other end of the second variable impedance passive element 122 are both applied with a working voltage V dd The step may include: applying a working voltage V to both the control line CL and the word line WL dd .

[0094] Regarding the specific method of determining whether the first memory unit 110 is in the relevant mode or the irrelevant mode, in some embodiments of the present invention, if the current value of the bit line BL is greater than the preset current threshold value, the first memory unit 110 is in the relevant mode; conversely, if the current value of the bit line BL (e.g., close to zero current) is less than or equal to the preset current threshold value, the first memory unit 110 is in the irrelevant mode. In practice, for example, the preset current threshold value can be set based on actual experience or experimental data.

[0095] In the don't care mode, the channel resistance R of the control transistor 111 is ctr In the first resistance state GRS, the channel resistance R of the data transistor 121 data In the relevant mode, the channel resistance R of the control transistor 111 is ctr In the third resistance state MRS, the channel resistance R data The first resistance state GRS is greater than the second resistance state HRS, the second resistance state HRS is greater than the third resistance state MRS, and the third resistance state MRS is greater than the fourth resistance state LRS.

[0096] In practice, for example, after the first variable impedance passive element 112 is programmed / erased, the channel resistance R of the control transistor 111 during operation is controlled. ctr Similarly, after the second variable impedance passive element 122 is programmed / erased, the channel resistance R of the data transistor 121 during operation is affected. data The resistance state is affected.

[0097] Next, when the first memory unit 110 is in the correlation mode, a first voltage is applied to the data line DL, and a second voltage complementary to the first voltage is applied to the bit line BL, and the information stored in the second memory unit 120 is determined to correspond to the first search result or the second search result according to the voltage value of the match line ML, and the second search result is opposite to the first search result. In some embodiments of the present invention, the first search result is a match, and the second search result is a mismatch. Alternatively, it can also be defined inversely, in some embodiments of the present invention, the first search result is a mismatch, and the second search result is a match.

[0098] In some embodiments of the present invention, the channel resistance R of the data transistor 121 is data In the fourth resistance state LRS, if the first voltage of the data line DL is approximately zero voltage (0V) and the second voltage of the bit line BL is approximately the working voltage V dd , the voltage value of the matching line ML is approximately zero voltage, and the information stored in the second memory unit 120 corresponds to the first search result; on the contrary, if the first voltage of the data line DL is approximately the working voltage V dd When the second voltage of the bit line BL is approximately zero voltage (0V), the voltage value of the matching line ML is approximately one third of the working voltage V dd High voltage or about the working voltage V dd , the information stored in the second memory unit 120 corresponds to the second search result.

[0099] Alternatively, in some embodiments of the present invention, the channel resistance R of the data transistor 121 is data In the second resistance state HRS, if the first voltage of the data line DL is approximately zero voltage and the second voltage of the bit line BL is approximately the working voltage V dd , the voltage value of the matching line ML is about one-third of the operating voltage V dd High voltage or about the working voltage V dd , the information stored in the second memory unit 120 corresponds to the second search result; on the contrary, if the first voltage of the data line DL is approximately the working voltage V dd When the second voltage of the bit line BL is approximately zero voltage, the voltage value of the matching line ML is approximately one third of the working voltage V dd The voltage is low or approximately zero, and the information stored in the second memory unit 120 corresponds to the first search result.

[0100] For a detailed description of the search phase of the operation method of the ternary content addressable memory 200, please also refer to Figure 2 , Figure 5 , Figure 6 . Figure 6 FIG. 2 is a diagram of a search in a method for operating a ternary content addressable memory 200 according to another embodiment of the present invention. Figure 2 In the embodiment, one end of the first variable impedance passive element 212 is electrically connected to the gate of the control transistor 211 , and one end of the second variable impedance passive element 222 is electrically connected to the gate of the data transistor 221 .

[0101] When searching the ternary content addressable memory 200, the other end of the first variable impedance passive element 212 and the other end of the second variable impedance passive element 222 are both applied with a working voltage V dd , and read the current value of the bit line BL to determine whether the first memory unit 210 is in the relevant mode or the irrelevant mode, wherein a source / drain of the control transistor 211 is electrically connected to the bit line BL.

[0102] Regarding the applied working voltage V dd The other end of the first variable impedance passive element 212 and the other end of the second variable impedance passive element 222 are electrically connected to the word line WL, and the other end of the first variable impedance passive element 212 and the other end of the second variable impedance passive element 222 are both applied with a working voltage V dd The steps include: applying a working voltage V to the word line WL dd .

[0103] Regarding the specific method of determining whether the first memory unit 210 is in the relevant mode or the irrelevant mode, in some embodiments of the present invention, if the current value of the bit line BL is greater than the preset current threshold value, the first memory unit 210 is in the relevant mode; conversely, if the current value of the bit line BL (e.g., close to zero current) is less than or equal to the preset current threshold value, the first memory unit 210 is in the irrelevant mode. In practice, for example, the preset current threshold value can be set based on actual experience or experimental data.

[0104] In the don't care mode, the channel resistance R of the control transistor 211 is ctr In the first resistance state GRS, the channel resistance R of the data transistor 221 data In the relevant mode, the channel resistance R of the control transistor 211 is ctr In the third resistance state MRS, the channel resistance R data The first resistance state GRS is greater than the second resistance state HRS, the second resistance state HRS is greater than the third resistance state MRS, and the third resistance state MRS is greater than the fourth resistance state LRS.

[0105] In practice, for example, after the first variable impedance passive element 212 is programmed / erased, the channel resistance R of the control transistor 211 during operation is controlled. ctrSimilarly, after the second variable impedance passive element 222 is programmed / erased, the channel resistance R of the data transistor 221 during operation is affected. data The resistance state is affected.

[0106] Next, when the first memory unit 210 is in the correlation mode, a first voltage is applied to the data line DL, and a second voltage complementary to the first voltage is applied to the bit line BL, and the information stored in the second memory unit 120 is determined to correspond to the first search result or the second search result according to the voltage value of the match line ML, and the second search result is opposite to the first search result. In some embodiments of the present invention, the first search result is a match, and the second search result is a mismatch. Alternatively, it can also be defined inversely, in some embodiments of the present invention, the first search result is a mismatch, and the second search result is a match.

[0107] In some embodiments of the present invention, the channel resistance R of the data transistor 221 is data In the fourth resistance state LRS, if the first voltage of the data line DL is approximately zero voltage (0V) and the second voltage of the bit line BL is approximately the working voltage V dd , the voltage value of the matching line ML is approximately zero voltage, and the information stored in the second memory unit 220 corresponds to the first search result; on the contrary, if the first voltage of the data line DL is approximately the working voltage V dd When the second voltage of the bit line BL is approximately zero voltage (0V), the voltage value of the matching line ML is approximately the working voltage V dd , the information stored in the second memory unit 220 corresponds to the second search result.

[0108] Alternatively, in some embodiments of the present invention, the channel resistance R of the data transistor 221 is data In the second resistance state HRS, if the first voltage of the data line DL is approximately zero voltage and the second voltage of the bit line BL is approximately the working voltage V dd , the voltage value of the matching line ML is approximately the operating voltage V dd , the information stored in the second memory unit 220 corresponds to the second search result; on the contrary, if the first voltage of the data line DL is approximately the working voltage V dd When the second voltage of the bit line BL is approximately zero voltage, the voltage value of the match line ML is approximately zero voltage, and the information stored in the second memory unit 220 corresponds to the first search result.

[0109] Figure 7 FIG. 7 is an equivalent circuit diagram of a memory array circuit 700 according to an embodiment of the present invention. Figure 7As shown, the memory array circuit 700 includes a plurality of ternary content addressable memories 100, the plurality of ternary content addressable memories 100 are arranged in an array, each of the plurality of ternary content addressable memories 100 includes a first memory unit 110 and a second memory unit 120, the second memory unit 120 is electrically connected to the first memory unit 110. The first memory unit 110 includes a control transistor 111 and a first variable impedance passive element 112, one end of the first variable impedance passive element 112 is electrically connected to the gate of the control transistor 111; similarly, the second memory unit 120 includes a data transistor 121 and a second variable impedance passive element 122, the data transistor 121 is connected in series to the control transistor 111, and one end of the second variable impedance passive element 122 is electrically connected to the gate of the data transistor 121.

[0110] exist Figure 7 In the embodiment, a source / drain of the control transistor 111 is electrically connected to a plurality of bit lines BL0-BL n The other source / drain of the control transistor 111 is electrically connected to a source / drain of the data transistor 121, and the other source / drain of the control transistor 111 and the source / drain of the data transistor 121 are electrically connected to a plurality of match lines ML0-ML1. n The other source / drain of the data transistor 121 is electrically connected to a plurality of data lines DL0-DL n One of the plurality of bit lines BL0-BL n With multiple data lines DL0~DL n Electrically connected to the first circuit 710, a plurality of matching lines ML0-ML n Electrically connected to the second circuit 720 .

[0111] In some embodiments of the present invention, the first circuit 710 may include a bit line driver, a data line driver, a control circuit, a peripheral circuit, and a sense amplifier. When in use, the control circuit controls the bit line driver to apply a suitable voltage (such as an erase voltage, a test voltage, a zero voltage, a floating connection, etc.) to the bit line, the control circuit controls the data line driver to apply a suitable voltage (such as an erase voltage, a test voltage, a zero voltage, a floating connection, etc.) to the bit line, the sense amplifier can sense the current value on the bit line, and the control circuit can determine the relevant or irrelevant mode according to the current value.

[0112] In some embodiments of the present invention, the second circuit 720 may include a match line driver, a control circuit, a peripheral circuit, and a read circuit. When in use, the control circuit controls the match line driver to apply a suitable voltage (such as zero voltage, floating, etc.) to the match line, the read circuit can read the voltage value on the match line, and the control circuit can determine the search result based on the voltage value.

[0113] exist Figure 7 The other end of the first variable impedance passive element 112 is electrically connected to a plurality of control lines CL0-CL n The other end of the second variable impedance passive element 122 is electrically connected to a plurality of word lines WL0-WL n One of the plurality of word lines WL0-WL n Electrically connected to the third circuit 730, a plurality of control lines CL0-CL n Electrically connected to the fourth circuit 740 .

[0114] In some embodiments of the present invention, the third circuit 730 may include a word line driver, a control circuit and a peripheral circuit. When in use, the control circuit controls the word line driver to apply a suitable voltage (such as programming voltage, reading voltage, zero voltage, floating, etc.) to the word line.

[0115] In some embodiments of the present invention, the fourth circuit 740 may include a control line driver, a control circuit and a peripheral circuit. When in use, the control circuit controls the control line driver to apply a suitable voltage (such as programming voltage, reading voltage, zero voltage, floating, etc.) to the control line.

[0116] Figure 8 FIG. 8 is an equivalent circuit diagram of a memory array circuit 800 according to another embodiment of the present invention. Figure 8 As shown, the memory array circuit 800 includes a plurality of ternary content addressable memories 200, the plurality of ternary content addressable memories 200 are arranged in an array, each of the plurality of ternary content addressable memories 200 includes a first memory unit 210 and a second memory unit 220, the second memory unit 220 is electrically connected to the first memory unit 210. The first memory unit 210 includes a control transistor 211 and a first variable impedance passive element 212, one end of the first variable impedance passive element 212 is electrically connected to the gate of the control transistor 211; similarly, the second memory unit 220 includes a data transistor 221 and a second variable impedance passive element 222, the data transistor 221 is connected in series with the control transistor 211, and one end of the second variable impedance passive element 222 is electrically connected to the gate of the data transistor 221.

[0117] exist Figure 8 In the embodiment, a source / drain of the control transistor 211 is electrically connected to a plurality of bit lines BL0-BL n The other source / drain of the control transistor 211 is electrically connected to a source / drain of the data transistor 221, and the other source / drain of the control transistor 211 and the source / drain of the data transistor 221 are electrically connected to a plurality of match lines ML0-ML1. n The other source / drain of the data transistor 221 is electrically connected to a plurality of data lines DL0-DLn One of the plurality of bit lines BL0-BL n With multiple data lines DL0~DL n Electrically connected to the first circuit 810, a plurality of matching lines ML0-ML n Electrically connected to the second circuit 820 .

[0118] In some embodiments of the present invention, the first circuit 810 may include a bit line driver, a data line driver, a control circuit, a peripheral circuit, and a sense amplifier. When in use, the control circuit controls the bit line driver to apply a suitable voltage (such as an erase voltage, a test voltage, a zero voltage, a floating connection, etc.) to the bit line, the control circuit controls the data line driver to apply a suitable voltage (such as an erase voltage, a test voltage, a zero voltage, a floating connection, etc.) to the bit line, the sense amplifier can sense the current value on the bit line, and the control circuit can determine the relevant or irrelevant mode according to the current value.

[0119] In some embodiments of the present invention, the second circuit 820 may include a match line driver, a control circuit, a peripheral circuit, and a read circuit. When in use, the control circuit controls the match line driver to apply a suitable voltage (such as zero voltage, floating, etc.) to the match line, the read circuit can read the voltage value on the match line, and the control circuit can determine the search result based on the voltage value.

[0120] exist Figure 8 In the embodiment, the other end of the first variable impedance passive element 212 and the other end of the second variable impedance passive element 222 are both electrically connected to a plurality of word lines WL0-WL1. n One of the plurality of word lines WL0-WL n Electrically connected to the third circuit 830 .

[0121] In some embodiments of the present invention, the third circuit 830 may include a word line driver, a control circuit and a peripheral circuit. When in use, the control circuit controls the word line driver to apply a suitable voltage (such as programming voltage, reading voltage, zero voltage, etc.) to the word line.

[0122] In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. Through the technical solution of the present invention, the ternary content addressable memory 100 is a non-volatile ternary content addressable memory with high stability, a wide memory window, and energy saving.

[0123] Although the present invention has been disclosed as above in the form of implementation modes, it is not intended to limit the present invention. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the attached claims.

Claims

1. A ternary content addressable memory, characterized in that: Include: a first memory unit, comprising a control transistor and a first variable impedance passive element, wherein one end of the first variable impedance passive element is electrically connected to a gate of the control transistor; and A second memory unit is electrically connected to the first memory unit. The second memory unit includes a data transistor and a second variable impedance passive element. The data transistor is connected in series with the control transistor. One end of the second variable impedance passive element is electrically connected to a gate of the data transistor.

2. The ternary content addressable memory according to claim 1, wherein: A source / drain of the control transistor is electrically connected to a bit line, another source / drain of the control transistor is electrically connected to a source / drain of the data transistor, the other source / drain of the control transistor and the source / drain of the data transistor are electrically connected to a matching line, and another source / drain of the data transistor is electrically connected to a data line.

3. The ternary content addressable memory according to claim 2, wherein: The other end of the first variable impedance passive element is electrically connected to a control line, and the other end of the second variable impedance passive element is electrically connected to a word line.

4. The ternary content addressable memory according to claim 2, wherein: The other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to a word line.

5. The ternary content addressable memory according to claim 1, wherein: Each of the first variable impedance passive element and the second variable impedance passive element is a variable resistor, a variable capacitor, or a capacitive element with electron capture capability and a fixed dielectric constant.

6. A memory array circuit, characterized in that: Include: A plurality of ternary content addressable memories are arranged in an array, each of the plurality of ternary content addressable memories comprising: a first memory unit, comprising a control transistor and a first variable impedance passive element, wherein one end of the first variable impedance passive element is electrically connected to a gate of the control transistor; and A second memory unit is electrically connected to the first memory unit. The second memory unit includes a data transistor and a second variable impedance passive element. The data transistor is connected in series with the control transistor. One end of the second variable impedance passive element is electrically connected to a gate of the data transistor.

7. The memory array circuit according to claim 6, wherein: A source / drain of the control transistor is electrically connected to one of a plurality of bit lines, another source / drain of the control transistor is electrically connected to a source / drain of the data transistor, the other source / drain of the control transistor and the source / drain of the data transistor are electrically connected to one of a plurality of match lines, another source / drain of the data transistor is electrically connected to one of a plurality of data lines, the plurality of bit lines and the plurality of data lines are electrically connected to a first circuit, and the plurality of match lines are electrically connected to a second circuit.

8. The memory array circuit according to claim 7, wherein: The other end of the first variable impedance passive element is electrically connected to one of a plurality of control lines, the other end of the second variable impedance passive element is electrically connected to one of a plurality of word lines, the plurality of word lines are electrically connected to a third circuit, and the plurality of control lines are electrically connected to a fourth circuit.

9. The memory array circuit according to claim 7, wherein: The other end of the first variable impedance passive element and the other end of the second variable impedance passive element are both electrically connected to one of a plurality of word lines, and the plurality of word lines are electrically connected to a third circuit.

10. A method for operating a ternary content addressable memory, characterized in that: The ternary content addressable memory comprises a first memory unit and a second memory unit, wherein the first memory unit comprises a control transistor and a first variable impedance passive element, one end of which is electrically connected to a gate of the control transistor, and the second memory unit comprises a data transistor and a second variable impedance passive element, wherein the data transistor is connected in series to the control transistor, and one end of which is electrically connected to a gate of the data transistor. The operation method comprises the following steps: When searching the ternary content addressable memory, an operating voltage is applied to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element, and the current value of a bit line is read to determine whether the first memory unit is in a relevant mode or an irrelevant mode, wherein a source / drain of the control transistor is electrically connected to the bit line, in the irrelevant mode, the channel resistance of the control transistor is a first resistance state, and in the relevant mode, the channel resistance of the control transistor is a third resistance state, and the channel resistance of the data transistor is a second resistance state or a fourth resistance state, the first resistance state is greater than the second resistance state, the second resistance state is greater than the third resistance state, and the third resistance state is greater than the fourth resistance state.

11. The operating method according to claim 10, characterized in that: The other source / drain of the control transistor is electrically connected to a source / drain of the data transistor, the other source / drain of the control transistor and the source / drain of the data transistor are electrically connected to a matching line, and the other source / drain of the data transistor is electrically connected to a data line. The operation method further includes: When the first memory unit is in the correlation mode, a first voltage is applied to the data line, and a second voltage complementary to the first voltage is applied to the bit line, and the information stored in the second memory unit is determined to correspond to a first search result or a second search result based on the voltage value of the matching line, and the second search result is opposite to the first search result.

12. The operating method according to claim 11, characterized in that: The channel resistance of the data transistor is in the fourth resistance state. If the first voltage of the data line is zero voltage and the second voltage of the bit line is the operating voltage, the voltage value of the match line is the zero voltage, and the information stored in the second memory unit corresponds to the first search result. If the first voltage of the data line is the operating voltage and the second voltage of the bit line is the zero voltage, the voltage value of the match line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result.

13. The operating method according to claim 11, characterized in that: The channel resistance of the data transistor is in the second resistance state. If the first voltage of the data line is zero voltage and the second voltage of the bit line is the operating voltage, the voltage value of the matching line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result. If the first voltage of the data line is the operating voltage and the second voltage of the bit line is zero voltage, the voltage value of the matching line is a voltage lower than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the first search result.

14. The operating method according to claim 11, characterized in that: The other end of the first variable impedance passive element is electrically connected to a control line, the other end of the second variable impedance passive element is electrically connected to a word line, and the step of applying the working voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element comprises: The operating voltage is applied to both the control line and the word line.

15. The operating method according to claim 14, characterized in that: Also includes: When programming the first memory cell, a programming voltage is applied to the control line, the word line is floated, the match line is floated, a zero voltage is applied to the bit line, and the data line is floated; and When programming the second memory cell, the control line is floated, the programming voltage is applied to the word line, the match line is floated, the bit line is floated, and the zero voltage is applied to the data line.

16. The operating method according to claim 15, characterized in that: Also includes: When erasing the first memory unit, applying the zero voltage to the control line, floating the word line, floating the match line, applying an erase voltage to the bit line, and floating the data line; and When erasing the second memory unit, the control line is floated, the zero voltage is applied to the word line, the match line is floated, the bit line is floated, and the erase voltage is applied to the data line.

17. The operating method according to claim 15, characterized in that: Also includes: When reading the first memory cell, a read voltage is applied to the control line, the zero voltage is applied to the word line, the zero voltage is applied to the match line, a test voltage is applied to the bit line, and the zero voltage is applied to the data line; as well as When reading the second memory unit, the control line is applied with the zero voltage, the word line is applied with the read voltage, the match line is applied with the zero voltage, the bit line is applied with the zero voltage, and the data line is applied with the test voltage.

18. The operating method according to claim 11, characterized in that: The other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to a word line, and the step of applying the working voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element comprises: The operating voltage is applied to the word line.

19. The operating method according to claim 18, characterized in that: Also includes: When programming the first memory cell and the second memory cell, a programming voltage is applied to the word line, the match line is floated, a zero voltage is applied to the bit line, and the zero voltage is applied to the data line; When erasing the first memory unit, applying the zero voltage to the word line, floating the match line, applying an erase voltage to the bit line, floating the data line; and When erasing the second memory unit, the zero voltage is applied to the word line, the match line is floated, the bit line is floated, and the erasing voltage is applied to the data line.

20. The operating method according to claim 19, characterized in that: Also includes: When reading the first memory cell, a read voltage is applied to the word line, the match line is floated, a test voltage is applied to the bit line, and the zero voltage is applied to the data line; as well as When reading the second memory unit, a read voltage is applied to the word line, the match line is floated, the zero voltage is applied to the bit line, and the test voltage is applied to the data line.

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