Memory

Abstract

The invention discloses a memory. The memory comprises a memory array and an input / output circuit. The storage array comprises at least one storage area, each storage area comprises a plurality of normal storage blocks and redundant standby storage blocks, each normal storage block corresponds to a plurality of columns of column gating signal lines, and the redundant standby storage blocks correspond to a plurality of columns of standby column gating signal lines. The input / output circuit comprises a plurality of normal input / output units and standby input / output units. Wherein when the column addressing address is matched with the replacement address in the replacement address set, the standby input / output unit and the standby column gating signal line corresponding to the replacement address are enabled, so that the damaged storage resource in the normal storage block is replaced by the standby resource in the redundant standby storage block. According to the memory provided by the invention, replacement resources can be remarkably saved when damaged resources of the memory are replaced, so that the purposes of reducing the size of the memory and saving the cost are achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a memory. Background Art

[0002] Dynamic random access memory (DRAM) is a type of random access memory (RAM) commonly used in system memory. Since the storage unit in DRAM has the characteristics of simple structure and high integration, DRAM can usually be integrated into a smaller computer chip to facilitate the use of various types of computer devices. Therefore, DRAM has high application value and development prospects.

[0003] In the manufacturing process of a dynamic random access memory, there may be defects in the memory cells in the row direction or in the column direction, and normal storage operations cannot be performed, and the dynamic random access memory cannot work properly. When a memory cell is defective, a replacement (Redundancy, RDN) technology is used to replace the damaged cell. In the related art, the replacement technology usually sets a redundant replacement memory cell in each memory block to replace the defective memory cell with the redundant replacement memory cell. For example, for the replacement technology in the column direction, it uses a replacement column selection signal line (RYST) to replace the column selection signal line (YST) corresponding to the damaged memory cell for addressing, so as to realize that the redundant replacement memory cell in a certain memory block replaces the defective memory cell.

[0004] However, since the addressing of the memory in the column direction is that multiple different storage blocks in the same storage area are addressed at the same time, that is, the storage cells of the same column address in different storage blocks in the same storage are enabled by the column selection signal line (YST) of the same column address at the same time; therefore, if a storage cell in any storage block is defective and needs to be replaced, when the replacement column selection signal line (RYST) in the storage block is used to replace the column selection signal line (YST) corresponding to the damaged storage cell, the storage cells of the corresponding columns of other storage blocks, due to the change of the addressing address, also need to use the replacement column selection signal line (RYST) of the same address to replace the corresponding column selection signal line, so as to ensure that each storage block corresponds to the same addressing address during addressing. In other words, even if the storage cells in other non-bad blocks of the storage block have no defects, they will be replaced by redundant replacement storage cells due to the design of the addressing method, resulting in a great waste of resources, a high demand for the number of replacement resources, and is not conducive to the integration of devices. Summary of the invention

[0005] The memory provided in the present application aims to save replacement resources when replacing damaged resources in the memory through redundant spare storage blocks, so as to achieve the purpose of reducing the size of the memory and saving costs.

[0006] In order to solve the above technical problems, a technical solution adopted by the present application is to provide a memory, including:

[0007] A storage array includes a normal storage block group and redundant spare storage blocks, wherein the normal storage block group includes a plurality of normal storage blocks, each normal storage block corresponds to a plurality of column selection signal lines, and the redundant spare storage block corresponds to a plurality of column selection signal lines;

[0008] An input-output circuit includes a plurality of normal input-output units and spare input-output units, wherein each normal input-output unit corresponds to a corresponding normal storage block, and the spare input-output unit corresponds to a redundant spare storage block;

[0009] A data transmission circuit comprises a plurality of data transmission units, wherein each data transmission unit is respectively coupled to a corresponding normal input-output unit and a spare input-output unit; wherein each data transmission unit selectively couples one of the corresponding normal input-output unit and the spare input-output unit to a data transmission bus based on bad storage block indication information, so as to select storage resources of a normal storage block corresponding to the normal input-output unit or redundant spare storage resources of a redundant spare storage block corresponding to the spare input-output unit,

[0010] In response to the column addressing address matching the replacement address in the replacement address set, bad memory block indication information is generated.

[0011] In some embodiments, the memory further includes a normal column decoding circuit, wherein, when performing column addressing, the normal column decoding circuit enables the column selection signal lines of the same numbered columns in multiple normal storage blocks corresponding to the column addressing address, so that the storage resources in the multiple normal storage blocks corresponding to the column selection signal lines of the same numbered columns are column addressed simultaneously.

[0012] In some embodiments, the memory further includes a redundant column decoding circuit, wherein, when performing column addressing, the redundant column decoding circuit is used to compare the column addressing address with a replacement address in a replacement address set, and in response to the column addressing address matching the replacement address, the redundant column decoding circuit generates bad memory block indication information and enables a spare column enable signal line based on the replacement address.

[0013] In some embodiments, when the memory performs column addressing, the normal memory block with damaged memory resources is normally column addressed, and redundant replacement column addressing is performed on the redundant spare memory block through a redundant column decoding circuit.

[0014] In some embodiments, the memory array includes a plurality of memory areas in a word line direction, wherein each memory area includes a normal memory block group and a redundant spare memory block, and the redundant column decoding circuit includes:

[0015] A first redundant column decoding unit receives replacement address set information and storage area indication information, and selects bad storage block indication information and a plurality of replacement addresses corresponding to the current storage area based on the replacement address set information and the storage area indication information, wherein the replacement address set information includes storage area information where the bad storage block is located, bad storage block information, and bad storage block replacement address;

[0016] A second redundant column decoding unit is coupled to the first redundant column decoding unit to receive bad storage block indication information and a replacement address in the current storage area, and receive a column addressing address; compares the column addressing address with the replacement address to generate replacement indication information and current output bad storage block indication information;

[0017] The output unit is coupled to the second redundant column decoding unit to receive the replacement indication information and the clock signal to sequentially output the redundant spare column strobe enable signal based on the clock signal, thereby enabling the corresponding spare column strobe signal line.

[0018] In some embodiments, the second redundant column decoding unit comprises:

[0019] a plurality of first logic gate circuits, wherein each of the first logic gate circuits receives the column addressing address and a corresponding replacement address respectively, so as to compare the column addressing address with the replacement address respectively;

[0020] Wherein, each first logic gate circuit comprises a logic XOR gate circuit.

[0021] In some embodiments, the output unit includes:

[0022] A plurality of second logic gate circuits, wherein each second logic gate circuit is respectively coupled to an output terminal of a corresponding first logic gate circuit to receive a replacement indication signal and a clock signal to output a corresponding redundant spare column gating enable signal based on the clock signal;

[0023] Wherein, each second logic gate circuit comprises a logic NAND gate circuit.

[0024] In some embodiments, each data transmission unit in the data transmission circuit is also respectively coupled to the redundant column decoding circuit to receive the current output bad memory block indication information, and coupled to the data transmission bus;

[0025] Each data transmission unit selectively couples the corresponding normal input and output unit and the spare input and output unit to the data transmission bus by selecting one of the common terminals of the normal input and output units or the spare common terminals of the redundant spare input and output units based on the currently output bad storage block indication information.

[0026] In some embodiments, the data transmission unit includes:

[0027] A third logic gate circuit includes a first transmission gate and a second transmission gate, wherein the first transmission gate and the second transmission gate receive current output bad storage block indication information and current output bad storage block indication inverse information respectively;

[0028] The first transmission gate is also coupled to a corresponding normal input-output unit to determine whether to couple the corresponding normal input-output unit to the data transmission bus based on the current output bad storage block indication information and the current output bad storage block indication inverse information;

[0029] The second transmission gate is further coupled to the spare input and output unit to determine whether to couple the spare input and output unit to the data transmission bus based on the current output bad memory block indication information and the current output bad memory block indication inverse information.

[0030] In some embodiments, the normal input-output unit and the standby input-output unit respectively include:

[0031] The memory array end input / output line and the memory array end input / output complementary line are used to couple the bit line and the complementary bit line of the memory array respectively;

[0032] The common input / output line and the common input / output complementary line are used to couple the storage array end input / output line and the storage array end input / output complementary line respectively;

[0033] The end read / write control unit is arranged between the storage array end input / output line and the storage array end input / output complementary line, and the common input / output line and the common input / output complementary line.

[0034] In some embodiments, each column of the selection signal line is respectively coupled to a preset number of bit lines, and each bit line is respectively coupled to a corresponding column of memory cells;

[0035] Each spare column selection signal line is respectively coupled to a preset number of spare bit lines, and each spare bit line is respectively coupled to a corresponding column of redundant spare memory cells.

[0036] In some embodiments, in response to a column addressing address matching a replacement address in a replacement address set, a spare input-output unit and a spare column enable signal line corresponding to the replacement address are enabled, wherein the enabled spare column enable signal line enables redundant spare storage cells coupled to a preset number of spare bit lines coupled thereto to the spare input-output unit based on replacement indication information.

[0037] In some embodiments, each memory includes a normal memory block group and a redundant spare memory block, the normal memory block group includes h normal memory blocks, each normal memory block corresponds to m column selection signal lines, and each column selection signal line is respectively coupled to n bit lines;

[0038] The redundant spare memory block corresponds to p spare column selection signal lines, and each spare column selection signal line is respectively coupled to n spare bit lines.

[0039] In some embodiments, the memory includes dynamic random access memory, ferroelectric random access memory, phase change random access memory, and pseudo-static random access memory.

[0040] The memory provided by the embodiment of the present application concentrates redundant spare storage resources on redundant spare storage blocks. When a storage unit is damaged, one of a normal input-output unit and a spare input-output unit can be selected through bad storage block indication information to be coupled to a data transmission bus, so as to replace the defective storage unit. Compared with the prior art of replacing a column selection signal line (such as YST) with a spare column selection signal line (such as RYST), the present application is improved to replace an input-output unit (such as LIO and DMIO) with a spare input-output unit (such as LIOR and DMIOR) during the process of replacing a damaged storage unit, so that replacement resources can be significantly saved during replacement, such as significantly saving the number of replacement bit lines (redundancy bitlines), so as to achieve the purpose of reducing the circuit area of ​​the memory and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0043] Figure 2 It is a schematic diagram of the circuit structure of a normal storage block and a normal input and output unit of a memory provided in an embodiment of the present application;

[0044] Figure 3 It is a schematic diagram of the circuit structure of a redundant spare storage block and a spare input and output unit of a memory provided in an embodiment of the present application;

[0045] Figure 4 It is a partial structural diagram of a memory provided by an embodiment of the present application;

[0046] Figure 5 It is a structural schematic diagram of a redundant column decoding circuit of a memory provided in an embodiment of the present application;

[0047] Figure 6is another structural schematic diagram of a memory provided by an embodiment of the present application;

[0048] Figure 7 It is a structural schematic diagram of a data transmission circuit of a memory provided in an embodiment of the present application;

[0049] Figure 8 is another structural schematic diagram of a memory provided in an embodiment of the present application;

[0050] Fig. 9 It is a structural schematic diagram of a memory in the prior art related to the embodiments of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0053] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0054] In some embodiments, see Figure 1 , Figure 1 Schematic diagram of a memory structure provided by an embodiment of the present application. Figure 1 As shown, a memory provided by an embodiment of the present application includes a memory array 100, an input-output circuit 200, and a data transmission circuit 500. The memory array 100 includes a normal memory block group 111 and a redundant spare memory block (MatR) 112. The normal memory block group includes a plurality of normal memory blocks (Mat), each normal memory block Mat corresponds to a plurality of column selection signal lines (YST) 113, and the redundant spare memory block 112 corresponds to a plurality of column selection signal lines (RYST) 114. The input-output circuit 200 includes a plurality of normal input-output units 210 and spare input-output units 220, wherein each normal input-output unit 210 corresponds to a corresponding normal memory block Mat, and the spare input-output unit 220 corresponds to the redundant spare memory block 112. The data transmission circuit 500 includes a plurality of data transmission units 510 (DC), wherein each data transmission unit 510 is respectively coupled to a corresponding normal input-output unit 210 and a spare input-output unit 220; wherein each data transmission unit 510 selectively couples one of the corresponding normal input-output unit 210 and the spare input-output unit 220 to the data transmission bus 600 based on the bad storage block indication information, so as to select the storage resource of the normal storage block Mat corresponding to the normal input-output unit 210 or the redundant spare storage resource of the redundant spare storage block 112 corresponding to the spare input-output unit 220. wherein the bad storage block indication information is generated in response to the column addressing address matching the replacement address in the replacement address set.

[0055] In some embodiments, the input-output circuit 200 includes a plurality of normal input-output units 210 and a spare input-output unit 220. After the normal storage block Mat is opened by the corresponding column selection signal line 113, it is connected to the corresponding normal input-output unit 210. Similarly, after the redundant spare storage block 112 is opened by the corresponding spare column selection signal line 114, it is connected to the redundant spare storage block 112 corresponding to the spare input-output unit 220. Through the above structure, after at least one normal storage block Mat is opened by the corresponding column selection signal line 113, the data in the memory enters the corresponding data transmission unit 510 in the data transmission circuit 500 through the input-output circuit 200, and then after the judgment of the data transmission unit 510, it is decided whether to connect 600 with the data transmission bus, so as to exchange data with the outside world.

[0056] Based on the above structure, when the column addressing address matches the replacement address in the replacement address set, the spare input and output unit 220 and the spare column selection signal line 114 corresponding to the corresponding replacement address are enabled, so that the spare resources in the redundant spare storage block 112 replace the damaged storage resources in the normal storage block Mat. It should be noted that the replacement address in the replacement address set is obtained by a pre-set damaged resource detection test and stored in a programmable memory, providing the damaged resource address that needs to be replaced for this application. Through the above method, the damaged storage resource in the normal storage block Mat can be replaced by the spare resource in the redundant spare storage block 112. Through the matching of the addressing address and the replacement address, the redundant spare storage block 112 that needs to be replaced into the normal storage block Mat can be placed in the corresponding addressing address, so that the damaged resource replacement can be completed under the condition of only calling the replacement resource in the redundant spare storage block 112.

[0057] In some embodiments, see Figure 2-3 , Figure 2 It is a circuit structure diagram of a normal storage block Mat and a normal input-output unit 210 of a memory provided in an embodiment of the present application; Figure 3 1 is a circuit structure diagram of a redundant spare storage block 112 and a spare input-output unit 220 of a memory provided in an embodiment of the present application. A normal storage block Mat generally includes at least one storage cell (Cell), at least one bit line, at least one word line, a sensitive amplifier unit (SA) and an equalization circuit (EQ). Specifically, when the random access memory performs a read operation, in a normal storage block Mat, the information of at least one storage cell is first opened by a word line signal and transmitted to the bit line, and then amplified by the sensitive amplifier unit and adjusted by the equalization circuit, and then opened by the signal of the column selection signal line 113 and transmitted to the normal input-output unit 210. The redundant spare storage block 112 also includes at least one storage element, at least one bit line, at least one word line, an amplifier circuit and an equalization circuit. Similarly, when the random access memory performs a read operation, in a redundant spare storage block 112, the information of at least one storage cell is first opened by a word line signal and transmitted to the bit line, and then amplified by the sensitive amplifier unit and adjusted by the equalization circuit, and then opened by the signal of the spare column selection signal line 114 and transmitted to the spare input-output unit 220. Through the above structure, the circuit structure within at least one normal storage block Mat is the same as the circuit structure of the redundant spare storage block 112, so that the replacement resources taken out from the redundant spare storage block 112 can correspondingly replace the damaged resources within at least one normal storage block Mat, thereby ensuring that the normal storage block Mat carrying the damaged resources can work normally after being replaced.

[0058] In some embodiments, at least one normal storage block Mat corresponds to a plurality of column selection signal lines 113, and the redundant spare storage block 112 corresponds to a plurality of spare column selection signal lines 114. It should be noted that the number of column selection signal lines 113 corresponds to the number of storage cell groups to be controlled in at least one normal storage block Mat, and the number of spare column selection signal lines 114 corresponds to the number of redundant storage cell groups to be controlled in the redundant spare storage block 112. For example, if the number of normal storage cell groups to be controlled in each normal storage block Mat is m, then the corresponding column selection signal lines are m. The specific number of columns of normal storage cell groups and column selection signal lines 113 is not limited here. The number of redundant spare storage cell groups can be p, and the number of spare column selection signal lines 114 corresponds to p. The specific number of columns of redundant spare storage cell groups and spare column selection signal lines 114 is not limited here. It should be noted that the number p of spare column enable signal lines 114 is less than or equal to the number m of column enable signal lines 113 to ensure that the number of spare column enable signal lines 114 does not exceed the number of column enable signal lines 113 to prevent excess replacement resources.

[0059] It should be noted that the number of columns of storage cells included in each normal storage cell group and redundant storage cell group is equal, which can be n columns, where n is a positive integer. The specific number of columns of storage cells included in the normal storage cell group and redundant storage cell group is not limited here.

[0060] In some embodiments, Figure 4 Schematic diagram of a partial structure of a memory provided by an embodiment of the present application. Figure 4 As shown, the memory provided by the embodiment of the present application further includes a normal column decoding circuit 300. When performing column addressing, the normal column decoding circuit 300 enables the column selection signal line 113 of the same number column in the multiple normal storage blocks Mat corresponding to the column addressing address, so that the storage resources in the multiple normal storage blocks Mat corresponding to the column selection signal line 113 of the same number column are simultaneously column addressed. For example, when the number of storage blocks in the multiple normal storage blocks Mat is 8, each storage block can be Mat0 to Mat7.

[0061] In some embodiments, please refer to Figure 4When the normal column decoding circuit 300 performs column addressing, since the column number set used by multiple normal storage blocks Mat is the same, the column selection signal lines 113 of the same number column in multiple normal storage blocks Mat will be selected by the decoding circuit at the same time. For example, when the first column in the first normal storage block Mat1 of the column addressing address is selected, the column selection signal line 113 corresponding to the first column in the first normal storage block Mat1 is selected; at the same time, the first columns in the remaining normal storage blocks Mat are all selected, and the column selection signal lines 113 corresponding to the first columns in the remaining normal storage blocks Mat are all selected. In this case, when multiple normal storage blocks Mat perform a read operation, by column addressing a certain specific address, the column selection signal line 113 corresponding to the column addressing address in all normal storage blocks Mat can be selected, and the selected column selection signal line 113 opens the bit line controlled by the corresponding column selection signal line 113, so that the signal in the storage unit passes through the bit line 115 controlled by the corresponding column selection signal line 113, thereby entering the normal input and output unit 210 to be read by other devices. This method can read out the information of multiple normal storage blocks Mat through one column addressing, thereby improving the information reading efficiency of the memory.

[0062] In some embodiments, see Figure 5 , Figure 5 1 is a schematic diagram of the structure of a redundant column decoding circuit 400 of a memory provided in an embodiment of the present application. The memory provided in an embodiment of the present application further includes a redundant column decoding circuit 400. When performing column addressing, the redundant column decoding circuit 400 is used to compare the column addressing address with the replacement address in the replacement address set, and in response to the column addressing address matching the replacement address, the redundant column decoding circuit 400 generates the bad memory block indication information and enables the spare column selection signal line based on the replacement address.

[0063] In some embodiments, when the redundant column decoding circuit 400 performs column addressing, the redundant column decoding circuit 400 generates a replacement address that can be used for comparison with the column addressing address according to the bad storage block indication information in the replacement address set. When the replacement address matches the column addressing address, the redundant column decoding circuit 400 determines the location of the damaged resource that needs to be replaced and enables the spare column selection signal line 114. The address of the enabled spare column selection signal line 114 corresponds to the column selection signal line 113 carrying the replacement address, so that the spare resources in the redundant spare storage block 112 can replace the damaged resources corresponding to the replacement address. In this way, by comparing with the column addressing address, the bad memory block indication information in the replacement address set can be converted by the redundant column decoding circuit 400 into a control signal that can enable the spare column strobe signal line 114, thereby opening the spare resources in the redundant spare memory block 112 and coupling to the corresponding spare input and output unit 220 in the redundant spare memory block 112, so as to allow the normal input and output unit 210 corresponding to the damaged part to be replaced in the data transmission circuit 500 and connected to the data transmission bus 600. In one embodiment, when the spare column strobe signal line 114 and the column strobe signal line 113 are equal, the address of the non-enabled spare column strobe signal line 114 also corresponds to the address of the column strobe signal line 113 that does not carry the replacement address, that is, all addresses of the spare column strobe signal line 114 and the column strobe signal line 113 correspond to each other. In this case, only the enabled spare column selection signal line 114 can open the spare resources in the redundant spare storage block 112 and couple to the corresponding spare input-output unit 220 in the redundant spare storage block 112, so as to subsequently replace the normal input-output unit 210 corresponding to the damaged part in the data transmission circuit 500 to access the data transmission bus 600.

[0064] In some embodiments, when performing column addressing, the normal memory block Mat having the damaged memory resource is normally column addressed, and redundant replacement column addressing is performed on the redundant spare memory block 112 through the redundant column decoding circuit 400 .

[0065] It should be noted that when performing column addressing, the first type column enable signal line 113 corresponding to the normal storage block Mat with damaged storage resources will not be replaced by the first type spare column enable signal line 114. Here, it is only explained that both the normal storage block Mat and the redundant spare storage block 112 are column addressed.

[0066] In some embodiments, the memory array includes multiple memory areas in the word line direction, each memory area includes multiple normal memory blocks Mat and redundant spare memory blocks 112, wherein the redundant column decoding circuit 400 includes: a first redundant column decoding unit 410, a second redundant column decoding unit 420 and an output unit 430.

[0067] In some embodiments, the first redundant column decoding unit 410 receives replacement address set information 411 and storage area indication information (CFRT<>), and selects bad storage block indication information (MLATCT<>) and multiple replacement addresses (CRCAT<>) in the corresponding current storage area based on the replacement address set information 411 and the storage area indication information, wherein the replacement address set information 411 includes the storage area information (EFBIT<>) where the bad storage block is located, bad storage block information (EFLATRT<>) and bad storage block replacement address (EFLATCT<>).

[0068] In this embodiment, the first redundant column decoding unit 410 has a latching function. When the first redundant column decoding unit 410 is working, the first redundant column decoding unit 410 latches the received address set information, that is, the first redundant column decoding unit 410 latches the storage area information, bad storage block information and bad storage block replacement address where the damaged resource is located. Through the storage area indication information, the damaged resource information latched in the first redundant column decoding unit 410 is selected to obtain the replacement information corresponding to the storage area 110 where the word line currently in the working state is located in the latched damaged resource information. In other words, through the first redundant column decoding unit 410, the damaged resource information is converted into a plurality of replacement addresses that match the damaged resource addresses in the normal storage block Mat, so that the subsequent replacement resources can replace the damaged part in the normal storage block Mat. Among them, since the replacement resources are located in the redundant spare storage unit group in the redundant spare storage block 112, the number of replacement addresses should not exceed the number of groups of the redundant spare storage unit group in the redundant spare storage block 112. For example, the number of replacement resources may be 32, 64, 128, or x, where x is a positive integer and x is less than or equal to p. The specific number of replacement resources is not limited herein.

[0069] It should be noted that the storage area information of the bad storage block, the bad storage block information and the bad storage block replacement address received by the first redundant column decoding unit 410 are from other storage structures, such as a one-time programmable memory (eFuse). Before the memory is used, the memory will perform a damaged resource detection, and the detection result information generated when detecting the damaged resource will be stored in other storage structures. The detection result includes the replacement address information, that is, the storage area information of the bad storage block, the bad storage block information and the bad storage block replacement address.

[0070] In some embodiments, please refer to Figure 5 The second redundant column decoding unit 420 is coupled to the first redundant column decoding unit 410 to receive the bad storage block indication information and the replacement address in the current storage area 110, and receive the column addressing address; compare the column addressing address and the replacement address to generate the replacement indication information (CRFGB<>) and the current output bad storage block indication information (MFGB<>).

[0071] In this embodiment, the generated replacement indication information is used to control the spare column selection signal line 114 to select the replacement resource. In cooperation with the currently output bad memory block information, the damaged resource address indicated by the replacement indication information is the damaged resource part in the normal memory block Mat.

[0072] It should be noted that the column addressing address received by the second redundant decoding unit 420 is generated by column addressing the normal storage block Mat. If multiple normal storage blocks Mat are addressed at this time, the column selection signal line 113 corresponding to the same number column of each different normal storage block Mat is selected, so that the storage resources in the multiple normal storage blocks Mat corresponding to the column selection signal line 113 of the same number column are simultaneously column addressed. In this case, since the column selection signal lines 113 of the multiple same number columns select the storage resources of the corresponding columns in the multiple normal storage blocks Mat, the replacement indication information output by the second redundant decoding unit 420 will not be able to determine the normal storage block Mat number of the damaged storage resource. At this time, the current output bad storage block indication information (MFGB<>) is required to indicate the specific damaged resource location, so that the replacement resource can replace the target damaged resource area.

[0073] In some embodiments, please refer to Figure 5 The output unit 430 is coupled to the second redundant column decoding unit 420 to receive the replacement indication information and the clock signal (CYCLK<>) to sequentially output the redundant spare column enable signal (RYST<>) based on the clock signal, thereby enabling the corresponding spare column enable signal line 114.

[0074] In some embodiments, please refer to Figure 5 The second redundant column translation unit 420 includes a plurality of first logic gate circuits 421, wherein each first logic gate circuit 421 receives a column address and a corresponding replacement address respectively to compare the column address and the replacement address respectively. Each first logic gate circuit 421 includes a logic XOR gate circuit.

[0075] In this embodiment, the column addressing address and the replacement address are compared in the following manner: when the two addresses are the same, the flag signal of the replacement indication information generated is 0, indicating that the circuit needs a replacement operation. When the two addresses are different, the flag signal of the replacement indication information generated is 1, indicating that the circuit does not need a replacement operation. For example, the replacement indication information is represented as: CRFGB <0> =0, it means that the 0th replacement information is used.

[0076] In some embodiments, the output unit 430 includes a plurality of second logic gate circuits 431, wherein each second logic gate circuit 431 is respectively coupled to an output end of a corresponding first logic gate circuit 421 to receive a replacement indication signal and a clock signal to output a corresponding redundant spare column gating enable signal based on the clock signal. Each second logic gate circuit 431 includes a logic NAND gate circuit.

[0077] In this embodiment, when the flag signal of the replacement indication information is 0, the redundant spare column strobe enable signal is enabled through the NAND gate judgment in conjunction with the clock signal, and the spare column strobe signal line 114 selects the replacement resource. When the flag signal of the replacement indication information is 1, the redundant spare column strobe enable signal is not enabled through the NAND gate judgment in conjunction with the clock signal, and the spare column strobe signal line 114 does not select the replacement resource.

[0078] In some embodiments, see Figure 6-7 , Figure 6 is another structural schematic diagram of a memory provided by an embodiment of the present application; Figure 7 Schematic diagram of a data transmission circuit 500 of a memory provided in an embodiment of the present application. Figure 6-7 As shown, each data transmission unit 510 in the data transmission circuit 500 in the memory provided in the embodiment of the present application is also coupled to the redundant column decoding circuit 400 to receive the current output bad memory block indication information, and coupled to the data transmission bus 600. Based on the current output bad memory block indication information, each data transmission unit 510 selects to connect to one of the common end (DMIO<>) of the normal input-output unit 210 or the spare common end (DMIOR<>) of the redundant spare input-output unit 220 through the selection signal (MFGB<>), so as to selectively couple the corresponding normal input-output unit 210 and one of the spare input-output unit 220 to the data transmission bus 600.

[0079] In this embodiment, continue to refer to Figure 6-7The data transmission unit 510 receives the input and output information of the normal storage block Mat of the normal input and output unit 210 and the input and output information of the redundant spare storage block 112 of the spare input and output unit 220, and according to the current output bad storage block indication information, determines one of the input and output information of the normal storage block Mat and the input and output information of the redundant spare storage block 112 to be transmitted to the data transmission bus 600. For example, when the first normal input-output unit 210 of the first normal storage block Mat is coupled to the data transmission unit 510, if the current output bad storage block indication information is 0, a column of storage cells coupled to the first normal input-output unit 210 in the first normal storage block Mat is damaged, the first normal input-output unit 210 in the first normal storage block Mat is disconnected from the data transmission bus 600, and the first spare input-output unit 220 in the redundant spare storage block 112 is coupled to the transmission bus 600, so that the first spare input-output unit 220 in the redundant spare storage block 112 replaces the first normal input-output unit 210 in the first normal storage block Mat; if the current output bad storage block indication information is 1, a column of storage cells coupled to the first normal input-output unit 210 in the first normal storage block Mat works normally, the first normal input-output unit 210 in the first normal storage block Mat is coupled to the data transmission bus 600, and the first spare input-output unit 220 in the redundant spare storage block 112 is disconnected from the data transmission bus 600, and no replacement occurs at this time. Through the data transmission circuit 500, the data transmission bus 600 can select the normal input-output unit 210 and the spare input-output unit 220 through the logic circuit to ensure that the replacement resource coupled to the spare input-output unit 220 can replace a column of storage units carrying damaged parts coupled to the normal input-output unit 210, thereby completing the replacement of the replacement resource and the damaged resource at a specific address.

[0080] In some embodiments, please refer to Figure 7 , each data transmission unit 510 includes a third logic gate circuit 510a. The third logic gate circuit includes a first transmission gate 511 and a second transmission gate 512. The first transmission gate 511 and the second transmission gate 512 receive the current output bad storage block indication information and the current output bad storage block indication inverse information respectively. The first transmission gate 511 is also coupled to a corresponding normal input-output unit 210 to determine whether to couple the corresponding normal input-output unit 210 to the data transmission bus 600 based on the current output bad storage block indication information and the current output bad storage block indication inverse information. The second transmission gate 512 is also coupled to the spare input-output unit 220 to determine whether to couple the spare input-output unit 220 to the data transmission bus 600 based on the current output bad storage block indication information and the current output bad storage block indication inverse information.

[0081] In this example, please continue to refer to Figure 7 , each data transmission unit works as follows: Assuming there are 8 normal storage blocks Mat, when the 0th normal storage block Mat0 has damaged resources, if the current output bad storage block indication information MFGB <0> =0,ˉMFGB <0> It is the inverse signal of the current output bad storage block indication information, the level is high, that is, MFGB <0> = 1. At this time, the current output bad storage block indication information MFGB <0> = 0 and the inverse signal of the current output bad storage block indication information ˉ MFGB <0> =1 respectively controls the high level conduction switch and the low level conduction switch of the first transmission gate in the third logic gate circuit 510a, so that the high level conduction switch is turned off and the low level conduction switch is also turned off, thereby causing the common terminal (DIMO0) of the 0th normal input and output unit 210 and the data transmission bus 600 to be disconnected; at the same time, the current output bad storage block indication information MFGB <0> = 0 and the inverse signal of the current output bad storage block indication information ˉ MFGB <0> =1 respectively controls the low level conduction switch and the high level conduction switch of the second transmission gate 512 in the third logic gate circuit 510a, so that the low level conduction switch is closed, and the high level conduction switch is also closed, so that the standby common terminal (DMIOR) of the standby input and output unit 220 is connected to the data transmission bus 600. In this case, the 1st to 7th normal storage blocks Mat1-7 have no damaged resources, so the 1st to 7th normal storage blocks Mat1-7 are all connected to the data transmission bus 600. In this way, only the standby common terminal of the 0th normal input and output unit 210 is replaced with a replacement resource, and the rest of the data transmission remains unchanged, so that the damaged resource replacement in the normal storage block Mat can be completed.

[0082] In some embodiments, see Figure 2-3 and Figure 6 Each normal input-output unit 210 and spare input-output unit 220 includes: a storage array end input-output line (LIOT) and a storage array end input-output complementary line (LIOB), which are used to couple the bit line and complementary bit line of the storage array respectively; a common input-output line (MIOT) and a common input-output complementary line (MIOB), which are used to couple the storage array end input-output line and the storage array end input-output complementary line respectively. Each normal input-output unit 210 and spare input-output unit 220 also includes a terminal read-write control unit (LSA), which is arranged between the storage array end input-output line and the storage array end input-output complementary line, and the common input-output line and the common input-output complementary line.

[0083] In some embodiments, please refer to Figure 2-3, one end of the storage array terminal input / output line and the storage array terminal input / output complementary line are respectively coupled to the storage array bit line and the storage array complementary bit line on the equalizer. The column selection signal line 113 controls the conduction state of the storage array bit line and the storage array terminal input / output line, and at the same time controls the conduction state of the storage array complementary bit line and the storage array terminal input / output complementary line. In addition, the storage array terminal input / output line and the storage array terminal input / output complementary line are respectively coupled to the common input / output line and the common input / output mutually complementary line through the terminal read / write control unit. In this case, under the control of the column selection signal line 113, the storage array information can be selectively transmitted to the storage array terminal input / output line and the storage array terminal input / output complementary line, and information is exchanged with the outside world through the common input / output line and the common input / output mutually complementary line, thereby completing data transmission.

[0084] Please refer to Figure 2-3 and Figure 6 The storage array end input / output line and the storage array end input / output complementary line can be uniformly represented as the storage array end (LIO) of the normal input / output unit 210 in the normal input / output unit 210; and can be uniformly represented as the spare storage array end (LIOR) of the spare input / output unit 220 in the spare input / output unit 220. The common input / output line and the common input / output complementary line can be uniformly represented as the common end (DIMO) of the normal input / output unit 210 in the normal input / output unit 210; and can be uniformly represented as the spare common end (DMIOR) of the spare input / output unit 220 in the spare input / output unit 220.

[0085] In some embodiments, see Figure 8 , Figure 8 is another structural diagram of a memory provided by an embodiment of the present application. Figure 8 As shown, each column selection signal line 113 is respectively coupled to a preset number of bit lines 115, each bit line 115 is respectively coupled to a corresponding column of memory cells. Each spare column selection signal line 114 is respectively coupled to a preset number of spare bit lines 116, each spare bit line 116 is respectively coupled to a corresponding column of redundant spare memory cells.

[0086] In some embodiments, continue to refer to Figure 8 Each column selection signal line 113 is coupled to a preset number of bit lines 115, that is, each column selection signal line 113 is coupled to a group of bit lines 115, and a column of memory cells in a normal memory block Mat is controlled by the bit lines 115. In other words, the number of bit lines 115 is determined by the number of memory cell columns of the memory cell group on the corresponding column in the normal memory block Mat that each column selection signal line 113 needs to control. Figure 8For example, if a column selection signal line 113 needs to control n columns of memory cells in a memory cell group on a corresponding column in a normal memory block Mat, then the number of bit lines 115 that need to be coupled to the memory cells in the memory cell group on each column is n. In this case, a column selection signal line 113 controls the selection signals of the corresponding n columns of memory cells in a memory cell group on the corresponding column by controlling the signals of the n bit lines 115, that is, it determines whether the memory array bit lines of the n columns of memory cells in a memory cell group on the corresponding column are connected to the input and output lines at the end of the memory array, and at the same time determines whether the memory array complementary bit lines are connected to the input and output complementary lines at the end of the memory array. The coupling method of each spare column selection signal line 114 corresponding to the coupling of a preset number of spare bit lines 116 is the same as the coupling method of each column selection signal line 113 corresponding to the coupling of a preset number of bit lines 115, which will not be repeated here.

[0087] It should be noted that Figure 8 For example, the number of normal memory blocks Mat is h, and each normal memory block Mat corresponds to m column selection signal lines 113, and each column selection signal line 113 controls n columns of memory cells through n bit lines 115; the number of redundant spare memory blocks 112 is 1, and each redundant spare memory block 112 corresponds to p spare column selection signal lines 114, and each spare column selection signal line 114 controls n columns of spare memory cells through n spare bit lines 116. The number of memory cell columns of the memory cell group on the corresponding column in the normal memory block Mat that the column selection signal line 113 needs to control and the number of bit lines 115 that the column selection signal line 113 needs to be coupled to are not limited here. Similarly, the spare column selection signal line 114 controls the selection signal of the corresponding redundant spare memory cells in the redundant spare memory cell group on the corresponding column by controlling the signals of the preset number of spare bit lines 116, that is, determines whether the redundant spare memory array bit lines of the redundant spare memory cells in the redundant spare memory cell group on the corresponding column are connected to the redundant spare memory array end input and output lines, and also determines whether the redundant spare memory array complementary bit lines are connected to the redundant array memory array end input and output complementary lines. The method for determining the number of spare bit lines 116 is the same as the method for determining the number of bit lines 115, and will not be repeated here.

[0088] In some embodiments, the number p of the spare column enable signal lines 114 is less than or equal to the number m of the column enable signal lines.

[0089] It should be noted that when the replacement resource replaces the damaged part of the normal storage block Mat, the spare input-output unit 220 and the corresponding spare column selection signal line 114 are enabled, and the spare resources in the redundant spare storage block 112 replace the damaged storage resources in the normal storage block Mat. In the replacement process, the spare column selection signal line 114 replaces the damaged storage resources in the normal storage block Mat with the spare resources in the redundant spare storage block 112 as needed, that is, one spare column selection signal line 114 can only be used to replace the normal input-output unit 210 controlled by one column selection signal line 113 in the normal storage block Mat with one spare input-output unit 220. Therefore, each time the spare input-output unit 220 is replaced with the normal input-output unit 210, one column selection signal line 113 is replaced by one spare column selection signal line 114. In addition, based on the replacement address in the replacement address set being the address of the damaged resource in the normal storage block Mat, the replacement address in the replacement address set is included in the column addressing address, that is, the replacement address in the replacement address set is one or more addresses in the column addressing address. In this case, based on the control range of the column selection signal line 113 covering all addresses available for column addressing in the normal storage block Mat, the replacement range of the spare column selection signal line 114 should not exceed all addresses available for column addressing in the normal storage block Mat, that is, the number of corresponding column addresses that the spare column selection signal line 114 can select is within the number range of column addresses corresponding to the column selection signal line 113. If the number p of the spare column selection signal lines 114 should be greater than the number m of the column selection signal lines 113, the excess part of the number of spare column selection signal lines 114 will not be used. In order to save replacement resources and spare column selection signal lines 114, the number p of spare column selection signal lines 114 should be less than or equal to the number m of column selection signal lines 113.

[0090] In some prior art embodiments, see Fig. 9 , Fig. 9 Schematic diagram of a memory structure in the prior art related to the embodiment of the present application. Fig. 9 As shown in FIG. 1 , the memory of the prior art does not have a redundant spare memory block 112, and its redundant replacement unit is set in each normal memory block Mat, that is, the column selection signal line 113 and its controlled memory cell group and the spare column selection signal line 114 and its controlled memory cell group are all set in the normal memory block Mat. When the damaged part in the normal memory block Mat needs to be replaced, the resource for replacing the damaged part comes from each normal memory block Mat. Fig. 9For example, the number of normal storage blocks Mat is h, and the number of column selection signal lines 113 corresponding to each normal storage block Mat is m, and each column selection signal line 113 controls n columns of storage units through n bit lines 115. Each normal storage block Mat is also equipped with y spare column selection signal lines 114, and each spare column selection signal line 114 controls n columns of spare storage units through n spare bit lines 116. Specifically, when the replacement resource replaces the damaged part of the normal storage block Mat, the spare column selection signal line 114 in the same normal storage block Mat as the damaged part to be replaced replaces the column selection signal line 113 corresponding to the damaged part. Among them, since the normal column decoding unit 300 performs column addressing for all normal storage blocks Mat at the same time when addressing, when the damaged part in a normal storage block Mat needs to be replaced, the damaged part in the normal storage block Mat is column addressed, and at the same time, the storage resources corresponding to the damaged column address in each normal storage block Mat are also column addressed. Each column selection signal line 113 corresponding to the addressed storage resource in each normal storage block Mat is replaced by the corresponding spare column selection signal line 114 in each normal storage block Mat, then the bit line 115 controlled by each column selection signal line 113 corresponding to the addressed storage resource and its corresponding storage cell group enter the failure state, and each spare bit line 116 controlled by the spare column selection signal line 114 for replacement and its corresponding redundant spare storage cell group are enabled, thereby completing the replacement. It should be noted that when each replacement is performed, even if only one first type spare column selection signal line 114 in the redundant spare storage block 112 is needed to replace the damaged resource, all replacement resources will be called.

[0091] Specifically, if a damaged resource is replaced by using the prior art, since each normal storage block Mat has y spare column selection signal lines 113, the required storage resources are y*h*n in total. The y spare column selection signal lines 114 in the prior art correspond to p spare column selection signal lines 114 in the redundant spare storage block 112 in the present application, and the present embodiment only needs to call the storage resources corresponding to the p spare column selection signal lines 114 in the redundant spare storage block 112 during replacement, that is, the required storage resources are p*n in total.

[0092] Therefore, compared with the prior art, the memory provided in the embodiment of the present application can significantly save replacement resources, namely column storage units, when replacing, which helps to reduce the number of word lines and bit lines required when packaging the memory circuit, so as to achieve the purpose of reducing the memory size and saving costs.

[0093] In some embodiments, the memory provided by the embodiments of the present application includes a dynamic random access memory, a ferroelectric random access memory, a high-frequency dynamic random access memory, a multi-slot dynamic random access memory, and a synchronous dynamic random access memory. The storage array 100 and the input-output circuit 200 provided by the embodiments of the present application can be used for the above-mentioned various types of memories to achieve replacement of damaged memory resources with fewer replacement resources.

[0094] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: A storage array includes a normal storage block group and a redundant spare storage block, wherein the normal storage block group includes a plurality of normal storage blocks, each of the normal storage blocks corresponds to a plurality of column selection signal lines, and the redundant spare storage blocks correspond to a plurality of column selection signal lines; An input-output circuit, comprising a plurality of normal input-output units and spare input-output units, wherein each of the normal input-output units corresponds to a corresponding normal storage block, and the spare input-output unit corresponds to the redundant spare storage block; A data transmission circuit, comprising a plurality of data transmission units, wherein each of the data transmission units is respectively coupled to a corresponding normal input-output unit and the spare input-output unit; wherein each of the data transmission units selectively couples the corresponding normal input-output unit and one of the spare input-output unit to the data transmission bus based on bad storage block indication information, so as to select the storage resource of the normal storage block corresponding to the normal input-output unit or the redundant spare storage resource of the redundant spare storage block corresponding to the spare input-output unit, Wherein, in response to the column addressing address matching the replacement address in the replacement address set, the bad memory block indication information is generated.

2. The memory according to claim 1, characterized in that: Further including: A normal column decoding circuit, wherein, when performing column addressing, the normal column decoding circuit enables the column selection signal lines of the same numbered columns in the multiple normal storage blocks corresponding to the column addressing address, so that the storage resources in the multiple normal storage blocks corresponding to the column selection signal lines of the same numbered columns are simultaneously column addressed.

3. The memory according to claim 2, characterized in that: Further including: A redundant column decoding circuit, wherein, when performing column addressing, the redundant column decoding circuit is used to compare the column addressing address with a replacement address in a replacement address set, and in response to the column addressing address matching the replacement address, the redundant column decoding circuit generates the bad storage block indication information and enables the spare column selection signal line based on the replacement address.

4. The memory according to claim 3, characterized in that: When performing column addressing, the normal memory block having the damaged memory resource is normally column addressed, and redundant replacement column addressing is performed on the redundant spare memory block through the redundant column decoding circuit.

5. The memory according to claim 3, characterized in that: The storage array includes a plurality of storage areas in the word line direction, wherein each storage area includes the normal storage block group and the redundant spare storage block, wherein the redundant column decoding circuit includes: a first redundant column decoding unit, receiving replacement address set information and storage area indication information, and selecting bad storage block indication information and a plurality of replacement addresses corresponding to the current storage area based on the replacement address set information and the storage area indication information, wherein the replacement address set information includes storage area information where the bad storage block is located, bad storage block information and bad storage block replacement address; a second redundant column decoding unit, coupled to the first redundant column decoding unit to receive the bad storage block indication information and the replacement address in the current storage area, and receive a column addressing address; compare the column addressing address with the replacement address to generate replacement indication information and current output bad storage block indication information; The output unit is coupled to the second redundant column decoding unit to receive the replacement indication information and a clock signal to sequentially output redundant spare column strobe enable signals based on the clock signal, thereby enabling the corresponding spare column strobe signal line.

6. The memory according to claim 5, characterized in that: The second redundant column decoding unit comprises: a plurality of first logic gate circuits, wherein each of the first logic gate circuits receives the column addressing address and a corresponding replacement address respectively, so as to compare the column addressing address with the replacement address respectively; Wherein, each of the first logic gate circuits comprises a logic XOR gate circuit.

7. The memory according to claim 5, characterized in that: The output unit comprises: a plurality of second logic gate circuits, wherein each of the second logic gate circuits is respectively coupled to an output terminal of a corresponding first logic gate circuit to receive the replacement indication signal and the clock signal to output the corresponding redundant spare column gating enable signal based on the clock signal; Wherein, each of the second logic gate circuits comprises a logic NAND gate circuit.

8. The memory according to claim 5, characterized in that: Each of the data transmission units in the data transmission circuit is also coupled to the redundant column decoding circuit to receive the current output bad storage block indication information, and is coupled to a data transmission bus; Each of the data transmission units selectively couples the corresponding normal input-output unit and one of the spare input-output units to the data transmission bus by selecting to connect to the common end of the normal input-output unit or the spare common end of the redundant spare input-output unit based on the currently output bad storage block indication information.

9. The memory according to claim 8, characterized in that: Each of the data transmission units comprises: A third logic gate circuit includes a first transmission gate and a second transmission gate, wherein the first transmission gate and the second transmission gate receive the current output bad storage block indication information and the current output bad storage block indication inverse information respectively; The first transmission gate is also coupled to a corresponding normal input-output unit to determine whether to couple the corresponding normal input-output unit to the data transmission bus based on the current output bad storage block indication information and the current output bad storage block indication inverse information; The second transmission gate is further coupled to the spare input output unit to determine whether to couple the spare input output unit to the data transmission bus based on the current output bad memory block indication information and the current output bad memory block indication inverse information.

10. The memory according to claim 1, characterized in that: Each of the normal input and output units and the standby input and output units respectively comprises: A storage array end input / output line and a storage array end input / output complementary line, for respectively coupling the bit line and the complementary bit line of the storage array; Common input / output lines and common input / output complementary lines, used to couple the storage array end input / output lines and the storage array end input / output complementary lines respectively; The end read / write control unit is arranged between the storage array end input / output line and the storage array end input / output complementary line, and the common input / output line and the common input / output complementary line.

11. The memory according to claim 1, characterized in that: Each of the column selection signal lines is respectively coupled to a preset number of bit lines, and each of the bit lines is respectively coupled to a corresponding memory cell in a column; Each of the spare column selection signal lines is respectively coupled to a preset number of spare bit lines, and each of the spare bit lines is respectively coupled to a corresponding column of redundant spare memory cells.

12. The memory according to claim 11, characterized in that: in, In response to a match between a column addressing address and a replacement address in a replacement address set, the spare input-output unit and the spare column enable signal line corresponding to the replacement address are enabled, wherein the enabled spare column enable signal line enables redundant spare storage units coupled to the preset number of spare bit lines coupled thereto to the spare input-output unit based on replacement indication information.

13. The memory according to claim 11, characterized in that: Each of the memories comprises a normal storage block group and a redundant spare storage block, the normal storage block group comprises h normal storage blocks, each normal storage block corresponds to m column selection signal lines, and each column selection signal line is respectively coupled to n bit lines; The redundant spare memory block corresponds to p spare column selection signal lines, and each of the spare column selection signal lines is respectively coupled to n spare bit lines.

14. The memory according to claim 1, characterized in that: The memory includes dynamic random access memory, ferroelectric random access memory, phase change random access memory, and pseudo-static random access memory.

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