Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate is provided, the substrate comprises a substrate body and discrete initial fin parts located on the substrate body, the substrate comprises a first area and a second area, the initial fin part of the first area serves as a first initial fin part, and the initial fin part of the second area serves as a second initial fin part; the first initial fin part and the second initial fin part are made of different materials; alternately carrying out first etching and second etching on the initial fin parts in the first region and the second region at the same time, and segmenting the initial fin parts; wherein the etching rate of the first etching to the first initial fin part is smaller than the etching rate of the second initial fin part, and the etching rate of the second etching to the second initial fin part is smaller than the etching rate of the first initial fin part. According to the embodiment of the invention, the etching rate difference of the first initial fin part and the second initial fin part is utilized for complementation, and the fin cutting size difference can be effectively reduced, so that the performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the semiconductor manufacturing process, with the development of ultra-large-scale integrated circuits, the characteristic size of the circuit is also shrinking. In order to meet the requirements of integrated circuits, the channel length of field effect transistors is constantly shortened, but the short channel effect becomes more and more serious, which limits the further reduction of the characteristic size of field effect transistors.

[0003] With the development of semiconductor technology, field effect transistors have gradually transitioned from planar to more efficient three-dimensional types, such as fin field effect transistors (FinFETs). In fin field effect transistors, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar field effect transistors, the gate structure has a stronger control over the channel and can effectively suppress the short channel effect; and compared with other devices, fin field effect transistors have better compatibility with existing integrated circuit manufacturing.

[0004] In the semiconductor field, according to process requirements, it is usually necessary to remove unnecessary parts of the fins so that the layout of the fins meets the design requirements. Currently, one approach is to remove the fins in a partial area through a fin cut process. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which reduces the difference in fin cut size caused by the difference in etching rate, thereby ensuring the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a substrate and discrete initial fins located on the substrate, the substrate comprising a first region and a second region, the initial fins located in the first region serve as first initial fins, and the initial fins located in the second region serve as second initial fins, and the materials of the first initial fins and the second initial fins are different; in the first region and the second region, simultaneously performing first etching and second etching alternately on the areas to be etched in the initial fins to divide the initial fins into multiple fins along their extension direction; wherein the etching rate of the first etching on the first initial fins is lower than the etching rate of the second initial fins, and the etching rate of the second etching on the second initial fins is lower than the etching rate of the first initial fins.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In a method for forming a semiconductor structure provided by an embodiment of the present invention, a first etch and a second etch are alternately performed on the to-be-etched area in the initial fin in the first region and the second region at the same time, so as to divide the initial fin into a plurality of fins along its extension direction, and the etching rate of the first etch on the first initial fin is lower than the etching rate of the second initial fin, and the etching rate of the second etch on the second initial fin is lower than the etching rate of the first initial fin; since the materials of the first initial fin and the second initial fin are different, a single etching step often has a difference in etching rates for the two, therefore, the embodiment of the present invention utilizes the respective etching selectivities of the first etching and the second etching to complement the difference in etching rates of the first initial fin and the second initial fin, thereby effectively reducing the difference in fin cut size caused by the difference in etching rate, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0010] Fig.11 is a flow chart corresponding to an embodiment of a method for forming a semiconductor structure of the present invention;

[0011] Figures 12 to 25 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure and taking the fin cutting process as an example, the reasons why the performance of semiconductor structures still needs to be improved are analyzed.

[0013] Figures 1 to 10 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figures 1 to 4 ,in, Figure 1 is a cross-sectional view in the first region and along a direction perpendicular to the extension direction of the initial fin, Figure 2 is a cross-sectional view in the second region and along a direction perpendicular to the extension direction of the initial fin, Figure 3 is a cross-sectional view in the first region and parallel to the extension direction of the initial fin, Figure 4It is a cross-sectional view in a second region and along a direction parallel to the extension direction of the initial fin, providing a substrate, the substrate including a substrate 10 and an initial fin (not marked) located on the substrate 10, the substrate including a first region 10A and a second region 10B, the initial fin located in the first region 10A serves as a first initial fin 20, and the initial fin located in the second region 10B serves as a second initial fin 21, and the first initial fin 20 and the second initial fin 21 are made of different materials.

[0015] It should be noted that the base further includes a bottom fin 25 located between the initial fin and the substrate 10 .

[0016] In this embodiment, a fin mask layer 30 is formed on the top of the initial fin, and the fin mask layer includes a first fin mask layer 31 , a second fin mask layer 32 and a third fin mask layer 33 stacked in sequence from bottom to top.

[0017] Continue to refer Figures 1 to 4 A mask layer 50 is formed between the initial fins and on the top of the initial fins, and the mask layer 50 includes a filling layer 51 covering the fin mask layer 30, an anti-reflective coating 52 located on the filling layer 51, and a patterned photoresist layer 53 located on the anti-reflective coating 52.

[0018] A mask opening (not shown) is formed in the photoresist layer 53 , and the mask opening is located above the to-be-etched area in the initial fin.

[0019] Combined with reference Figures 5 to 8 ,in, Figure 5 is a cross-sectional view in the first region and along a direction perpendicular to the extension direction of the initial fin, Figure 6 is a cross-sectional view in the second region and along a direction perpendicular to the extension direction of the initial fin, Figure 7 is a cross-sectional view in the first region and parallel to the extension direction of the initial fin, Figure 8 It is a cross-sectional view in the second area and along a direction parallel to the extension direction of the initial fin. The anti-reflective coating 52 and the filling layer 51 are sequentially etched along the photoresist layer 53, and the remaining filling layer 51 after patterning is used as a mask to etch away the fin mask layer 30 above the area to be etched of the initial fin and the area to be etched in the initial fin, thereby dividing the initial fin into a plurality of fins (not shown) along its extension direction.

[0020] It should be noted that the base also includes a bottom fin 25 located between the initial fin and the substrate 10. Therefore, after etching away the area to be etched in the initial fin, the bottom fin 25 is further etched downward to expose the substrate 10. Therefore, the bottom fin 25 remaining after etching and the remaining initial fin located above the remaining bottom fin 25 constitute a fin.

[0021] refer to Fig. 9 and Fig.10 , Fig. 9 is a cross-sectional view in the first region and parallel to the extending direction of the fin, Fig.10 It is a cross-sectional view in the second region and along a direction parallel to the extension of the fin. An isolation layer 60 is formed on the substrate 10 where the fin (not shown) is exposed. The top of the isolation layer 60 is lower than the top of the fin and covers part of the sidewall of the fin.

[0022] Specifically, the isolation layer 60 covers the sidewalls of the remaining bottom fin 25 and exposes the sidewalls of the remaining initial fins.

[0023] During the longitudinal etching process, a certain amount of lateral etching will usually occur. However, the first initial fin 20 and the second initial fin 21 are made of different materials. Due to the difference in etching rates between different materials, as the etching proceeds, the first initial fin 20 and the second initial fin 21 have different critical dimensions (CD) of the fin cut due to the different materials. The characteristic dimension of the fin cut refers to the size of the opening formed in the initial fin after etching along the extension direction of the initial fin.

[0024] Moreover, a gate structure spanning the fins will be formed later. The first initial fin 20 and the second initial fin 21 have different characteristic dimensions of fin cut due to different materials, which correspondingly causes the relative positions of the gate structures in the first region 10A and the second region 10B and their corresponding fins to change.

[0025] For example, Figure 7 and Figure 8 As shown, when the materials of the first initial fin 20 and the second initial fin 21 are silicon and silicon germanium, respectively, the fin cut feature sizes of the two are different due to the inconsistency of the etching rates of silicon and silicon germanium. Generally, under the conventional fin cut etching process, the etching rate of silicon germanium is faster than the etching rate of silicon. Therefore, when the first initial fin 20 formed of silicon material and the second initial fin 21 formed of silicon germanium need to be etched at the same time, if the fin cut feature size of the first initial fin 20 is to meet the requirements, the fin cut feature size of the second initial fin 21 will be too large; if the fin cut feature size of the second initial fin 21 is to meet the requirements, the fin cut feature size of the first initial fin 20 will be too small.

[0026] All of the above situations will lead to degradation of the performance of the semiconductor structure.

[0027] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. Fig.111 is a flow chart corresponding to an embodiment of a method for forming a semiconductor structure of the present invention, wherein the method comprises:

[0028] Step S1: providing a substrate, wherein the substrate includes a substrate and a discrete initial fin located on the substrate, wherein the substrate includes a first region and a second region, wherein the initial fin located in the first region is used as a first initial fin, and the initial fin located in the second region is used as a second initial fin, and the first initial fin and the second initial fin are made of different materials;

[0029] Step S2: In the first area and the second area, the first etching and the second etching are alternately performed on the area to be etched in the initial fin at the same time to divide the initial fin into a plurality of fins along its extension direction; wherein the etching rate of the first etching on the first initial fin is lower than the etching rate of the second initial fin, and the etching rate of the second etching on the second initial fin is lower than the etching rate of the first initial fin.

[0030] In a method for forming a semiconductor structure provided by an embodiment of the present invention, a first etch and a second etch are alternately performed on the to-be-etched area in the initial fin in the first region and the second region at the same time, so as to divide the initial fin into a plurality of fins along its extension direction, and the etching rate of the first etch on the first initial fin is lower than the etching rate of the second initial fin, and the etching rate of the second etch on the second initial fin is lower than the etching rate of the first initial fin; since the materials of the first initial fin and the second initial fin are different, a single etching step often has a difference in etching rates for the two, therefore, the embodiment of the present invention utilizes the respective etching selectivities of the first etching and the second etching to complement the difference in etching rates of the first initial fin and the second initial fin, thereby effectively reducing the difference in fin cut size caused by the difference in etching rate, thereby improving the performance of the semiconductor structure.

[0031] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 12 to 25 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0033] Combined with reference Figures 12 to 15 , Fig.12 is a cross-sectional view in the first region and along a direction perpendicular to the extension direction of the initial fin, Fig.13 is a cross-sectional view in the second region and along a direction perpendicular to the extension direction of the initial fin, Fig.14 is a cross-sectional view in the first region and parallel to the extension direction of the initial fin, Fig.15It is a cross-sectional view in the second region and along a direction parallel to the extension direction of the initial fin, performing step S1, providing a substrate (not marked), the substrate including a substrate 100 and a discrete initial fin (not marked) located on the substrate 100, the substrate including a first region 100A and a second region 100B, the initial fin located in the first region 100A serves as a first initial fin 200, and the initial fin located in the second region 100B serves as a second initial fin 210, and the materials of the first initial fin 200 and the second initial fin 210 are different.

[0034] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0035] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, etc. The substrate 100 may also be a silicon on insulator substrate or a germanium on insulator substrate, as well as other materials suitable for process requirements.

[0036] In this embodiment, the first region 100A and the second region 100B are used to form devices with different channel materials. Specifically, the first region 100A is used to form an NMOS device, and the second region 100B is used to form a PMOS device.

[0037] The initial fin is used to provide a basis for a subsequent fin cutting process.

[0038] The initial fin located in the first region 100A is referred to as the first initial fin 200 , and the initial fin located in the second region 100B is referred to as the second initial fin 210 .

[0039] The material of the initial fin includes any two of silicon, silicon germanium, germanium and Group III-V semiconductor materials, so that the materials of the first initial fin 200 and the second initial fin 210 are different, that is, the material of the first initial fin 200 is any one of silicon, silicon germanium, germanium and Group III-V semiconductor materials, the material of the second initial fin 210 is any one of silicon, silicon germanium, germanium and Group III-V semiconductor materials, and the materials of the first initial fin 200 and the second initial fin 210 are different, thereby meeting the different performance requirements of the devices formed in the first region 100A and the second region 100B.

[0040] In this embodiment, the material of the first initial fin 200 is the same as that of the substrate 100 , that is, silicon; the material of the second initial fin 210 is different from that of the substrate 100 , that is, silicon germanium.

[0041] In this embodiment, the second region 100B is used to form a PMOS device, so the material of the second initial fin 210 is silicon germanium. Silicon germanium is beneficial to improving the current drive performance of the PMOS device due to its high carrier mobility and strained Si-Ge lattice characteristics.

[0042] It should be noted that, in this embodiment, the initial fin is used to form an effective fin (active Fin), so a bottom fin 150 is also formed between the substrate 100 and the initial fin, and the bottom fin 150 is the portion subsequently covered by the isolation layer.

[0043] As an example, the material of the bottom fin 150 is the same as that of the substrate 100. Specifically, the bottom fin 150 and the first initial fin 200 are an integral structure.

[0044] In this embodiment, a fin mask layer 300 is further formed on the top of the initial fin, and the fin mask layer 300 is used as a mask for forming the initial fin and the bottom fin 150 .

[0045] In addition, the fin mask layer 300 can protect the initial fins, and in the subsequent planarization process, the fin mask layer 300 can also serve as a stop position for the planarization process.

[0046] The material of the fin mask layer 300 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0047] In this embodiment, the fin mask layer 300 includes a first fin mask layer 310, a second fin mask layer 320, and a third fin mask layer 330 stacked sequentially from bottom to top. As an example, the material of the first fin mask layer 310 is silicon oxide, the material of the second fin mask layer 320 is silicon nitride, and the material of the third fin mask layer 330 is silicon oxide. In other embodiments, the fin mask material can also be other materials suitable for the fin mask layer.

[0048] Continue to refer Figures 11 to 15 , and combined with reference Fig.16 and Fig.17 , Fig.16 is a cross-sectional view in the first region and parallel to the extension direction of the initial fin, Fig.17 The cross-sectional view is in the second region and parallel to the extension direction of the initial fin. In the first region 100A and the second region 100B, before the first etching and the second etching are alternately performed on the to-be-etched region in the initial fin, the method further includes: performing step S3, patterning the fin mask layer 300, and forming a mask opening 700 (such as Fig.16 and Fig.17 As shown), the mask opening 700 is located above the to-be-etched area in the initial fin.

[0049] The mask opening 700 is used to provide a basis for a subsequent fin cutting process.

[0050] In this embodiment, along the extension direction of the initial fin, the line width of the mask opening 700 meets the target line width of the to-be-etched region of the initial fin.

[0051] Along the extension direction of the initial fin, the line width of the mask opening 700 meets the target line width of the to-be-etched region of the initial fin, so that the fin cut sizes of the first region 100A and the second region 100B can meet the design requirements.

[0052] Moreover, the etching selectivities of the first etching and the second etching are subsequently used to complement the difference in etching rates of the first initial fin 200 and the second initial fin 210, so as to reduce the difference in fin cutting size caused by the difference in etching rates. Therefore, the line width of the mask opening 700 meets the target line width of the area to be etched of the initial fin, thereby reducing or avoiding changes to the mask corresponding to the fin cutting process.

[0053] In this embodiment, the step of patterning the fin mask layer 300 includes: Figures 12 to 15 As shown, a mask stack 500 covering the fin mask layer 300 is formed on the substrate 100, and the mask stack 500 includes a first mask layer 510 covering the substrate 100 and the fin mask layer 300, a second mask layer 520 located on the first mask layer 510, and a patterned third mask layer 530 located on the second mask layer 520; Fig.16 and Fig.17 As shown, the second mask layer 520 , the first mask layer 510 and the fin mask layer 300 are sequentially etched using the patterned third mask layer 530 as a mask, so as to form a mask opening 700 in the fin mask layer 300 .

[0054] The use of the mask stack 500 with a stacked structure is beneficial to improving the accuracy of pattern transfer.

[0055] In this embodiment, the first mask layer 510 has good filling performance, so that the first mask layer 510 has good filling performance between the initial fins, thereby providing a good foundation for the uniformity of the photolithography process and the subsequent etching process performed on the first mask layer 510. The material of the first mask layer 510 may include a spin on carbon (SOC) material, a photoresist, or an organic dielectric layer (ODL).

[0056] In this embodiment, the material of the first mask layer 510 is a spin-coated carbon material. The spin-coated carbon is formed by a spin coating process, and the process cost is low; moreover, by adopting the spin-coated carbon, the first mask layer 510 has better filling property between the initial fins, and is conducive to improving the flatness of the top surface of the first mask layer 510, thereby providing a good foundation for the uniformity of the photolithography process performed on the first mask layer 510 and the subsequent etching process.

[0057] In this embodiment, the second mask layer 520 is an anti-reflective coating, and the third mask layer 530 is a photoresist layer. The second mask layer 520 is used to improve the exposure quality of the third mask layer 530 .

[0058] Specifically, the second mask layer 520 includes a silicon-containing anti-reflective coating (Si-ARC) material or a bottom anti-reflective coating (BARC) material. As an example, the material of the second mask layer 520 is a bottom anti-reflective coating material.

[0059] It should be noted that, as an example, after the mask opening 700 is formed in the fin mask layer 300 , the third mask layer 530 and the second mask layer 520 are removed.

[0060] Continue to refer Fig.11 , and combined with reference Figures 18 to 23 , Fig.18 is a cross-sectional view in the first region and parallel to the extension direction of the initial fin after a first etching, Fig.19 is a cross-sectional view of the second region parallel to the extension direction of the initial fin after a first etching, Fig. 20 is a cross-sectional view in the first region and parallel to the extending direction of the fin after a second etching is performed, Fig.21 is a cross-sectional view of the second region parallel to the extending direction of the fin after a second etching is performed, Fig. 22 is a cross-sectional view of the first region parallel to the extension direction of the initial fin after the first etching and the second etching are completed, Fig.23After the first etching and the second etching are completed, in the cross-sectional view of the second region parallel to the extension direction of the fin, step S2 is performed, in the first region 100A and the second region 100B, the first etching and the second etching are alternately performed on the to-be-etched region (not shown) in the initial fin portion, so as to divide the initial fin portion into a plurality of fin portions 400 (such as Fig. 22 and Fig.23 As shown); wherein, the first etching rate of the first initial fin 200 is lower than the etching rate of the second initial fin 210, and the second etching rate of the second initial fin 210 is lower than the etching rate of the first initial fin 200.

[0061] Specifically, the patterned fin mask layer 300 is used as a mask to perform the first etching and the second etching alternately on the initial fin at the bottom of the mask opening 700 .

[0062] Since the materials of the first initial fin 200 and the second initial fin 210 are different, a single etching step often has a difference in etching rate for the two. Therefore, by utilizing the etching selectivity of the first etching and the second etching to complement the difference in etching rate between the first initial fin 200 and the second initial fin 210, the difference in fin cut size caused by the difference in etching rate can be effectively reduced, thereby improving the performance of the semiconductor structure.

[0063] In this embodiment, the etching capability of the first etching is greater than that of the second etching, that is, for the initial fins of the same material, the etching rate of the first etching is greater than that of the second etching.

[0064] Correspondingly, the second etching is performed after the first etching is performed.

[0065] The first etching is used to achieve vertical etching. The etching ability of the first etching is stronger, and its rate is faster than the rate of the second etching as a whole. Therefore, the first etching is performed first, which makes it easier to etch a pattern at the position to be etched, that is, it is easy to achieve preliminary patterning of the initial fin, thereby providing a basis for the subsequent second etching.

[0066] The etching capability of the second etching is slightly weaker, and the second etching is used to compensate for the difference in etching rate of the first etching.

[0067] In this embodiment, the material of the first initial fin 200 is silicon, and the material of the second initial fin 210 is silicon germanium. Therefore, the etching gas used in the first etching includes one or more of Ar, Cl2, HBr, SF6, and CF4, and the etching rate of the etching gas used in the first etching on the first initial fin 200 is lower than the etching rate of the second initial fin 210; correspondingly, the etching gas used in the second etching includes H2, and the etching rate of the etching gas used in the second etching on the first initial fin 200 is higher than the etching rate of the second initial fin 210.

[0068] In this embodiment, the material of the first initial fin 200 is silicon, and the material of the second initial fin 210 is silicon germanium. Therefore, when the first etching is performed using the above etching gas, the etching rate of silicon germanium is higher.

[0069] In addition, in this embodiment, the above etching gas is first used to perform the first etching, thereby opening the silicon and silicon germanium in the area to be etched.

[0070] The etching gas used in the second etching includes H2. The conventional etching process enhances etching by incident ions with high energy, so the etching rate tends to increase with the increase of ion energy, but since the atomic radius of hydrogen is relatively small, the ions can enter the deeper position inside the initial fin with relatively few collisions, and when the ion energy is relatively small, the ion energy is deposited near the surface of the initial fin in a low ion energy manner, thereby achieving etching of silicon and silicon germanium based on the reaction of the deposited ion energy, and the etching rate of the first initial fin 200 made of silicon is higher.

[0071] Specifically, when hydrogen is used for the second etching, the ions deposited on the surface of the initial fin can be used to etch silicon and silicon germanium. Hydrogen easily bonds with silicon to form Si-H bonds, and as the etching time proceeds, it is easy to form Si-H bonds adsorbed on the surface of the second initial fin 210, which in turn passivates the silicon germanium, making the second etching rate for silicon germanium lower, thereby making the second etching rate for silicon higher than the etching rate for silicon germanium, which is beneficial to complement the etching rates of the first initial fin 200 and the second initial fin 210 to meet process requirements.

[0072] In this embodiment, in the step of alternately performing the first etching and the second etching on the area to be etched in the initial fin in the first region 100A and the second region 100B at the same time, the pressure of the first etching should not be too large or too small. If the pressure is too large, the side wall of the initial fin is easily damaged due to the random collision of the gas, and the excessive pressure is also likely to cause the ion energy to be too high, which is likely to cause the effect of depositing ion energy near the surface of the initial fin to be poor, and then it is easy to cause the effect of complementing the etching rates of the first initial fin 200 and the second initial fin 210 through the second etching to be poor; if the pressure is too small, it is easy to cause the etching rate to be too slow, thereby affecting the process efficiency. For this reason, in this embodiment, in the step of alternately performing the first etching and the second etching on the area to be etched in the initial fin in the first region 100A and the second region 100B at the same time, the pressure of the first etching is 3 mTorr to 80 mTorr.

[0073] In this embodiment, in the step of alternately performing the first etching and the second etching on the area to be etched in the initial fin in the first region 100A and the second region 100B at the same time, the flow rate of the first etching should not be too large or too small. If the flow rate is too large, it is easy to cause the concentration of the etching gas to be too high, resulting in an overly violent reaction, thereby causing damage to the initial fin. Moreover, the excessive flow rate is accompanied by an increase in pressure, which is also easy to cause the ion energy to be too high, thereby easily leading to poor effect of depositing ion energy near the surface of the initial fin, thereby easily leading to poor effect of complementing the etching rates of the first initial fin and the second initial fin through the second etching; if the flow rate is too small, it is easy to cause the etching rate to be too slow due to insufficient concentration of the etching gas, thereby affecting the process efficiency. For this reason, in this embodiment, in the step of alternately performing the first etching and the second etching on the area to be etched in the initial fin in the first region 100A and the second region 100B at the same time, the flow rate of the etching gas of the first etching is 50 ml / min to 200 ml / min.

[0074] In this embodiment, the second etching is performed under low temperature conditions, which is conducive to depositing ion energy near the surface of the initial fin.

[0075] In this embodiment, the process temperature of the second etching is less than or equal to 80 degrees Celsius.

[0076] It should be noted that in the step of alternately performing the first etching and the second etching on the to-be-etched area in the initial fin in the first region 100A and the second region 100B at the same time, the process temperature of the second etching should not be too high. When the temperature is too high, it is easy to cause the ions in the material of the second initial fin 210 to diffuse. For example, the silicon germanium of the second initial fin 210 is easy to cause the diffusion of germanium, thereby affecting the material uniformity of the second initial fin 210. Moreover, under low temperature conditions, it is conducive to the deposition of ion energy near the surface of the initial fin. Too high a temperature is easy to cause the ion energy to be too high, which is easy to cause the effect of depositing ion energy near the surface of the initial fin to be poor, and then it is easy to cause the effect of complementing the etching rates of the first initial fin 200 and the second initial fin 210 through the second etching to be poor; therefore, the process temperature of the second etching is less than or equal to 80 degrees Celsius.

[0077] However, the process temperature of the second etching should not be too low. If the temperature is too low, it is easy to cause the etching rate to be too slow, thereby affecting the process efficiency. For this reason, in the step of alternately performing the first etching and the second etching on the to-be-etched area in the initial fin at the same time, the process temperature of the second etching is 20 degrees Celsius to 80 degrees Celsius.

[0078] In this embodiment, the second etching is performed under a preset bias voltage, and the preset bias voltage is less than or equal to 200 volts.

[0079] The preset bias voltage is used to adjust the etching direction. By performing the etching under the preset bias voltage, it is beneficial to realize longitudinal etching, thereby realizing longitudinal etching of the initial fin, which is beneficial to realizing fin cutting while improving the accuracy of the fin cutting size.

[0080] It should be noted that the preset bias voltage should not be too large. If the preset bias voltage is too large, uneven lateral and longitudinal etching may occur due to ion collision, which may result in poor cross-sectional morphology after etching. For this reason, in this embodiment, the preset bias voltage is less than or equal to 200 volts.

[0081] However, the preset bias voltage should not be too small. If the preset bias voltage is too small, it will easily lead to too low an etching rate, thereby affecting the realization of etching. For this reason, in this embodiment, the preset bias voltage is 100 volts to 200 volts.

[0082] In this embodiment, the source power of the second etching is greater than or equal to 400 watts.

[0083] The source power is used to adjust the concentration of ions in the second etching reaction, thereby achieving the adjustment of the reaction rate.

[0084] It should be noted that the source power of the second etching should not be too small. If the source power of the second etching is too small, it is easy to cause insufficient ion concentration for etching, resulting in the second etching having an etching rate for the first initial fin 200 greater than the etching rate for the second initial fin 210, which is not good, and further leads to poor complementary effect of the etching rates of the first initial fin 200 and the second initial fin 210. For this reason, in this embodiment, the source power of the second etching is greater than or equal to 400 watts.

[0085] The source power of the second etching should not be too large, which may cause poor effect of depositing ion energy near the surface of the initial fin, and further cause poor effect of complementing the etching rates of the first initial fin 200 and the second initial fin 210 by the second etching.

[0086] To this end, in this embodiment, the source power of the second etching is 400 watts to 2000 watts.

[0087] In this embodiment, the area to be etched in the initial fin is subjected to one or more etching treatments, and each etching treatment includes the first etching and the second etching; wherein, in the same etching treatment, the second etching is performed after the first etching, and the greater the difference in etching rate of the first etching on the first initial fin 200 and the second initial fin 210, the greater the time proportion of the second etching in the etching treatment.

[0088] The etching rate of the first etch on the first initial fin 200 is lower than the etching rate of the second initial fin 210. The greater the difference in the etching rate of the first etch on the first initial fin 200 and the second initial fin 210, the greater the difference in the etching size of the initial fins in the first region 100A and the second region 100B after the first etch. Therefore, the complementary etching size in the second etch is larger, and the etching time required is longer when the etching rate of the second etch is constant. Therefore, the greater the difference in the etching rate of the first etch on the first fin and the second fin, the greater the time proportion of the second etch in the etching process.

[0089] The time proportion of the second etching in the etching process can be adjusted accordingly according to the process requirements, so that the etching effect can meet the corresponding requirements.

[0090] In this embodiment, in the step of alternately performing the first etching and the second etching on the to-be-etched area in the initial fin in the first region 100A and the second region 100B at the same time, the number of the alternating cycles of the first etching and the second etching is 2 to 10 times.

[0091] If the number of alternating cycles of the first etching and the second etching is too large, it is easy to cause the etching process to take too long, and if the number of alternating cycles of the first etching and the second etching is too small, it is easy to cause poor effect of complementing the difference in etching rates of the first initial fin 200 and the second initial fin 210. Therefore, in this embodiment, the number of alternating cycles of the first etching and the second etching is 2 to 10 times.

[0092] It should be noted that the number of alternating cycles of the first etching and the second etching can be adjusted accordingly according to the process requirements. For example, in the first region 100A and the second region 100B, in the step of alternating the first etching and the second etching on the to-be-etched region (not indicated) in the initial fin, when the process efficiency needs to be improved, the number of alternating cycles of the first etching and the second etching can be appropriately reduced; when a higher fin cutting size accuracy needs to be met, the number of alternating cycles of the first etching and the second etching can be increased according to the process requirements.

[0093] It should be noted that this embodiment only describes in detail one first etching and one second etching. When the first etching and the second etching are alternately cycled more than once, the first etching and the second etching are repeated, which will not be described in detail in this embodiment.

[0094] In this embodiment, a bottom fin 150 is also formed between the substrate 100 and the initial fin. Therefore, after completing the first etching and the second etching (that is, completing the etching process of the initial fin), it also includes: etching the bottom fin 150 exposed by the remaining initial fin, thereby dividing the bottom fin 150 along its extension direction to expose the substrate 100.

[0095] In a specific embodiment, after the bottom fin 150 exposed by the remaining initial fin is etched, the stacked remaining bottom fin 150 and the remaining initial fin constitute the fin 400 .

[0096] Combined with reference Fig.24 and Fig.25 , Fig.24 is a cross-sectional view in the first region and parallel to the extending direction of the fin 400, Fig.25 It is a cross-sectional view in the second region and along a direction parallel to the extension direction of the fin 400 . An isolation layer 600 is formed on the substrate 100 at the side of the fin 400 , and the top of the isolation layer 600 is lower than the top of the fin 400 .

[0097] The isolation layer 600 is used as a shallow trench isolation (STI) structure to isolate adjacent devices.

[0098] The material of the isolation layer 600 includes other insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. As an example, in this embodiment, the material of the isolation layer 600 is silicon oxide.

[0099] In this embodiment, the isolation layer covers the sidewalls of the remaining bottom fin 150 and exposes the remaining initial fin. It is understood that in other embodiments, the isolation layer may also cover part of the sidewalls of the remaining initial fin.

[0100] In one embodiment, the step of forming the isolation layer 600 includes: forming an initial isolation material layer (not shown) on the substrate where the fin 400 is exposed, the initial isolation material layer covering the top of the fin mask layer 300; using the fin mask layer 300 as a stop position, flattening the initial isolation material layer; after flattening the initial isolation material layer, removing the fin mask layer 300; after removing the fin mask layer 300, etching back a portion of the thickness of the remaining initial isolation material layer to form the isolation layer 600.

[0101] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a discrete initial fin located on the substrate, the substrate comprising a first region and a second region, the initial fin located in the first region being a first initial fin, the initial fin located in the second region being a second initial fin, and the first initial fin and the second initial fin being made of different materials; In the first region and the second region, simultaneously and alternately performing the first etching and the second etching on the to-be-etched region in the initial fin portion, so as to divide the initial fin portion into a plurality of fin portions along its extension direction; The etching rate of the first etch on the first initial fin is lower than the etching rate of the second initial fin, and the etching rate of the second etch on the second initial fin is lower than the etching rate of the first initial fin.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial fin includes any two of silicon, silicon germanium, germanium and Group III-V semiconductor materials, so that the materials of the first initial fin and the second initial fin are different.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first initial fin is silicon, and the material of the second initial fin is silicon germanium; The etching gas used in the second etching includes hydrogen.

4. The method for forming a semiconductor structure according to claim 3, wherein: The process temperature of the second etching is less than or equal to 80 degrees Celsius.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process temperature of the second etching is 20 degrees Celsius to 80 degrees Celsius.

6. The method for forming a semiconductor structure according to claim 3, wherein: The source power of the second etching is greater than or equal to 400 watts.

7. The method for forming a semiconductor structure according to claim 3, wherein: The second etching is performed under a preset bias voltage, and the preset bias voltage is less than or equal to 200 volts.

8. The method for forming a semiconductor structure according to claim 7, wherein: The preset bias voltage is 100 to 200 volts.

9. The method for forming a semiconductor structure according to claim 3, wherein: The parameters of the first etching include: a pressure of 3 mTorr to 80 mTorr, and a flow rate of the etching gas of 50 ml / min to 200 ml / min.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first initial fin is silicon, and the material of the second initial fin is silicon germanium; The etching gas used in the first etching includes one or more of Ar, Cl2, HBr, SF6, CF4 and H2.

11. The method for forming a semiconductor structure according to claim 1 or 10, characterized in that: The etching capability of the first etching is greater than the etching capability of the second etching; After performing the first etching, performing the second etching.

12. The method for forming a semiconductor structure according to claim 1, wherein: In the step of alternately performing the first etching and the second etching on the to-be-etched area in the initial fin in the first region and the second region at the same time, the number of the alternating cycles of the first etching and the second etching is 2 to 10 times.

13. The method for forming a semiconductor structure according to claim 1, wherein: The to-be-etched area in the initial fin is subjected to one or more etching processes, each etching process comprising the first etching and the second etching; wherein, In the same etching process, the second etching is performed after the first etching, and the greater the difference in etching rate of the first etching on the first initial fin and the second initial fin, the greater the time proportion of the second etching in the etching process.

14. The method for forming a semiconductor structure according to claim 1, wherein: After the initial fin is divided into a plurality of fins along its extension direction, the method for forming a semiconductor structure further includes: forming an isolation layer on the substrate at the side of the fin, wherein the top of the isolation layer is lower than the top of the fin.

15. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, a fin mask layer is formed on the top of the initial fin; Before alternately performing the first etching and the second etching on the to-be-etched area in the initial fin in the first region and the second region at the same time, the method further includes: patterning the fin mask layer, forming a mask opening in the fin mask layer, wherein the mask opening is located above the to-be-etched area in the initial fin, and along the extension direction of the initial fin, the line width of the mask opening meets the target line width of the to-be-etched area in the initial fin; In the first region and the second region, in the step of alternately performing the first etching and the second etching on the to-be-etched region in the initial fin at the same time, the patterned fin mask layer is used as a mask to alternately perform the first etching and the second etching on the initial fin at the bottom of the mask opening.

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