Packaging process for solving poor infiltration of small-diameter salient points on chip edge of FCQFN product and FCQFN product

Abstract

The invention relates to the technical field of chip packaging, in particular to a process and a product for solving poor infiltration of small-diameter salient points on the edge of an FCQFN product chip, and the process comprises the following steps: S1, manufacturing silk screens in one-to-one correspondence of salient points and pins according to a frame drawing and salient point mounting positions, and then printing a soldering flux on the surface of a frame by utilizing silk screen printing to obtain a preprocessed frame; s2, performing first reflow soldering treatment on the pre-treated framework to obtain a framework to be subjected to chip mounting; s3, mounting a chip on the frame to be subjected to chip mounting to obtain a mounted chip; and S4, performing second reflow soldering processing on the surface-mounted chip to complete reflow soldering of the salient points and the frame pins, and obtaining a finished FCQFN product chip. According to the method, the anti-oxidation layer on the surface of the frame is removed through printing scaling powder backflow, and then reflow soldering is performed after the chip is mounted, so that the phenomenon of poor soldering infiltration in the prior art is solved, and the yield and reliability of products are improved.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, in particular to a packaging process and a product for solving the problem of poor wetting of small-diameter bumps at the edge of a FCQFN product chip. Background Art

[0002] QFN (Quad Flat No-leads Package) is one of the surface mount packages. The bare copper frame is used as the base material for flip chip soldering. The bare copper frame lead surface is directly soldered to the solder of the bump. Due to the electrical performance requirements of some chips, when designing chip bumps, the bump diameter of the chip edge will be much smaller than that of other bumps. For example, the difference between the large and small bump diameters is more than 25um, and the normal difference is within 20um, as shown below Figure 1 , 2 The chip design shown is as follows: the diameter of the edge bump is 65um, the diameter of the other bumps is 100um, and the difference between the two diameters is 35um.

[0003] Under the current bumping process capability, the height difference between the small-diameter bumps on the upper edge and the large-diameter bumps will tend to the upper limit of process control. This is because the smaller the bump diameter on the chip edge, the more difficult it is to control the height difference with the large-diameter bumps. After the chip is attached to the frame during the flip-chip process of the packaging process, the flux mark on the small-diameter bumps is missing (e.g. Figure 3 After the reflow soldering is completed, the small-diameter bumps on the edge of the chip and the bare copper frame surface have Die shear-poor wetting and Cross-section-poor wetting (as shown in Figure 2). Figure 4 As shown in the figure, the reason for the poor wetting phenomenon is that the height of the small-diameter bump on the edge is lower than that of the large-diameter bump. When the bumping process accuracy is lower than the lower limit (such as Figure 5 As shown in the figure, the height difference between the small-diameter bump and the large-diameter bump exceeds the current flip-chip process capability. When dipping the flux in the flip-chip process, the small-diameter bump cannot get enough flux due to its low height, resulting in the inability to effectively remove the anti-oxidation layer on the welding surface of the bare copper frame during reflow soldering, resulting in poor soldering wetting. Summary of the invention

[0004] Aiming at the problem in the prior art that poor soldering wetting occurs because the anti-oxidation layer on the soldering surface of the bare copper frame cannot be effectively removed during reflow soldering, the present invention provides a packaging process for solving the poor wetting of small-diameter bumps on the edge of a FCQFN product chip.

[0005] The present invention is achieved through the following technical solutions: A packaging process for solving the problem of poor wetting of small-diameter bumps on the edge of a chip of a FCQFN product, comprising the following steps: S1, according to the frame drawing and the bump mounting position, a screen with one-to-one correspondence between bumps and pins is made, and then solder flux is printed on the surface of the frame by screen printing to obtain a pre-processed frame; S2, performing a first reflow process on the pre-processed frame to obtain a frame to be loaded with core; S3, mounting the chip on the frame to be mounted, to obtain a mounted chip; S4, performing a second reflow soldering process on the mounted chip to complete the reflow soldering of the bumps and the frame pins, and obtaining a finished FCQFN product chip.

[0006] Preferably, in S1, the wire mesh is woven from stainless steel material.

[0007] Preferably, the thickness of the screen is 40-50 μm.

[0008] Preferably, in S1, the area of ​​the mesh is 80% of the area of ​​the bump.

[0009] Preferably, in S1, the printing thickness of the soldering flux is 40±0.5 μm.

[0010] Preferably, the soldering flux is a water-free and low-residue soldering flux.

[0011] Preferably, in S2, during the first reflow soldering process, the temperature is 240-245° C. and the time is 40-45 seconds.

[0012] Preferably, in S3, the chip mounting is completed within 30 minutes after the first reflow treatment on the core frame.

[0013] Preferably, in S4, during the second reflow soldering process, the temperature is 245-250° C. and the time is 45-55 s.

[0014] A product obtained by a packaging process that solves the problem of poor wetting of small-diameter bumps at the edge of a FCQFN product chip.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a packaging process for solving the problem of poor wetting of small-diameter bumps on the edge of a chip of an FCQFN product. In the packaging process for solving the problem of poor wetting of small-diameter bumps on the edge of a chip of an FCQFN product, a printed soldering flux is firstly used to reflow to remove an anti-oxidation layer on the surface of a frame, and then the chip is mounted and reflow soldered. The first reflow soldering is to remove the anti-oxidation layer on the surface of the frame, improve the cleanliness and activity of the welding surface, and provide good joining conditions for subsequent welding processes; the second reflow soldering is to complete the electrical connection between the bumps and the frame pins, thereby solving the problem of poor welding wetting in the prior art, thereby improving the yield and reliability of the product. Furthermore, the material and thickness of the screen are limited in order to ensure the stability and printing accuracy of the screen.

[0016] Furthermore, the thickness of the flux is limited in order to ensure uniformity and wetting effect, and the water-free and low-residue flux is selected to reduce subsequent cleaning steps and potential residue problems.

[0017] Furthermore, the chip mounting is completed within 30 minutes after the first reflow soldering treatment of the core frame. Performing this operation within this time helps to maintain the activity and good wetting performance of the flux. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a design schematic diagram of a chip in the prior art; Figure 2 It is a design schematic diagram of a chip from another perspective in the prior art; Figure 3 This is a phenomenon diagram of the missing solder flux mark of a small-diameter bump on a chip in the prior art; Figure 4 It is a diagram of the phenomenon of Cross-section-poor infiltration in the prior art; Figure 5 It is a schematic diagram of bump wetting in the prior art; Figure 6 This is a flow chart of a packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of a chip of a FCQFN product according to the present invention; Figure 7 It is a schematic diagram of a product chip made by a packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of a FCQFN product chip according to the present invention. DETAILED DESCRIPTION

[0019] The present invention is further described in detail below in conjunction with specific embodiments, which are intended to explain the present invention rather than to limit it.

[0020] The present invention discloses a packaging process for solving the problem of poor wetting of small-diameter bumps on the edge of FCQFN product chips. Figure 6 , 7 , including the following steps: S1, according to the frame drawing and the bump mounting position, make a screen with one-to-one correspondence between the bump and the pin, and then use the screen printing equipment to print the flux on the surface of the frame to obtain the pre-processed frame. Among them, the material, thickness and mesh design of the screen meet the process requirements to improve the printing accuracy and uniformity of the flux. In this embodiment, the screen is woven from stainless steel material, the screen thickness is controlled at 40~50μm, and the area of ​​the mesh is 80% of the bump area. The printing thickness of the flux is 40±0.5μm, and the flux uses a water-free and low-residue flux, such as NC-809 ultra-low residue flux, 3M flux, Alpha flux, etc. The water-free and low-residue flux can reduce subsequent cleaning steps and potential residue problems, and improve product reliability.

[0021] S2, the pre-treated frame is subjected to the first reflow soldering treatment to obtain the frame to be cored; specifically: after printing the flux, the frame needs to pass through the reflow soldering furnace equipment within 30 minutes. During the first reflow soldering treatment, the temperature is 240~245℃ and the time is 40~45S, so as to effectively remove the antioxidant film or oxidizing components on the bare copper surface. Among them, the frame needs to be processed by the reflow soldering furnace equipment within 30 minutes. This time limit is to maintain the activity and wetting performance of the flux, ensure that the flux forms an effective coating on the surface of the frame, and is ready to be combined with the chip bumps to be subsequently mounted. The first reflow soldering parameter setting is firstly to effectively remove the antioxidant film or oxidizing components on the bare copper surface of the frame, to provide good surface conditions for the subsequent welding process, and secondly to ensure that the flux can fully penetrate and act on the welding surface, while ensuring that the frame will not be damaged or the welding quality will not be affected due to excessively long high temperature treatment.

[0022] S3, mounting the chip on the frame to be mounted, obtaining a mounted chip; that is, the frame after the first reflow soldering enters the flip chip mounting equipment within 30 minutes to complete the chip mounting.

[0023] S4, the mounted chip is subjected to a second reflow soldering process to complete the reflow soldering of the bumps and the frame pins, and a finished FCQFN product chip is obtained. During the second reflow soldering process, the temperature is 245-250°C and the time is 45-55s.

[0024] The present invention also discloses a product obtained by a packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips. During the packaging process of the product chip, the anti-oxidation layer on the surface of the frame is first removed by printing flux and performing a first reflow soldering, and then the chip is mounted, and finally a second reflow soldering is performed, which successfully solves the problem of poor wetting of small-diameter bumps, thereby improving the electrical performance and reliability of the product. The product can be widely used in electronic products that require high-density and high-reliability packaging, such as mobile communication equipment, computers, automotive electronics, industrial control and other fields.

[0025] The above description is only a preferred embodiment of the present invention and is not intended to impose any limitation on the technical solution of the present invention. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can also be subjected to several simple modifications and substitutions, and these modifications and substitutions are also within the scope of protection covered by the claims.

Claims

1. A packaging process for solving the problem of poor wetting of small-diameter bumps on the edge of FCQFN product chips, characterized in that: The following steps are involved: S1, according to the frame drawing and the bump mounting position, a screen with one-to-one correspondence between bumps and pins is made, and then solder flux is printed on the surface of the frame by screen printing to obtain a pre-processed frame; S2, performing a first reflow process on the pre-processed frame to obtain a frame to be loaded with core; S3, mounting the chip on the frame to be mounted, to obtain a mounted chip; S4, performing a second reflow soldering process on the mounted chip to complete the reflow soldering of the bumps and the frame pins, and obtaining a finished FCQFN product chip.

2. The packaging process for solving the poor wetting of small-diameter bumps on the edge of FCQFN product chips according to claim 1, characterized in that: In S1, the wire mesh is woven from stainless steel material.

3. The packaging process for solving the poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that: The thickness of the screen is 40~50μm.

4. The packaging process for solving the poor wetting of small-diameter bumps on the edge of FCQFN product chips according to claim 1, characterized in that: In S1, the mesh design requires 80% of the bump area.

5. The packaging process for solving the poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that: In S1, the printing thickness of the flux was 40 ± 0.5 μm.

6. The packaging process for solving the poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that: The flux used is water-free and low-residue flux.

7. The packaging process for solving the poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that: In S2, during the first reflow process, the temperature is 240~245°C and the time is 40~45S.

8. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that: In S3, the chip mounting is completed within 30 minutes after the first reflow treatment of the core frame.

9. The packaging process for solving the poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that: In S4, during the second reflow process, the temperature is 245-250°C and the time is 45-55s.

10. A product obtained by the packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of a chip of a FCQFN product according to any one of claims 1 to 9.

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