Die embedded package and method of forming a die embedded package

Abstract

A die embedded package is provided. The die embedded package may include: a first die and a second die, the first die being thinner than the second die; a first encapsulation material encapsulating the first die, where a total thickness of the first encapsulation material and the first die is approximately equal to a thickness of the second die, and where an outer surface of the first encapsulation material and an outer surface of the second die are arranged coplanar; a second encapsulating material encapsulating the encapsulated first die and second die; a first set of conductive vias electrically contacting the first die from a first side of the first die and a second set of conductive vias electrically contacting the first die from a second side of the first die, the second side being opposite the first side; and a third set of conductive vias electrically contacting the second die from the first side of the second die or from the second side of the second die.

Description

Technical Field

[0001] Various embodiments are generally directed to a die embedded package and a method of forming a die embedded package. Background Art

[0002] As thinner and thinner dies are required (e.g., from 60 μm dies currently used to 40 μm dies), handling of the dies becomes increasingly critical. Especially when the die is embedded inside a PCB laminate using die embedding techniques, which may be done by a PCB manufacturer who may have limited experience in handling thin dies, the risk of damage (e.g., cracking, breaking, etc.) during die handling and embedding may be high.

[0003] Another die embedded package (also called chip embedded (CE) package) key topic that may arise from ultra-thin chips, such as SFET dies, is as follows: Although thinning processes are already available for MOSFET dies (such as SFET dies), processes for thinning driver dies to the same thickness (e.g., 40μm) may not yet be available. Different die thicknesses may result in micro vias on the front and back sides of an ultra-thin die (e.g., SFET) having different depths. This may make design rules, laser drilling, and electroplating processes (e.g., filling of vias) more complicated. In addition, since the vias are approximately conical, the increase in via depth may ultimately reduce the effective contact area on the die pad. This may mean that unequal contact areas are formed on both sides of the die.

[0004] The problem is Figure 3 It can be seen that Figure 3 A die embedded package is shown in which the die 102 is so thin (eg, compared to the core 104 and / or a second die (the second die is not shown, but Figure 3 The same issues described in the context of Figure 1 , even though the vias of the (multi) die embedded package 100 according to the prior art are simplified to be straight lines instead of tapered)) so that the contact area (indicated by the arrow) on the side of the die 102 where the longer micro via 102V is required is significantly smaller than the contact area on the other side of the die 102 with the shorter micro via 102V. The difference in diameter of the contact area is indicated by the second arrow on the bottom side.

[0005] Until today, the problems posed by ultra-thin dies remain unsolved. There is no proven concept that allows embedding ultra-thin dies (eg, thickness of about 40 μm) inside a carrier, such as a PCB laminate, in a reliable manner and with good yield.

[0006] It may not be possible to thin the driver die to the same thickness as the SFET. However, it may be desirable to embed dies with different thicknesses (e.g., 40 μm and 60-100 μm) inside one package. This may not be possible in a cost-effective manner using current die embedding processes. Summary of the invention

[0007] A die-embedded package is provided. The die-embedded package may include: a first die and a second die, the first die being thinner than the second die; a first encapsulation material encapsulating the first die, wherein the total thickness of the first encapsulation material and the first die is approximately equal to the thickness of the second die, and wherein the outer surface of the first encapsulation material and the outer surface of the second die are arranged coplanar; a second encapsulation material encapsulating the encapsulated first die and the second die; a first group of conductive vias electrically contacting the first die from a first side of the first die and a second group of conductive vias electrically contacting the first die from a second side of the first die, the second side being opposite to the first side; and a third group of conductive vias electrically contacting the second die from the first side of the second die or from the second side of the second die. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, the same or similar reference numerals generally refer to the same or similar parts in different views. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0009] Figure 1 shows a schematic cross-sectional view of a bare die embedded package according to the prior art;

[0010] Figure 2 shows a schematic cross-sectional view of a die embedded package according to various embodiments;

[0011] Figure 3 shows a schematic cross-sectional view of a bare die embedded package according to the prior art;

[0012] Figure 4 shows a schematic cross-sectional view of a die embedded package according to various embodiments;

[0013] Figure 5 shows a schematic cross-sectional view of a bare die embedded package according to the prior art;

[0014] FIG. 6A to FIG. 6C Each of which shows a schematic cross-sectional view of a die embedded package according to various embodiments;

[0015] Fig. 7Ashows a schematic cross-sectional view of a bare die embedded package according to the prior art;

[0016] Figure 7B shows a schematic cross-sectional view of a die embedded package according to various embodiments;

[0017] Fig. 8A shows a schematic top view and a schematic cross-sectional view of a die with encapsulation material used in a die embedded package according to the prior art;

[0018] FIG. 8B to FIG. 8E each showing a schematic top view and a schematic cross-sectional view of a die with encapsulation material as used in a die embedded package according to various embodiments;

[0019] Fig. 9 Methods of forming a die embedded package according to various embodiments are shown in a series of separate panels;

[0020] Fig. 10A , Fig. 10B and Fig.11 each showing a schematic cross-sectional view of a die with encapsulation material as used in a die embedded package according to various embodiments;

[0021] Fig.12 shows a schematic top view of a die with encapsulation material as used in a die embedded package according to various embodiments; and

[0022] Fig.13 A flow chart of a method of forming a die embedded package according to various embodiments is shown. DETAILED DESCRIPTION

[0023] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0024] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0025] The term "over" used in relation to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "directly" on the side or surface, e.g., in direct contact with the side or surface. The term "over" used in relation to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "indirectly" on the side or surface with one or more additional layers disposed between the side or surface and the deposited material.

[0026] Various aspects of the present disclosure are provided for devices, and various aspects of the present disclosure are provided for methods. It should be understood that the basic characteristics of the devices also apply to the methods, and vice versa. Therefore, for the sake of brevity, repeated descriptions of these characteristics may have been omitted.

[0027] The terms "chip" and "die" are used herein as synonyms.

[0028] "Micro vias" are also referred to herein as "vias."

[0029] In various embodiments, a die embedded package and a method for forming a die embedded package are provided that allow thin dies and / or dies with different thicknesses to be embedded inside a (e.g., ordinary) PCB laminate in a reliable manner and without requiring any significant changes to existing manufacturing processes. Various embodiments may be particularly relevant in the context of double-sided chip embedding (CE2).

[0030] In various embodiments, the die may be protected by an additional protective layer (e.g., a layer of encapsulation material, such as a prepreg material or a molding material) to increase the thickness of the die and make the die more robust for handling. The die may be protected with additional molding, lamination, or coating layers to shield the die from one or both major sides.

[0031] In various embodiments, the protective layer may completely cover one or both of the main surfaces (and optionally the side surfaces), or the protective layer may be structured in areas where this may be suitable (ie via the landing area).

[0032] In various embodiments, a die having a protective layer on one or both of its major surfaces is provided. The protective layer can increase the thickness of the die, making the die more robust for handling during die placement and embedding processes. The protective layer can also make it easier to embed a thin die inside the same package with a thicker die.

[0033] Increasing the thickness of the thin die with the protective layer can shift the active surface (e.g., vertically, orthogonal to a horizontal plane parallel to the main surface of the die) of the embedded thin die toward the middle (e.g., the central plane) of the core layer. The core layer can be part of a die-embedded package including the thin die, and the thin die can be arranged in an opening of the core layer.

[0034] For a (vertically) displaced die, the depth of the micro vias that can be arranged to electrically contact the die from two opposite main sides of the die can be symmetrical on both sides. In other words, at least for some of the micro vias, the micro vias on both sides of the die can have approximately equal lengths.

[0035] In various embodiments, a protective layer, such as an encapsulation material layer, may be provided as a structured top layer and / or bottom layer to enhance handling capabilities and further facilitate processing, especially during die handling and laser via drilling. The protective layer, such as an encapsulation material, may be configured to enhance adhesion on one or more, such as two, main sides of the die (e.g., on the die side facing the metal pad, and on the other side toward the embedding material). Thus, the risk of delamination may be reduced.

[0036] Figure 2 A schematic cross-sectional view of a die embedded package 200 according to various embodiments is shown. The die embedded package 200 may have a first side 200S1 (bottom side in the drawings) and a second side 200S2 (top side in the drawings). For other elements included in the die embedded package 200, their corresponding sides arranged in the same direction as the first side 200S1 of the die embedded package 200 are also referred to as the first side S1, and the second side (200) S2 is also applicable. The first die 102 may be a double-sided die having a die contact 102M on its first side (referred to as a die contact 102_1MS1) and a second side (referred to as a die contact 102_1MS2).

[0037] The die embedded package 200 may include a first die 102 and a second die 106 (optionally adjacent to each other), the first die 102 being thinner than the second die 106 .

[0038] The first die 102 may, for example, be or include a semiconductor device, such as a field effect transistor, such as a MOSFET. For this type of die, thinning techniques may already exist that allow thinning to a die thickness below 60 μm, below 50 μm, or below 40 μm, such as to a die thickness between 30 μm and 50 μm, such as about 40 μm. In other embodiments, the first die 102 may be any other type of die having a thickness within the range specified above.

[0039] The second die 106 may be, for example, a control die, also referred to as a driver die. As described above, thinning technologies that allow thinning of the control die may not currently exist. The control die may typically have a thickness in the range of about 60 μm to about 100 μm. Optionally, the second die 106 may be a single-sided die having die contacts only on its first side or only on its second side. In other embodiments, the second die 106 may have die contacts on two opposing main sides.

[0040] Therefore, the first die 102 may be thinner than the second die 106 .

[0041] The die embedded package 200 may further include a first encapsulation material 220 (also referred to as the first encapsulation body 220 ) encapsulating the first die 102. The first encapsulation body 220 may be, for example, a molding material, a laminate material, a polyimide / epoxy material, or a combination thereof.

[0042] The total thickness of the first encapsulant 220 and the first die 102 is approximately equal to the thickness of the second die 106 .

[0043] The total thickness of the first encapsulant 220 and the first die 102 being “approximately equal to” the thickness of the second die 106 can be, for example, when the thickness difference (between the total thickness of the first encapsulant 220 and the first die 102 on the one hand and the thickness of the second die 106 on the other hand) is less than 20% (for example, less than 10% or less than 5%) of the thickness of the second die 106.

[0044] The outer surface of the first encapsulation material 220 and the outer surface of the second die 106 may be arranged coplanar. It should be understood that the encapsulated first die 102 and the second die 106 are arranged on a common plane, each of the dies 102, 106 is arranged on the common plane with one of its major surfaces, wherein the encapsulated first die 102 is arranged on the common plane with the encapsulated side.

[0045] Fig. 7A and Figure 7B Respectively Figure 1 and Figure 2 Essentially the same, but with additional instructions, references, and formulas provided to explain certain effects that may occur using the encapsulated first die 102 .

[0046] exist Figure 2 , Fig. 7A and Figure 7B , the common plane is represented by a line joining two portions of the core 104 that are part of the die embedded package 200. The second die 106 is arranged on the common plane with its die contacts 106M. The encapsulated first die 102 is arranged on the common plane with the encapsulation 220. Therefore, the first die 102 is raised from the common plane by an amount Y that corresponds to the thickness of the encapsulation 220 extending above the die contacts 102M of the first die 102. Therefore, the central plane of the first die 102 is shifted to be closer to the central plane of the second die 106 compared to the case where the first die 102 is arranged on the common plane with its die contacts 102M (for example, in the case where the first die 102 is arranged on the common plane with its die contacts 102M). Figure 1 and Fig. 7A ).

[0047] The die embedded package 200 may further include a second encapsulation material 112 (also referred to as a second encapsulation body 112) encapsulating the encapsulated first die 102 and the second die 106. The second encapsulation body 112 may be, for example, a molding material, a laminate material, a polyimide / epoxy resin material, or a combination thereof. The first encapsulation body 220 and the second encapsulation body 112 may be or include the same material or different materials. The second encapsulation body 112 may not be arranged at the same time as the first encapsulation body 220, but may be arranged after the first encapsulation body 220.

[0048] The die embedded package 200 may further include a first set of conductive vias 102_1VS1 electrically contacting the first die 102 from a first side thereof and a second set of conductive vias 102_1VS2 electrically contacting the first die 102 from a second side thereof opposite to the first side.

[0049] The die embedded package 200 may further include a third set of conductive vias 106V (also referred to herein as vias 106VS1, see for example) electrically contacting the second die 106 from the first side of the second die 106. Figure 2 or Fig. 7A ) or a third set of conductive vias 106V (also referred to herein as vias 106VS2, see, for example, Fig. 9 ).

[0050] In double-sided chip embedding (CE2), the thickness of the die embedded package 100 can generally be determined by the thickest component, such as the embedded die 106 and / or the core. The thickest embedded die 106 (and / or the core 104) can generally be arranged approximately in the center between the top surface and the bottom surface of the die embedded package 100.

[0051] According to the prior art, due to the processes involved, one outer surface of the thinner die 102 may be arranged coplanar with one of the centrally arranged thicker components 104, 106, which means that the thinner die 102 is not substantially vertically centered, but is offset to one side thereof that is coplanar with the thicker components 104, 106. This effect is, for example, Figure 1 , Figure 3 , Figure 5 and Fig. 7A Subsequently, the thinner die 102 is contacted by vias 102_1VS1 from the first side and micro vias 102_1VS2 from the second side, so that the micro vias 102_1VS1 on the first side (where the component and the thinner die are coplanar) are much shorter (shorter by an amount Y, see Fig. 7AThis length difference in the micro via 102V makes the design rules, laser drilling and plating process (via filling) more complicated.

[0052] Additionally, asymmetric via lengths may cause the package to warp.

[0053] In addition, if Figure 3 As shown, due to the characteristic tapered shape of the micro vias, the significant difference in length between the via 102_1VS1 from the first side and the micro via 102_1VS2 from the second side may result in different sizes of the areas where the micro vias 102_1VS1 and 102_1VS2 interface with the die contacts 102_1MS1 and 102_1MS2, respectively. In other words, the shorter micro via has a larger interface area (given by the Figure 3 ), which is also undesirable.

[0054] By effectively decoupling the thickness of the (semiconductor portion) of the die 102 from its arrangement in the die embedded package 200, micro vias 102_1VS1, 102_1VS2 of equal or substantially equal lengths can be obtained, thereby avoiding the above-mentioned problem. Figure 2 , Figure 4 , Fig. 6A , Figure 6B , Figure 6C and Figure 7B In other words, at least some of the vias 102_1VS1 in the first group of conductive vias and at least some of the vias 102_1VS2 in the second group of conductive vias may have the same via length.

[0055] In various embodiments, the die embedded package 200 may include a core 104. The core 104 may include or consist of an electrically insulating or conductive material or a combination thereof, for example as commonly used in the art. The core 104 may include at least one opening that may extend completely or partially through the core 104.

[0056] In the at least one opening, the first die 102 and the second die 106 are arranged. The first die 102 and the second die 106 may be arranged in a common opening (eg, Figure 2 , Figure 4 , FIG. 6A to FIG. 6C and Figure 7B Alternatively, the first die 102 and the second die 106 may be arranged in separate openings.

[0057] In various embodiments, the die-embedded package 200 may optionally further include at least one additional first die 102_2, and (each additional first die 102_2 having) an additional first set of conductive vias 102_2VS1 electrically contacting the additional first die 102_2 from a first side of the first die 102_2, and an additional second set of conductive vias 102_2VS2 electrically contacting the additional first die 102_2 from a second side of the additional first die 102_2, the second side being opposite to the first side.

[0058] The relative arrangement of the dies 102_1, 102_2, 106 with respect to each other may depend on the desired application. For example, all of the dies 102_1, 102_2, 106 may be located in separate openings of the core 104; all of the dies 102_1, 102_2, 106 may be located in the same opening (see, for example, Figure 2 , FIG. 6A to FIG. 6C and Figure 7B ); two of the dies (eg, 102_1, 106) may be located in a common opening, while one or more of the other dies (eg, 102_2) may be located in different openings (eg, see Fig. 9 )wait.

[0059] In various embodiments, the first die 102_1 and the further first die 102_2 may be arranged together in the first encapsulation 220 .

[0060] In various embodiments, the further first die 102_2 may be arranged in a further first encapsulation 220 separate from the first encapsulation 220 .

[0061] In various embodiments, more than two first dies 102_1 may be arranged together in the first encapsulation body 220 .

[0062] The absolute orientation and relative orientation of the first die 102, the second die 106, and the optional additional die (eg, the additional first die 102_2) can be selected as desired. Figure 2 , FIG. 6A to FIG. 6C and Figure 7BA flip configuration of two (or optionally similar or identical) first dies 102_1, 102_2 is shown. In those exemplary embodiments, the first dies 102_1, 102_2 may be, for example, transistors, such as power transistors, such as SFETs. One of the first dies (e.g., 102_1) may be oriented with its drain contact toward the first side of the die embedded package 200, while the other first die 102_2 may be arranged with its source contact and gate contact toward the first side of the die embedded package 200. Other embodiments may require that the two first dies 102 have the same orientation, etc.

[0063] FIG. 8B to FIG. 8E Each of them shows a schematic top view and a schematic cross-sectional view of the first die 102 with the first encapsulation material 220 as used in the die embedded package 200 according to various embodiments.

[0064] In various embodiments, the first encapsulation material 220 may be disposed on all sides of the first die 102. The first encapsulation material 220 may completely cover the first die 102 on all sides (eg, Fig. 9 as shown); may include Figure 8C The alignment openings shown may extend partially or completely through the encapsulation material (as an alternative to the openings as alignment indicators, for example, markings on the outside of the die embedded package 200 may be used; the alignment indicators may be used to align the first die during subsequent processing); may be partially (see Fig.8D and Fig. 8E , wherein the first encapsulation material 220 is removed only in the via locations or via row locations) or almost completely (see Figure 8B ) exposes the die contact 102M on the first side and / or the second side of the first die 102; or can be arranged only on one of the main sides of the first die 102, and optionally on a side surface connecting the first side of the first die 102 and the second side of the first die 102.

[0065] Providing the first encapsulant only on either the first side or the second side may be sufficient to adjust the vertical position of the first die 102 within the die embedded package 200, provided that the first encapsulant 220 is arranged to extend further away from the central plane of the first die 102 than the surface of the die contact 102_1M on the same side of the first die 102 (or the semiconductor material of the first die 102). Fig. 10B is shown in the example and also in Fig.11 It is shown in Fig.11 The two dies 102 are included within the same first encapsulation body 220 .

[0066] Fig.12Only the first encapsulation 220 of the die embedded package 200 is shown, which may be constructed with interlocking features 1212, such as a puzzle-piece structure including a protrusion on one of the die embedded packages 200 and a matching recess on another of the die embedded packages 200. This may enable a defined combination of separate die embedded packages 200.

[0067] From a die protection perspective, substantially completely covering the first die 102 may be preferred. Depending on the level of protection provided by the first encapsulant 220, the PCB process can be completed without handling the die. This means that the core competencies of the semiconductor company and the PCB manufacturer remain essentially unchanged, allowing the strengths of both to be used in the final product. This results in higher yields because handling / contamination / ESD issues with the die can be avoided by pre-protecting the die.

[0068] Furthermore, reliability issues due to incorrect handling of the die on the PCB side may also be reduced.

[0069] On the other hand, the adhesion of the protective layer to the die can be achieved by common processes (such as A2, silane, Cu roughening), and is no longer a problem that is not fully solved by the CE2 process.

[0070] In various embodiments ( Fig. 10A 1010 ). The first encapsulating material 220 may be provided with an adhesion promoter 1010 on its outer surface. Although the adhesion promoter 1010 is depicted as an additional layer, any type of adhesion promoter known in the art may be used, such as applying a layer of material such as silane, chemically processing the surface of the first encapsulating material 220 (e.g., plasma processing), mechanically processing the first encapsulating material 220 (e.g., roughening), etc. The adhesion promoter 1010 may be configured to improve the adhesion between the first encapsulating material 220 and the second encapsulating material 112. Although Fig. 10A Treatment of all outer surfaces is shown, but treatment of only a portion of the outer surface of the first encapsulating material 220 may already be beneficial and may be sufficient.

[0071] In various embodiments, the exposed metal surfaces of the first die 102 (and / or the second die 106, and optionally the additional die) may be treated with, for example, an adhesion promoter known in the art, for example by a process similar to that described for the first encapsulation material 220 and tuned for the metal material. For example, Cu roughening may be used.

[0072] Fig. 9 A method of forming a die embedded package 200 according to various embodiments, such as described above, is shown in the form of a series of individual panels.

[0073] The method may include encapsulating the first die 102 with a first encapsulation material 220, the first die 102 being thinner than the second die 106, wherein the total thickness of the first encapsulation material 220 and the first die 102 is approximately equal to the thickness of the second die 106 (this is in Fig. 9 In panel a), the first die 102 has been encapsulated by the first encapsulation material 220 .

[0074] The method may further include arranging the encapsulated first die 102 and the second die 106. The die 102, 106 may be arranged, for example, on a temporary carrier 990, for example in an opening of the core 104, wherein an outer surface of the first encapsulation material 220 and an outer surface of the second die 106 are arranged coplanar (see panel a)).

[0075] The method may further comprise encapsulating the encapsulated first die 102 and the second die 106 with a second encapsulation material 112. This may be achieved, for example, by laminating the dies 102, 106 (and the core 104) with the laminating material 112 from the second side, optionally with a metal layer, such as a top redistribution layer 110, for example as a prepreg material with a copper layer (see panel b)), followed by removing the temporary carrier 990 (see panel c)), and arranging a bottom portion of the second encapsulation material 112, such as another laminating material 112, optionally with a second metal layer, such as a bottom redistribution layer 110 (see panel d)).

[0076] The method may also include electrically contacting the first die 102 from a first side of the first die 102 by forming a first group of conductive vias 102_1VS1, electrically contacting the first die 102 from a second side of the first die 102 by forming a second group of conductive vias 102_1VS2, the second side being opposite to the first side, and electrically contacting the second die 106 from a first side of the second die 106 or (as shown in panel e) from a second side of the second die 106 by forming a third group of conductive vias 106VS2.

[0077] Fig.13 A flow chart 1300 of a method of forming a die embedded package according to various embodiments is shown.

[0078] The method may include: encapsulating a first die with a first encapsulation material, the first die being thinner than a second die, wherein a total thickness of the first encapsulation and the first die is approximately equal to a thickness of the second die (1310); arranging the first die and the second die so that an outer surface of the first encapsulation material and an outer surface of the second die are arranged coplanarly (1320); encapsulating the encapsulated first die and the second die with a second encapsulation material (1330); electrically contacting the first die from a first side of the first die by forming a first group of conductive vias (1340); electrically contacting the first die from a second side of the first die by forming a second group of conductive vias, the second side being opposite to the first side (1350); and electrically contacting the second die from a first side of the second die or from a second side of the second die by forming a third group of conductive vias (1360).

[0079] Figure 4 A schematic cross-sectional view of a die embedded package 400 according to various embodiments is shown.

[0080] In the above description, the second die 106 is the main reason why the thickness of the die embedded package 200 cannot be selected to be suitable for the (small) thickness of the first die 102 .

[0081] However, other constraints may also lead to similar situations, where the die embedded package 400 may include only a single first die 102, or alternatively include multiple single first dies 102. For example, the core 104 may define the thickness of the die embedded package 400 and may be (e.g., significantly) thicker than the first die 102.

[0082] In this case, a similar strategy as described above for the embodiment including both the first die 102 and the second die 106 may be employed.

[0083] In various embodiments, such as Figure 4 As shown, the die-embedded package 400 may include a die 102, a first encapsulation material 220 encapsulating the first die 102, a second encapsulation material 112 encapsulating the encapsulated first die 102, a first group of conductive vias 102_1VS1 electrically contacting the first die 102 from a first side of the first die 102, and a second group of conductive vias 102_1VS2 electrically contacting the first die 102 from a second side of the first die 102, the second side being opposite to the first side, wherein at least some of the first group of conductive vias 102_1VS1 and at least some of the second group of conductive vias 102_1VS2 have the same via length.

[0084] Regarding other characteristics of the die embedded package 400 , the above descriptions related to the die embedded package 200 are applicable, such as the materials and processes used, thickness, advantages of having approximately symmetrical via lengths, etc.

[0085] Various examples are described below:

[0086] Example 1 is a die-embedded package. The die-embedded package may include: a first die and a second die, the first die being thinner than the second die; a first encapsulation material encapsulating the first die, wherein the total thickness of the first encapsulation and the first die is approximately equal to the thickness of the second die, and wherein the outer surface of the first encapsulation material and the outer surface of the second die are arranged coplanar; a second encapsulation material encapsulating the encapsulated first die and the second die; a first group of conductive vias electrically contacting the first die from a first side of the first die and a second group of conductive vias electrically contacting the first die from a second side of the first die, the second side being opposite to the first side; and a third group of conductive vias electrically contacting the second die from the first side of the second die or from the second side of the second die.

[0087] In Example 2, the subject matter of Example 1 can optionally include at least some of the first group of conductive vias and at least some of the second group of conductive vias having the same via length.

[0088] In Example 3, the subject matter of Example 1 or 2 can optionally include: the first die having a thickness between approximately 30 μm and 50 μm.

[0089] In Example 4, the subject matter of any one of Examples 1 to 3 can optionally include that the first die is a double-sided die having die contacts on a first side thereof and on a second side thereof.

[0090] In Example 5, the subject matter of Example 4 can optionally include the die contacts on the first side of the first die being connected to the first set of vias and the die contacts on the second side of the first die being connected to the second set of vias.

[0091] In Example 6, the subject matter of any one of Examples 1 to 5 can optionally include that the second die is a single-sided die having die contacts only on a first side thereof.

[0092] In Example 7, the subject matter of Example 6 can optionally include the die contacts on the first side of the second die being connected to the third set of vias.

[0093] In Example 8, the subject matter of Example 4 or 5 can optionally include: the surface area of ​​each via in the first group of vias at the die contact portion on the first side of the first die is approximately the same as the surface area of ​​each via in the second group of vias at the die contact portion on the second side of the first die.

[0094] In Example 9, the subject matter of any of Examples 1 to 8 can optionally further include a core comprising an opening, wherein the first die and the second die are arranged in the opening.

[0095] In Example 10, the subject matter of Example 9 can optionally include the opening extending completely or partially through the core.

[0096] In Example 11, the subject matter of any one of Examples 1 to 10 can optionally include the first encapsulation material being disposed on all sides of the first die.

[0097] In Example 12, the subject matter of any one of Examples 1 to 11 can optionally include that the first encapsulation material is arranged to expose die contacts on the first side and / or on the second side of the first die.

[0098] In Example 13, the subject matter of any one of Examples 1 to 12 can optionally include that the first encapsulation material is arranged to expose die contacts on the first side and / or on the second side of the first die only in via locations.

[0099] In Example 14, the subject matter of any one of Examples 1 to 11 can optionally include that the first encapsulation material is arranged to completely encapsulate the first die, optionally completely encapsulating the first die except for alignment marks.

[0100] In Example 15, the subject matter of Example 14 can optionally include the alignment mark extending partially or completely through the encapsulation material.

[0101] In Example 16, the subject matter of any one of Examples 1 to 15 can optionally include the first die and the second die being arranged adjacent to each other.

[0102] In Example 17, the subject matter of Example 4 or 5 can optionally include that the first encapsulation is arranged to extend further away from a central plane of the first die than surfaces of the die contacts on a same side of the first die.

[0103] In Example 18, the subject matter of any one of Examples 1 to 17 can optionally include: the first encapsulating material being provided with an adhesion promoter on an outer surface thereof.

[0104] In Example 19, the subject matter of any one of Examples 1 to 15 may optionally further include an additional first die, and an additional first set of conductive vias electrically contacting the additional first die from a first side of the first die and an additional second set of conductive vias electrically contacting the additional first die from a second side of the additional first die, the second side being opposite to the first side.

[0105] In Example 20, the subject matter of Example 19 can optionally include that the first die and the additional first die are arranged together in the first package.

[0106] In Example 21, the subject matter of Example 19 can optionally include that the additional first die is disposed in an additional first encapsulation separate from the first encapsulation.

[0107] In Example 22, the subject matter of any one of Examples 1 to 21 can optionally include that the first die is a power semiconductor die.

[0108] In Example 23, the subject matter of any one of Examples 1 to 22 can optionally include that the second die is a control die.

[0109] Example 24 is a die-embedded package. The die-embedded package may include a die, a first encapsulation material encapsulating the first die, a second encapsulation material encapsulating the encapsulated first die, a first set of conductive vias electrically contacting the first die from a first side of the first die, and a second set of conductive vias electrically contacting the first die from a second side of the first die, the second side being opposite to the first side, wherein at least some of the first set of conductive vias and at least some of the second set of conductive vias have the same via length.

[0110] In Example 25, the subject matter of Example 24 can optionally further include a core comprising an opening, wherein the die is disposed in the opening.

[0111] Example 26 is a method of forming a die embedded package. The method may include: encapsulating a first die with a first encapsulation material, the first die being thinner than a second die, wherein the total thickness of the first encapsulation and the first die is approximately equal to the thickness of the second die; arranging the first die and the second die so that an outer surface of the first encapsulation material and an outer surface of the second die are arranged coplanar; encapsulating the encapsulated first die and the second die with a second encapsulation material; electrically contacting the first die from a first side of the first die by forming a first set of conductive vias; electrically contacting the first die from a second side of the first die by forming a second set of conductive vias, the second side being opposite to the first side; and electrically contacting the second die from a first side of the second die or from a second side of the second die by forming a third set of conductive vias.

[0112] In Example 27, the subject matter of Example 26 can optionally include at least some of the first set of conductive vias and at least some of the second set of conductive vias having the same via length.

[0113] In Example 28, the subject matter of Example 26 or 27 can optionally include the first die having a thickness between approximately 30 μm and 50 μm.

[0114] In Example 29, the subject matter of any one of Examples 26 to 28 can optionally include that the first die is a double-sided die having die contacts on a first side thereof and on a second side thereof.

[0115] In Example 30, the subject matter of Example 29 can optionally include the die contacts on the first side of the first die being connected to the first set of vias and the die contacts on the second side of the first die being connected to the second set of vias.

[0116] In Example 31, the subject matter of any one of Examples 26 to 30 can optionally include that the second die is a single-sided die having die contacts only on a first side thereof.

[0117] In Example 32, the subject matter of Example 31 can optionally include the die contacts on the first side of the second die being connected to the third set of vias.

[0118] In Example 33, the subject matter of Example 29 or 30 may optionally include: the surface area of ​​each via in the first group of vias at the die contact portion on the first side of the first die is approximately the same as the surface area of ​​each via in the second group of vias at the die contact portion on the second side of the first die.

[0119] In Example 34, the subject matter of any one of Examples 26 to 33 can optionally further include a core comprising an opening, wherein the first die and the second die are arranged in the opening.

[0120] In Example 35, the subject matter of Example 34 can optionally include the opening extending completely or partially through the core.

[0121] In Example 36, the subject matter of any one of Examples 26 to 35 can optionally further include encapsulating the first die with a first encapsulation material including disposing the encapsulation material on all sides of the first die.

[0122] In Example 37, the subject matter of any one of Examples 26 to 33 can optionally further include encapsulating the first die with a first encapsulation material including arranging the first encapsulation material to expose die contacts on the first side and / or on the second side of the first die.

[0123] In Example 38, the subject matter of any one of Examples 26 to 37 can optionally further include encapsulating the first die with the first encapsulation material including arranging the first encapsulation material to expose die contacts on the first side and / or the second side of the first die only in via locations.

[0124] In Example 39, the subject matter of any one of Examples 26 to 33 can optionally further include encapsulating the first die with a first encapsulation material including arranging the first encapsulation material to completely encapsulate the first die, optionally completely encapsulating the first die except for alignment marks.

[0125] In Example 40, the subject matter of Example 39 can optionally include: the alignment mark extending partially or completely through the encapsulation material.

[0126] In Example 41, the subject matter of any one of Examples 26 to 40 can optionally further include: the first die and the second die being arranged adjacent to each other.

[0127] In Example 42, the subject matter of any one of Examples 26 to 41 can optionally further include: the first encapsulation being arranged to extend further away from a central plane of the first die than surfaces of the die contacts on a same side of the first die.

[0128] In Example 43, the subject matter of any one of Examples 26 to 42 can optionally further include: an adhesion promoter is provided on an outer surface of the first encapsulating material.

[0129] In Example 44, the subject matter of any one of Examples 26 to 43 may optionally further include: arranging an additional first die, and

[0130] electrically contacting the further first die from a first side of the further first die through a further first set of conductive vias, and

[0131] The further first die is electrically contacted from a second side of the further first die through a further second set of electrically conductive vias electrically contacting the further first die from a second side of the further first die, the second side being opposite to the first side.

[0132] In Example 45, the subject matter of Example 44 can optionally include that the first die and the additional first die are arranged together in the first package.

[0133] In Example 46, the subject matter of Example 44 can optionally include that the additional first die is disposed in an additional first encapsulation separate from the first encapsulation.

[0134] In Example 47, the subject matter of any one of Examples 26 to 42 may optionally further include: the first die is a power semiconductor die.

[0135] In Example 48, the subject matter of any one of Examples 26 to 33 may optionally further include: the second die is a control die.

[0136] Although the present invention has been particularly shown and described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and therefore, it is intended to cover all changes within the equivalent meaning and scope of the claims.

Claims

1. A bare chip embedded package, comprising: a first die and a second die, the first die being thinner than the second die; a first encapsulation material encapsulating the first die, wherein a total thickness of the first encapsulation material and the first die is approximately equal to a thickness of the second die, and an outer surface of the first encapsulation material and an outer surface of the second die are arranged coplanar; a second encapsulation material encapsulating the encapsulated first die and the second die; a first set of conductive vias electrically contacting the first die from a first side of the first die and a second set of conductive vias electrically contacting the first die from a second side of the first die, the second side being opposite the first side; and A third set of conductive vias electrically contacts the second die from the first side of the second die or from the second side of the second die.

2. The bare die embedded package according to claim 1, in, At least some of the first set of conductive vias and at least some of the second set of conductive vias have the same via length.

3. The bare die embedded package according to claim 1 or 2, in, The thickness of the first die is between about 30 μm and 50 μm.

4. The bare die embedded package according to any one of claims 1 to 3, in, The first die is a double-sided die having die contacts on a first side thereof and on a second side thereof.

5. The bare die embedded package according to claim 4, in, The die contacts on a first side of the first die are connected to the first set of vias and the die contacts on a second side of the first die are connected to the second set of vias.

6. The bare die embedded package according to any one of claims 1 to 5, in, The second die is a single-sided die having die contacts only on a first side thereof.

7. The bare die embedded package according to claim 6, in, The die contacts on the first side of the second die are connected to the third set of vias.

8. The bare die embedded package according to claim 4 or 5, in, The surface area of ​​each via in the first set of vias at the die contact on the first side of the first die is approximately the same as the surface area of ​​each via in the second set of vias at the die contact on the second side of the first die.

9. The bare die embedded package according to any one of claims 1 to 8, wherein: The bare die embedded package further comprises: Including an open core, The first die and the second die are arranged in the opening.

10. The bare die embedded package according to claim 9, in, The opening extends completely or partially through the core.

11. The bare die embedded package according to any one of claims 1 to 10, in, The first encapsulation material is disposed on all sides of the first die.

12. The bare die embedded package according to any one of claims 1 to 11, in, The first encapsulation material is arranged to expose die contacts on the first side and / or on the second side of the first die.

13. The bare die embedded package according to any one of claims 1 to 12, in, The first encapsulation material is arranged to expose die contacts on the first side and / or on the second side of the first die only in via locations.

14. The bare die embedded package according to any one of claims 1 to 11, in, The first encapsulation material is arranged to completely encapsulate the first die, optionally except for alignment marks.

15. The bare die embedded package according to claim 14, in, The alignment mark extends partially or completely through the encapsulation material.

16. The bare die embedded package according to any one of claims 1 to 15, in, The first die and the second die are arranged adjacent to each other.

17. The bare die embedded package according to claim 4 or 5, in, The first encapsulation material is arranged to extend further away from a central plane of the first die than surfaces of the die contacts on a same side of the first die.

18. The bare die embedded package according to any one of claims 1 to 17, in, The first encapsulating material is provided with an adhesion promoter on its outer surface.

19. The bare die embedded package according to any one of claims 1 to 15, wherein: The bare die embedded package further comprises: another first die; and A further first set of conductive vias electrically contacts the further first die from a first side of the first die and a further second set of conductive vias electrically contacts the further first die from a second side of the further first die, the second side being opposite to the first side.

20. The bare die embedded package according to claim 19, in, The first die and the further first die are arranged together in the first encapsulation material.

21. The bare die embedded package according to claim 19, in, The further first die is arranged in a further first encapsulation material separate from the first encapsulation material.

22. The bare die embedded package according to any one of claims 1 to 21, wherein: The first die is a power semiconductor die.

23. The bare die embedded package according to any one of claims 1 to 22, wherein: The second die is a control die.

24. A bare chip embedded package, comprising: Bare chips; a first encapsulation material encapsulating the first die; a second encapsulation material encapsulating the encapsulated first die; a first set of conductive vias electrically contacting the first die from a first side of the first die and a second set of conductive vias electrically contacting the first die from a second side of the first die, the second side being opposite the first side, wherein at least some of the first set of conductive vias and at least some of the second set of conductive vias have the same via length.

25. The bare die embedded package according to claim 24, wherein: The bare die embedded package further comprises: Including an open core, Wherein, the die is arranged in the opening.

26. A method of forming a bare die embedded package, the method comprising: encapsulating a first die with a first encapsulation material, the first die being thinner than a second die, wherein a combined thickness of the first encapsulation material and the first die is approximately equal to a thickness of the second die; Arranging the first die and the second die such that an outer surface of the first encapsulation material and an outer surface of the second die are arranged coplanarly; encapsulating the encapsulated first die and the second die with a second encapsulation material; electrically contacting the first die from a first side of the first die by forming a first set of conductive vias; electrically contacting the first die from a second side of the first die, the second side opposite the first side, by forming a second set of conductive vias; and The second die is electrically contacted from a first side of the second die or from a second side of the second die by forming a third set of conductive vias.

27. The method according to claim 26, in, At least some of the first set of conductive vias and at least some of the second set of conductive vias have the same via length.

28. The method according to claim 26 or 27, in, The thickness of the first die is between about 30 μm and 50 μm.

29. The method according to any one of claims 26 to 28, in, The first die is a double-sided die having die contacts on a first side thereof and on a second side thereof.

30. The method according to claim 29, in, The die contacts on a first side of the first die are connected to the first set of vias and the die contacts on a second side of the first die are connected to the second set of vias.

31. The method according to any one of claims 26 to 30, in, The second die is a single-sided die having die contacts only on a first side thereof.

32. The method according to claim 31, in, The die contacts on the first side of the second die are connected to the third set of vias.

33. The method according to claim 29 or 30, in, The surface area of ​​each via in the first set of vias at the die contact on the first side of the first die is approximately the same as the surface area of ​​each via in the second set of vias at the die contact on the second side of the first die.

34. A method according to any one of claims 26 to 33, wherein: The method further comprises: Including an open core, The first die and the second die are arranged in the opening.

35. The method according to claim 34, in, The opening extends completely or partially through the core.

36. The method according to any one of claims 26 to 35, in, Encapsulating the first die with a first encapsulation material includes disposing the encapsulation material on all sides of the first die.

37. The method according to any one of claims 26 to 36, in, Encapsulating the first die with a first encapsulation material includes arranging the first encapsulation material to expose die contacts on a first side and / or on a second side of the first die.

38. The method according to any one of claims 26 to 37, in, Encapsulating the first die with a first encapsulation material includes arranging the first encapsulation material to expose die contacts on the first side and / or on the second side of the first die only in via locations.

39. The method according to any one of claims 26 to 38, in, Encapsulating the first die with a first encapsulation material includes arranging the first encapsulation material to completely encapsulate the first die, optionally except for alignment marks.

40. The method according to claim 39, in, The alignment mark extends partially or completely through the encapsulation material.

41. The method according to any one of claims 26 to 40, in, The first die and the second die are arranged adjacent to each other.

42. The method according to claim 26 or 41, in, The first encapsulation material is arranged to extend further away from a central plane of the first die than surfaces of the die contacts on a same side of the first die.

43. The method according to any one of claims 26 to 42, wherein: The method further comprises: An adhesion promoter is disposed on the outer surface of the first encapsulating material.

44. A method according to any one of claims 26 to 43, wherein: The method further comprises: arranging additional first dies; and electrically contacting the further first die from a first side of the further first die through a further first set of electrically conductive vias; and The further first die is electrically contacted from a second side of the further first die through a further second set of electrically conductive vias electrically contacting the further first die from a second side of the further first die, the second side being opposite to the first side.

45. The method according to claim 44, in, The first die and the further first die are arranged together in the first encapsulation material.

46. ​​The method according to claim 44, in, The further first die is arranged in a further first encapsulation material separate from the first encapsulation material.

47. The method according to any one of claims 26 to 46, wherein: The first die is a power semiconductor die.

48. The method according to any one of claims 26 to 47, wherein: The second die is a control die.

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