Chip

Abstract

The present disclosure provides a chip, comprising: a substrate having a heat dissipation side for setting an interface heat conduction material; the net-shaped structure is connected to the heat dissipation side of the substrate and is made of a heat conduction material; and the heat conductivity of the heat conduction material is greater than that of the material on the heat dissipation side of the substrate.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip packaging, and in particular to a chip. Background Art

[0002] The heat generated by chip operation can be conducted to the heat dissipation boundary (such as a heat sink) through the interface thermal conductive material (TIM).

[0003] However, TIM is prone to slippage, pumping out, edge degradation, voids, etc., resulting in reduced heat dissipation effect. Summary of the invention

[0004] The present disclosure provides a chip.

[0005] In a first aspect, an embodiment of the present disclosure provides a chip, comprising:

[0006] A substrate having a heat dissipation side for disposing an interface thermal conductive material;

[0007] A mesh structure made of a heat-conducting material connected to the heat-dissipating side of the substrate; the thermal conductivity of the heat-conducting material is greater than the thermal conductivity of the material on the heat-dissipating side of the substrate.

[0008] In the disclosed embodiment, a "bumpy" mesh structure is provided on the heat dissipation side of the substrate. After the TIM is coated, the TIM will enter the "concave part" of the mesh structure at some positions, so that the mesh structure can exert horizontal resistance on the TIM to prevent the movement of the TIM and avoid problems such as slippage, pumping out, and edge degradation of the TIM. The mesh structure also divides the TIM into multiple relatively small parts to a certain extent, thereby reducing the risk of voids (especially large voids), avoiding over-temperature problems of the chip after long-term use, and improving packaging reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the accompanying drawings of the embodiments of the present disclosure:

[0010] Figure 1 A schematic cross-sectional structure diagram of a chip provided in an embodiment of the present disclosure;

[0011] Figure 2 A schematic cross-sectional view of another chip provided in an embodiment of the present disclosure;

[0012] Figure 3 A schematic diagram of a top view structure of another chip provided in an embodiment of the present disclosure;

[0013] Figure 4 A schematic cross-sectional structure diagram of a chip after packaging provided by an embodiment of the present disclosure;

[0014] Figure 5 A schematic cross-sectional structure diagram of another chip after packaging provided by an embodiment of the present disclosure;

[0015] In the embodiments of the present disclosure, the meanings of the figure marks are: 1. substrate; 12. device layer; 13. base plate; 14. connecting pin; 15. bump; 181. first fixed blind hole; 182. second fixed blind hole; 19. heat dissipation side; 2. mesh structure; 3. fixing column; 4. TIM; 5. packaging structure; 6. PCB. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the chip provided by the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0017] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0018] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0019] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0020] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0021] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0023] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0024] As chip manufacturing processes shrink towards smaller sizes, the power consumption and heat flux density of chips continue to rise. In addition, the rapid development of 2.5D and 3D heterogeneous chip technologies has made chip heat dissipation an important issue.

[0025] In some related technologies, a thermal interface material (TIM) such as silicone grease can be applied to the back side of the substrate of the chip (such as a bare die), and then a packaging structure such as a heat sink and a protective cover (Lid) is pressed on the other side of the TIM (specifically TIM1 or TIM1.5), and then the TIM is cured. Thus, the TIM is connected between the chip and the packaging structure, and a large amount of heat generated during the operation of the chip (such as more than 95% of the heat for a high-power chip) can be conducted through the TIM to the heat dissipation interface for dissipation.

[0026] To ensure good contact with the substrate and the packaging structure, TIM is usually a material such as silicone grease that has a certain fluidity (or deformability). Therefore, the chip can only be used after the TIM is solidified.

[0027] However, such TIMs are also prone to softening due to high temperatures during use, and creep, expand, shrink, etc., causing the TIM to slip, pump out, edge degradation, etc., or voids to appear inside the TIM (for example, when using indium TIM for large-size flip chip ball grid array FCBGA packaging, the void size can reach 2*2mm level), resulting in the TIM being unable to transfer heat between the substrate and the packaging structure well, and over-temperature problems are likely to occur after long-term use, reducing packaging reliability.

[0028] First, refer to Figures 1 to 5 , an embodiment of the present disclosure provides a chip.

[0029] The chip provided in the embodiment of the present disclosure is a relatively independent computing device with data processing capability.

[0030] The chip of the embodiment of the present disclosure may be of any type, such as a central processing unit (CPU), and in particular may be a high-power chip that generates a large amount of heat and has high requirements for heat dissipation performance.

[0031] Reference Figure 1 , Figure 4 , the chip of the embodiment of the present disclosure includes:

[0032] A substrate 1 having a heat dissipation side 19 for arranging an interface thermal conductive material;

[0033] A mesh structure 2 made of a heat-conducting material connected to the heat-dissipating side 19 of the substrate 1 ; the thermal conductivity of the heat-conducting material is greater than the thermal conductivity of the material of the heat-dissipating side 19 of the substrate 1 .

[0034] Reference Figure 1 The chip of the embodiment of the present disclosure includes a substrate 1, which is a semiconductor base (such as a silicon base) serving as a basis for forming various structures in the chip.

[0035] For example, refer to Figure 2 The substrate 1 may be a wafer, and the chip further includes a device layer 12 disposed on one side of the substrate 1, and the device layer 12 is connected to a substrate 13 through a Bump 15 (connection protrusion) and the like. The substrate 13 is encapsulated with wiring for connecting the device, and the other side of the substrate 13 is provided with connecting pins 14 (such as a ball grid array BGA) connected to the wiring, and the connecting pins 14 are used to connect to a printed circuit board (PCB6), thereby connecting the device in the substrate 1 to the PCB6.

[0036] Therefore, the substrate 1 and the above device layer 12, Bump 15 and other structures can be regarded as unpackaged bare die (bare chip), and the bare die can be packaged and then used as a complete chip (Chip). It can adopt the 2D packaging method of chip flip (FC, Flip Chip), or other packaging forms such as 2.5D packaging and 3D packaging.

[0037] Part of the surface plane of the substrate 1 (such as the surface of the wafer facing away from the device layer 12) is used to contact the interface thermal conductive material (TIM) after packaging, and these surfaces of the substrate 1 are called its "heat dissipation side 19". For example, when a 2D packaging method is adopted, the "front side" of the substrate 1 is used to set the device layer 12, etc., and the "back side" is used to set the TIM4 (that is, the heat dissipation side 19).

[0038] Reference Figure 1 In the chip of the embodiment of the present disclosure, a grid-shaped “mesh structure 2” is provided on the heat dissipation side 19 of the substrate 1, and the mesh structure 2 is composed of a thermally conductive material having better thermal conductivity than the material of the heat dissipation side 19 (such as the semiconductor material of the wafer).

[0039] The specific forms of each "grid" in the above mesh structure are various. For example, it can refer to Figure 3 It is a square composed of mutually perpendicular and equidistant horizontal and vertical bars; or, the above "grid" can also be other shapes such as rectangle, rhombus, triangle, trapezoid, pentagon, hexagon, etc.; or, the above "grid" can also be other irregular, uneven shapes, etc.; or, the shapes and sizes of different grids in the mesh structure can be different.

[0040] In the present disclosure, refer to Figure 4 The heat dissipation side 19 of the substrate 1 is provided with an "uneven" mesh structure 2. After the TIM4 is coated, the TIM4 will enter the "concave part" of the mesh structure 2 at some positions, so that the mesh structure 2 can exert horizontal resistance on the TIM4 to prevent the movement of the TIM4 and avoid problems such as slippage, pumping out, and edge degradation of the TIM4; and the mesh structure 2 also divides the TIM4 into multiple relatively small parts to a certain extent, thereby reducing the risk of voids (especially large voids), avoiding over-temperature problems of the chip after long-term use, and improving packaging reliability.

[0041] On the other hand, the mesh structure 2 is made of a thermally conductive material with better thermal conductivity than the heat dissipation side 19, so the mesh structure 2 can also more effectively conduct the heat generated by the substrate 1 to the TIM4, reduce the junction to case (Rjc) thermal resistance of the 2D package, lower the junction temperature and hot spot temperature, and improve the heat dissipation effect.

[0042] In some embodiments, the thermally conductive material is a metallic material.

[0043] As one mode of an embodiment of the present disclosure, the above thermal conductive material may be a metal (including alloy) material, such as a metal with high thermal conductivity such as copper, aluminum, gold, silver, etc., so the mesh structure 2 may specifically be in the form of a "metal grid".

[0044] In some embodiments, the chip further includes: a connection structure connected to the substrate 1 and the mesh structure 2 respectively.

[0045] As one mode of the embodiment of the present disclosure, a connection structure connected to the substrate 1 may be provided, and the connection structure is also connected to the mesh structure 2 at the same time, so that the connection structure can more firmly connect the mesh structure 2 to the substrate 1 .

[0046] For example, the connection structure and the mesh structure may be an “integrated structure” made of the same material (thermal conductive material) and originally formed as one.

[0047] In some embodiments, reference Figure 2The connection structure includes one or more fixing columns 3 , one end of the fixing column 3 is connected to the substrate 1 , and the other end is connected to the mesh structure 2 .

[0048] As one mode of an embodiment of the present disclosure, the connection structure may include a “columnar” fixing column 3 , and two ends of the fixing column 3 are respectively connected to the substrate 1 and the mesh structure 2 .

[0049] In some embodiments, there are multiple fixing pillars 3 , and the distance between adjacent fixing pillars is between 50 μm and 600 μm.

[0050] The greater the number of fixing posts 3, the better the strengthening effect of the connection between the mesh structure 2 and the substrate 1. However, since the fixing posts 3 need to connect to the substrate 1, they may cause certain damage to the strength of the substrate 1 itself. Therefore, the distribution density of the fixing posts 3 should be moderate. For example, referring to Figure 3 The pitch (d4, Pitch) of the fixed pillars 3 may be 50 to 600 μm, and further may be 100 to 400 μm.

[0051] Reference Figure 2 The heat dissipation side 19 of the substrate 1 is provided with one or more first fixing blind holes 181 ; the fixing pillars 3 are located in the first fixing blind holes 181 .

[0052] Furthermore, the heat dissipation side 19 of the substrate 1 may be formed with a plurality of non-penetrating blind holes (first fixed blind holes 181), for example, the first fixed blind holes 181 are formed on the originally complete heat dissipation side 19 of the substrate 1 (such as the back side of the wafer) by dry etching, wet etching, laser drilling and other processes.

[0053] And refer to Figure 2 , the fixing column 3 can be arranged in the first fixing blind hole 181, so that one end of the fixing column 3 ( Figure 2 The lower end in the figure is equivalent to being connected to substrate 1, while the other end (such as Figure 2 The upper end of the mesh structure 2 is connected to the mesh structure 2.

[0054] For example, refer to Figure 3 The first fixing blind hole 181 may be located at a position where the mesh structure 2 needs to be set, so that when the mesh structure 2 is formed, the thermal conductive material will naturally form a fixing column 3 in the first fixing blind hole 181 .

[0055] There are various specific ways to form the mesh structure 2 and the fixing columns 3 .

[0056] For example, the fixed pillars 3 and the mesh structure 2 can be formed in a "one-time" deposition, or can be formed by "staged" deposition.

[0057] For another example, the specific process used for the above deposition may be electroplating, evaporation, chemical vapor deposition, screen printing, etc.

[0058] For another example, a complete layer of thermally conductive material may be first deposited on the heat dissipation side 19, and then the thermally conductive material in some positions may be removed through a photolithography process, so that the remaining thermally conductive material forms a mesh structure 2 (and fixed columns 3). Alternatively, the thermally conductive material may be directly "only" deposited at corresponding predetermined positions to form a mesh structure 2 (and fixed columns 3).

[0059] It can be seen that the above fixing columns 3 not only better fix the mesh structure 2 on the heat dissipation side 19 of the substrate 1 to prevent the mesh structure 2 from deforming or peeling off from the heat dissipation side 19, but also because the fixing columns 3 penetrate deep into the substrate 1, they can more effectively absorb the heat generated by the substrate 1 and conduct it to the mesh structure 2, further improving the heat dissipation effect.

[0060] The specific cross-sectional shape of the first fixing blind hole 181 is various, such as a round hole (see Figure 3 ), square hole, etc. Of course, the first fixing blind hole 181 can also be in other shapes.

[0061] The specific arrangement of the first fixing blind holes 181 is varied, as shown in FIG. Figure 3 They are arranged in the form of an “array (further a matrix)” and are located at the “crossing” position of the mesh structure 2 .

[0062] It should be understood that the first fixing blind holes 181 may also be distributed in other ways, and may also correspond to other positions of the mesh structure 2 .

[0063] It should be understood that the existence of the first fixed blind hole 181 (and the fixed column 3) cannot affect the function of the device layer 12 of the substrate 1 itself, so the first fixed blind hole 181 must be a blind hole that does not penetrate the substrate 1, that is, the first fixed blind hole 181 cannot reach the device layer 12 (otherwise leakage and other problems may occur).

[0064] In some embodiments, the depth of the first fixing blind hole 181 is between 100 μm and 500 μm; the maximum radial dimension of the first fixing blind hole 181 (i.e., the maximum value of the dimensions of the first fixing blind hole 181 in all directions parallel to the heat dissipation side 19) is between 50 μm and 250 μm.

[0065] Reference Figure 2 Usually, the thickness (d5) of the substrate 1 is hundreds of microns, such as 200-750 μm, so the depth (d2, i.e. the dimension in the direction of penetrating into the substrate 1) of the first fixed blind hole 181 should be smaller than it, such as 100-500 μm, and further 200-400 μm.

[0066] The diameter of each first fixing blind hole 181 should be appropriate. If it is too small, it will be difficult to form the fixing column 3 therein and the fixing column 3 will be insufficient in strength. If it is too large, the strength of the substrate 1 will be significantly reduced. Figure 2 Considering factors such as the diameter-to-depth ratio, the aperture (d3, i.e., the maximum radial dimension) of the first fixed blind hole 181 may be 50 to 250 μm, and may further be 100 to 200 μm.

[0067] Among them, the distribution density of the first fixed blind holes 181 should also be appropriate. Too high a distribution density will also lead to too many holes in the substrate 1 (such as a wafer), affecting its strength and making the substrate 1 fragile; too low a distribution density will lead to insufficient gripping force and thermal conductivity of the fixing column 3, and the mesh structure 2 will be easily deformed or peeled off.

[0068] For example, if each first fixing blind hole 181 is provided with a fixing column 3 , and all the fixing columns 3 are located in the first fixing blind holes 181 , the distribution density of the first fixing blind holes 181 may be the same as the distribution density of the fixing columns 3 .

[0069] It should be understood that the above fixing column 3 does not necessarily cooperate with the first fixing blind hole 181. For example, there may be no first fixing blind hole, and the fixing column 3 may be directly connected to the substrate 1 by welding, bonding, etc.

[0070] It should be understood that the connection structure is not limited to the form of the above-mentioned fixing column 3. For example, the connection structure may also include a "edging" that is stuck on the edge of the substrate 1 and is integrated with the mesh structure 2.

[0071] In some embodiments, a dimension of the mesh structure 2 in a direction facing away from the heat dissipation side 19 of the substrate 1 is between 40 μm and 100 μm.

[0072] Among them, refer to Figure 2 The thickness of the mesh structure 2 (d1, i.e., the dimension in the direction away from the heat dissipation side 19 of the substrate 1) should also be appropriate. If it is too small, it will not play the role of fixing the TIM4. If it is too large, the thickness of the TIM4 will also increase too much, thereby reducing the heat dissipation effect.

[0073] Therefore, considering the usual thickness range of TIM 4 , the thickness of the mesh structure 2 may be 40 μm to 100 μm, and further may be 50 μm to 80 μm.

[0074] In some embodiments, the chip of the embodiment of the present disclosure further includes: an interface TIM4 provided on the heat dissipation side of the substrate 1 and covering the mesh structure 2 .

[0075] As mentioned above, the chip of the embodiment of the present disclosure may be a bare die including only the substrate 1 (of course, it may also have the device layer 12 etc.) and the mesh structure 2 .

[0076] Alternatively, as another embodiment of the present disclosure, refer to Figure 4 The chip may also be a more complete chip after packaging, so it may also include a TIM4 coated on the heat dissipation side of the substrate 1.

[0077] Among them, TIM4 has fluidity when applied (it may be fluid itself or after heating), so that TIM4 will fill in the gaps of the mesh structure 2 and completely cover the mesh structure 2 (that is, the thickness of TIM4 needs to be greater than the thickness of the mesh structure 2).

[0078] Therefore, refer to Figure 5 , and then connected to PCB6, a packaging structure 5 can be further arranged on the side of TIM4 away from the substrate 1, and the surface of the packaging structure 5 close to the chip is in contact with TIM4, so that after TIM4 is solidified, the heat generated during the operation of the substrate 1 can be conducted from its heat dissipation side 19 (including the mesh structure 2) to TIM4, and then conducted from TIM4 to the packaging structure 5.

[0079] The packaging structure 5 is a structure with heat dissipation capability such as a heat sink or a protective cover (Lid).

[0080] Among them, the TIM used in the embodiments of the present disclosure may be in the form of TIM1, TIM1.5, etc.

[0081] In some embodiments, TIM4 includes at least one of an organic thermal conductive material, liquid metal, metal solder paste, and soft metal.

[0082] The TIM 4 used in the embodiment of the present disclosure needs to have fluidity to cover the mesh structure 2 .

[0083] Therefore, TIM4 can specifically be an organic thermally conductive material (also called a first type TIM), such as silicone grease, thermally conductive gel, thermally conductive adhesive, etc.

[0084] Alternatively, the TIM4 may also be a material containing metal (also called a third type of TIM), that is, an indium TIM, such as liquid metal, metal solder paste, soft metal, etc.

[0085] In some embodiments, the size of the mesh structure 2 in the direction away from the heat dissipation side 19 of the substrate 1 is between 40 μm and 100 μm, and the size of the TIM 4 in the direction away from the heat dissipation side 19 of the substrate 1 is between 80 μm and 300 μm.

[0086] Reference Figure 5 , the thickness of TIM4 (d6, i.e., the dimension in the direction away from the heat dissipation side 19 of the substrate 1) must be greater than the thickness (d1) of the mesh structure 2 to ensure that TIM4 can cover the mesh structure 2; and the thickness of TIM4 can generally be 80 to 300 μm, further 120 to 200 μm, and the corresponding thickness of the mesh structure 2 can be 40 μm to 100 μm, further 50 to 80 μm.

[0087] In some embodiments, the strength of the mesh structure 2 is greater than the strength of the TIM 4 .

[0088] As one mode of an embodiment of the present disclosure, the mesh structure 2 may have a higher strength than the TIM4 (TIM4 after curing), so that it may better play the role of fixing the TIM4.

[0089] In some embodiments, the heat dissipation side 19 of the substrate 1 is provided with one or more second fixing blind holes 182 ; the second fixing blind holes 182 are filled with the TIM 4 .

[0090] As one embodiment of the present disclosure, refer to Figure 4 The heat dissipation side 19 of the substrate 1 may also be provided with a second fixing blind hole 182, and the second fixing blind hole 182 is not blocked by the mesh structure 2 and is exposed, so that the TIM4 will also be filled into the second fixing blind hole 182, and the TIM4 in the second fixing blind hole 182 is also connected to the TIM4 outside the heat dissipation side 19, thereby playing a role in assisting the fixing of the TIM4.

[0091] The spacing, depth, aperture, etc. of the second fixing blind holes 182 can be set in combination with the fixing requirements of the TIM4 and the strength requirements of the substrate 1, and will not be described in detail here.

[0092] It should be understood that it can be a reference Figure 2 and Figure 4 , in the chip product, there is only one of the first fixing blind hole 181 (fixing column 3) and the second fixing blind hole 182; or, it can also be a reference Figure 5 The chip product is provided with a first fixing blind hole 181 (fixing column 3) and a second fixing blind hole 182.

[0093] Example 1:

[0094] In the chip of Example 1, an array hole (first fixed blind hole) is formed on the back side (heat dissipation side) of a 450 μm thick wafer (substrate), wherein the hole diameter is 100 μm, the pitch is 300 μm, and the hole depth is 250 μm. The hole is filled with a column (fixed column / connection structure) of metal aluminum (thermal conductive material), and the aluminum material also extends 100 μm beyond the back side of the wafer to form a trapezoidal metal grid (mesh structure).

[0095] In the package, the indiμm TIM (TIM) is first coated on the metal grid with a thickness of 230μm to cover the metal grid; then a heat sink (packaging structure) is set to contact the indiμm TIM, and then the indiμm TIM and the metal grid are integrated through reflow soldering to obtain a TIM without voids.

[0096] Example 2:

[0097] In the chip of Example 2, an array hole (first fixed blind hole) is formed on the back side (heat dissipation side) of a 650 μm thick wafer (substrate), wherein the hole diameter is 200 μm, the pitch is 500 μm, and the hole depth is 400 μm. The hole is filled with a column (fixed column / connection structure) of metal copper (thermal conductive material), and the copper material also extends 30 μm beyond the back side of the wafer and forms a square metal grid (mesh structure).

[0098] In packaging, a thermal conductive gel (TIM) is first coated on the metal grid with a thickness of 80 μm to cover the metal grid; then a Lid (packaging structure) is set in contact with the thermal conductive gel, and then the thermal conductive gel is cured to form an integrated structure with the metal grid.

[0099] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A chip, comprising: A substrate having a heat dissipation side for disposing an interface thermal conductive material; A mesh structure made of a heat-conducting material connected to the heat-dissipating side of the substrate; the thermal conductivity of the heat-conducting material is greater than the thermal conductivity of the material on the heat-dissipating side of the substrate.

2. The chip according to claim 1, wherein: The heat conductive material is a metal material.

3. The chip according to claim 1, wherein: Also includes: A connection structure connected to the substrate and the mesh structure respectively.

4. The chip according to claim 3, wherein: The connection structure includes one or more fixing posts, one end of each fixing post is connected to the substrate, and the other end of each fixing post is connected to the mesh structure.

5. The chip according to claim 4, wherein: There are a plurality of fixing columns, and the distance between adjacent fixing columns is between 50 μm and 600 μm.

6. The chip according to claim 5, wherein: The heat dissipation side of the substrate is provided with one or more first fixing blind holes; The fixing column is located in the first fixing blind hole.

7. The chip according to claim 6, wherein: The depth of the first fixing blind hole is between 100 μm and 500 μm; The maximum radial dimension of the first fixing blind hole is between 50 μm and 250 μm.

8. The chip according to claim 1, wherein: The size of the mesh structure in a direction facing away from the heat dissipation side of the substrate is between 40 μm and 100 μm.

9. The chip according to claim 1, wherein: Also includes: An interface thermal conductive material is provided on the heat dissipation side of the substrate and covers the mesh structure.

10. The chip according to claim 9, wherein: The interface thermal conductive material includes at least one of organic thermal conductive material, liquid metal, metal solder paste, and soft metal.

11. The chip according to claim 9, wherein: The strength of the mesh structure is greater than the strength of the interface thermal conductive material.

12. The chip according to claim 9, wherein: One or more second fixing blind holes are provided on the heat dissipation side of the substrate; The second fixing blind hole is filled with the interface thermal conductive material.

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