Semiconductor element with spacer

Abstract

The invention relates to a semiconductor element. The semiconductor element comprises a substrate; a plurality of word line structures disposed in the substrate; the buried conductive layer comprises a bottom part which is arranged in the substrate and between the word line structures; the top part is arranged in the substrate, on the bottom part and among the word line structures; and the groove inner gap wall is arranged in the substrate and between the word line structures, surrounds the bottom part and is covered by the top part. A top surface of the top portion, a top surface of the substrate and top surfaces of the word line structures are substantially coplanar. A bottom surface of the gap wall in the groove and a bottom surface of the bottom portion are substantially coplanar. One side wall of the gap wall in the groove and one side wall of the top portion are substantially coplanar.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202311150587X, filed on September 7, 2023, with the invention name of “Semiconductor element with spacers”. Application No. 202311150587X claims priority and benefits of U.S. formal application No. 18 / 219,238 filed on July 7, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element, and more particularly to a semiconductor element with a spacer. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the growing demand for computing power. However, various problems arise during the shrinking process, and these problems continue to increase. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] One aspect of the present disclosure provides a semiconductor device, including a substrate; a plurality of word line structures disposed in the substrate; a buried conductive layer, including: a bottom portion disposed in the substrate and between the word line structures; and a top portion disposed in the substrate, on the bottom portion and between the word line structures; and a recessed inner spacer disposed in the substrate and between the word line structures, surrounding the bottom portion and covered by the top portion. A top surface of the top portion, a top surface of the substrate and the top surfaces of the word line structures are substantially coplanar. A bottom surface of the recessed inner spacer is substantially coplanar with a bottom surface of the bottom portion. A side wall of the recessed inner spacer is substantially coplanar with a side wall of the top portion.

[0006] Due to the design of the semiconductor element disclosed in the present invention, the electric field near the buried conductive layer can be reduced by using the spacer in the groove. Therefore, due to the reduction of the electric field, the drain leakage caused by the gate can be reduced. Accordingly, the performance of the semiconductor element will be improved.

[0007] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the disclosure of the present application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which the same reference numerals refer to the same elements.

[0009] Figure 1 is a flow chart illustrating a method for preparing a semiconductor element according to an embodiment of the present disclosure;

[0010] Figure 2 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0011] Figure 3 is a cross-sectional view, showing Figure 2 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0012] Figure 4 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0013] Figure 5 is a cross-sectional view, showing Figure 4 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0014] Figure 6 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0015] Figure 7 is a cross-sectional view, showing Figure 6 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0016] Figure 8 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0017] Figures 9 to 20 is a cross-sectional view, showing Figure 8 The cross-sectional structure taken along the line segments AA' and BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0018] Fig.21is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0019] Fig. 22 is a cross-sectional view, showing Fig.21 The cross-sectional structure taken by the A-A' and B-B' line segments;

[0020] Fig.23 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0021] Fig.24 and Fig.25 is a cross-sectional view, showing Fig.23 The cross-sectional structure taken along the line AA' and the line BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0022] Fig.26 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0023] Fig. 27 and Fig.28 is a cross-sectional view, showing Fig.26 The cross-sectional structure taken along the line AA' and the line BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0024] Fig.29 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0025] Fig.30 and Fig.31 is a cross-sectional view, showing Fig.29 The cross-sectional structure taken along the line segments AA' and BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0026] Fig.32 is a top view illustrating an intermediate semiconductor element in another embodiment of the present disclosure; and

[0027] Fig.33 is a cross-sectional view, showing Fig.32 The cross-sectional structure taken along the A-A' and B-B' lines.

[0028] The reference numerals are described as follows:

[0029] 1A: Semiconductor components

[0030] 1B: Semiconductor components

[0031] 10: Preparation method

[0032] 101: Base

[0033] 101TS: Top

[0034] 103: Pad oxide

[0035] 105: Pad Nitride

[0036] 107: Isolation layer

[0037] 200: Character line structure

[0038] 211: word line dielectric layer

[0039] 211TS: Top

[0040] 213: Character line overlay

[0041] 213BS: Bottom

[0042] 213TS: Top

[0043] 221: Bottom conductive layer

[0044] 223: Intermediate conductive layer

[0045] 225: Top conductive layer

[0046] 225TS: Top

[0047] 231: Bottom padding layer

[0048] 231TS: Top

[0049] 233: Top lining layer

[0050] 233TS: Top

[0051] 301: Spacing wall in groove

[0052] 301SW: Sidewall

[0053] 301BS: bottom surface

[0054] 401: buried conductive layer

[0055] 411: Bottom

[0056] 411BS: Bottom

[0057] 411SW: Sidewall

[0058] 413: Top

[0059] 413SW: Sidewall

[0060] 413TS: Top

[0061] 601: First dielectric material

[0062] 603: Covering material

[0063] 605: Spacer material

[0064] 611: First conductive material

[0065] 613: Second conductive material

[0066] 615: The third conductive material

[0067] 617: Fourth conductive material

[0068] 621: First liner material

[0069] 623: Secondary liner material

[0070] 701: First groove

[0071] 703: Character line groove

[0072] 705: Opening

[0073] 705BS: bottom surface

[0074] 801: First mask

[0075] A: Hatch

[0076] A': Hatch line

[0077] AA: Active Area

[0078] B: Hatch

[0079] B': Hatch line

[0080] DR: Drain

[0081] H1: Height

[0082] H2: Height

[0083] R1: First Area

[0084] R2: Second Area

[0085] S11: Steps

[0086] S13: Steps

[0087] S15: Steps

[0088] S17: Steps

[0089] SR: Source

[0090] T1: Thickness

[0091] VL1: Vertical Level

[0092] W1: Width

[0093] W2: Width

[0094] X: Direction

[0095] Y: direction

[0096] Z: Direction DETAILED DESCRIPTION

[0097] The following description of the present disclosure is accompanied by the drawings which are incorporated into and constitute a part of the specification, and illustrate embodiments of the present disclosure, but the present disclosure is not limited to the embodiments. In addition, the following embodiments can be appropriately integrated to complete another embodiment.

[0098] "One embodiment", "an embodiment", "an exemplary embodiment", "another embodiment", "another embodiment", etc. mean that the embodiment described in the present disclosure may include specific features, structures or characteristics, but not every embodiment must include the specific features, structures or characteristics. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but it can be the same embodiment.

[0099] In order to make the present disclosure fully understood, the following description provides detailed steps and structures. Obviously, the implementation of the present disclosure will not be limited to the specific details known to those skilled in the art. In addition, the known structures and steps are no longer described in detail to avoid unnecessarily limiting the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the claims.

[0100] In the present disclosure, semiconductor elements generally refer to elements that utilize semiconductor characteristics to function. Electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements all fall within the category of semiconductor elements.

[0101] It should be noted that, in the description of the present disclosure, the upper direction (or upward) corresponds to the direction of the Z-direction arrow, and the lower direction (or downward) corresponds to the opposite direction of the Z-direction arrow.

[0102] It should be noted that in the description of the present disclosure, the terms "form", "formation" and "form" may represent and include any creation, construction, patterning, implantation or deposition of an element, a dopant or a material. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching and wet etching.

[0103] It should be noted that, in the description of the present disclosure, the order in which the functions or steps are marked here may be different from the order marked in the figure. For example, depending on the functions or steps involved, two figures shown in succession may actually be executed substantially simultaneously or may sometimes be executed in the opposite order.

[0104] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 is a cross-sectional view, showing Figure 2 The cross-sectional structure taken along the A-A' and B-B' line segments. Figure 4 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 is a cross-sectional view, showing Figure 4 The cross-sectional structure taken along the A-A' and B-B' line segments. Figure 6 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view, showing Figure 6 The cross-sectional structure taken along the A-A' and B-B' line segments. Figure 8 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 9 to 20 is a cross-sectional view, showing Figure 8 The cross-sectional structures taken along the lines AA′ and BB′ in the figure represent a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Fig.21 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig. 22 is a cross-sectional view, showing Fig.21 The cross-sectional structure taken along the A-A' and B-B' lines.

[0105] Reference Figures 1 to 9 In step S11, a substrate 101 is provided, an isolation layer 107 is formed in the substrate 101 to define a plurality of active areas AA, and a plurality of word line trenches 703 are formed in the substrate 101 to divide the active area AA into a plurality of first regions R1 and a plurality of second regions R2.

[0106] Reference Figure 2 and Figure 3 In some embodiments, the substrate 101 may include a bulk semiconductor substrate composed of at least one semiconductor material. The bulk semiconductor substrate may be formed of an elemental semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or other III-V compound semiconductors or II-VI compound semiconductors; or a combination thereof.

[0107] In some embodiments, substrate 101 may include a semiconductor-on-insulator structure, which consists of a processing substrate, an insulator layer, and a topmost semiconductor material layer from bottom to top. The processing substrate and the topmost semiconductor material layer may be formed of the same material as the bulk semiconductor substrate described above. The insulator layer may be a crystalline or non-crystalline dielectric material, such as an oxide and / or a nitride. For example, the insulator layer may be a dielectric oxide, such as silicon oxide. For another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. For another example, the insulator layer may include a stack of dielectric oxides and dielectric nitrides, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulator layer may have a thickness between about 10 nanometers (nm) and about 200 nm. The insulator layer may eliminate leakage currents between adjacent elements in substrate 101 and reduce parasitic capacitance associated with source / drain.

[0108] It should be noted that the term "about" to modify the amount of the ingredients, components or reactants of the present disclosure used refers to possible changes in the value, for example, by the use of making a concentrate or solution. In addition, changes may be caused by unintentional errors in the measurement procedure, differences in the manufacture, source or purity of the ingredients used to prepare the composition or implement the method, etc. On the one hand, the term "about" refers to within 10% of the reported value. On the other hand, the term "about" refers to within 5% of the reported value. In other aspects, the term "about" refers to within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1% of the reported value.

[0109] Reference Figure 2 and Figure 3 A series of deposition processes may be performed to deposit a pad oxide 103 and a pad nitride 105 on the substrate 101. A lithography process may be performed to form a first mask 801 on the pad nitride 105 and define a location of the isolation layer 107.

[0110] Reference Figure 4 and Figure 5 After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a first trench 701 passing through the pad oxide 103 and the pad nitride 105 and extending to the substrate 101. After the first trench 701 is formed, the first mask 801 may be removed.

[0111] Reference Figure 6 and Figure 7 An insulating material such as silicon oxide, silicon nitride, silicon oxynitride or silicon nitride oxide may be deposited into the first trench 701 , and then a planarization process such as chemical mechanical polishing may be performed to remove excess filling material until the top surface of the substrate 101 is exposed to form an isolation layer 107 .

[0112] Reference Figure 6 and Figure 7 , the isolation layer 107 defines a plurality of active regions AA. In some embodiments, the plurality of active regions AA may extend in a direction inclined relative to the X-axis and the Y-axis in a top view.

[0113] It should be noted that each active area AA may include a portion of the substrate 101 and a space above the substrate 101. Describing an element as being disposed on the active area AA means that the element is disposed on the top surface of the portion of the substrate 101. Describing an element as being disposed in the active area AA means that the element is disposed in the portion of the substrate 101; however, the top surface of the element may be flush with the top surface of the portion of the substrate 101. Describing an element as being disposed above the active area AA means that the element is disposed above the top surface of the portion of the substrate 101.

[0114] It should be noted that in the description of the present disclosure, the surface of the element (or feature) at the highest vertical height along the Z axis is referred to as the top surface of the element (or feature). The surface of the element (or feature) at the lowest vertical level along the Z axis is referred to as the bottom surface of the element (or feature).

[0115] It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0116] Reference Figure 8 and Fig. 9 , a plurality of word line grooves 703 are formed in the substrate 101 to define the positions of a plurality of word line structures 200 to be described later. The word line grooves 703 may be formed by a lithography process and a subsequent etching process. In some embodiments, the word line grooves 703 have a linear shape and extend in a direction X and cross the active area AA in a top view. For example, each active area AA may intersect with two word line grooves 703. The word line grooves 703 may divide each active area AA into a plurality of first regions R1 and a plurality of second regions R2. For one active area AA, a first region R1 may be formed between two word line grooves 703, and two second regions R2 may be formed respectively and correspondingly between the isolation layer 107 and the two word line grooves 703.

[0117] Reference Figure 1 and Figures 10 to 22 In step S13 , a plurality of word line structures 200 are formed in the word line trenches 703 .

[0118] Reference Fig.10A layer of a first dielectric material 601 is conformally formed on the pad nitride 105, on the isolation layer 107, and in the word line trench 703. The layer of the first dielectric material 601 may have a U-shaped cross-sectional profile in the word line trench 703. In some embodiments, the layer of the first dielectric material 601 may have a thickness in a range of about 1 nanometer (nm) to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0119] In some embodiments, the layer of the first dielectric material 601 can be formed by a thermal oxidation process. For example, the layer of the first dielectric material 601 can be formed by oxidizing the surface of the word line trench 703. In some embodiments, the layer of the first dielectric material 601 can be formed by a deposition process such as chemical vapor deposition or atomic layer deposition. The first dielectric material 601 can include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a pad polysilicon layer (not shown for clarity), the layer of the first dielectric material 601 can be formed by free radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown for clarity), the layer of the first dielectric material 601 can be formed by free radical oxidation of the pad silicon nitride layer.

[0120] In some embodiments, the high-k material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0121] Reference Fig.11 , a layer of a first conductive material 611 is formed on the layer of the first dielectric material 601 and completely fills the word line trench 703. In some embodiments, the first conductive material 611 can be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the overall chemical potential energy of a material (e.g., a metal) relative to the vacuum energy level.

[0122] For example, in the present embodiment, the first conductive material 611 is titanium nitride, which can be formed by chemical vapor deposition. In some embodiments, the formation of the layer of the first conductive material 611 may include a source gas introduction step, a first purge step, a reactant flow step, and a second purge step. The source gas introduction step, the first purge step, the reactant flow step, and the second purge step can be regarded as one cycle. Multiple cycles can be performed to obtain the desired thickness of the layer of the first conductive material 611.

[0123] In detail, Fig.10The intermediate semiconductor element shown in can be loaded in the reaction chamber. In the source gas introduction step, the source gas containing the precursor and the reactant can be introduced into the reaction chamber containing the intermediate semiconductor element. The precursor and the reactant can diffuse through the boundary layer and reach the surface of the intermediate semiconductor element (that is, the surface of the layer of the first dielectric material 601). The precursor and the reactant can be adsorbed on the above-mentioned surface and then migrate to the above-mentioned surface. The adsorbed precursor and the adsorbed reactant can react on the above-mentioned surface and form solid by-products. The solid by-products can form a core on the above-mentioned surface. The core can grow into an island, and these islands can be merged into a continuous film on the above-mentioned surface. In the first purge step, a purge gas such as argon gas can be injected into the reaction chamber to purge out gaseous by-products, unreacted precursors and unreacted reactants.

[0124] In the reactant flow step, reactants may be introduced separately into the reaction chamber to transform a continuous thin film into a layer of first conductive material 611. In the second purge step, a purge gas such as argon may be injected into the reaction chamber to purge out gaseous byproducts and unreacted reactants.

[0125] In some embodiments, forming the layer of first conductive material 611 using chemical vapor deposition may be performed with the aid of plasma. The plasma source may be, for example, argon, hydrogen, or a combination thereof.

[0126] For example, the precursor may be titanium tetrachloride. The reactant may be ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the surface and form a titanium nitride film containing high chloride contamination. The ammonia in the reactant flow step may reduce the chloride content of the titanium nitride film. After the ammonia treatment, the titanium nitride film may be considered as a layer of the first conductive material 611.

[0127] Alternatively, in some other embodiments, the layer of the first conductive material 611 can be formed by atomic layer deposition, such as light-assisted atomic layer deposition or liquid injection atomic layer deposition. In some embodiments, the formation of the layer of the first conductive material 611 can include a first precursor introduction step, a first purge step, a second precursor introduction step, and a second purge step. The first precursor introduction step, the first purge step, the second precursor introduction step, and the second purge step can be considered as one cycle. Multiple cycles can be performed to obtain the desired thickness of the layer of the first conductive material 611.

[0128] In detail, Fig.10The intermediate semiconductor element shown in can be loaded in the reaction chamber. In the first precursor introduction step, a first precursor can be introduced into the reaction chamber. The first precursor can diffuse through the boundary layer and reach the surface of the intermediate semiconductor element (i.e., the surface of the layer of the first dielectric material 601). The first precursor can be adsorbed on the above-mentioned surface to form a monolayer at the monoatomic layer level. In the first purge step, a purge gas such as argon can be injected into the reaction chamber to purge out the unreacted first precursor.

[0129] In the second precursor introduction step, a second precursor may be introduced into the reaction chamber. The second precursor may react with the monolayer and convert the monolayer into a layer of the first conductive material 611. In the second purge step, a purge gas such as argon may be injected into the reaction chamber to purge out the unreacted second precursor and gaseous byproducts. Compared to chemical vapor deposition, since the first precursor and the second precursor are introduced separately, the generation of particles caused by the gas phase reaction may be suppressed.

[0130] For example, the first precursor may be titanium tetrachloride. The second precursor may be ammonia. The adsorbed titanium tetrachloride may form a titanium nitride monolayer. The ammonia in the second precursor introduction step may react with the titanium nitride monolayer and convert the titanium nitride monolayer into a layer of the first conductive material 611.

[0131] In some embodiments, the formation of the layer of first conductive material 611 using atomic layer deposition can be performed with the help of plasma. The plasma source can be, for example, argon, hydrogen, oxygen, or a combination thereof. In some embodiments, the oxygen source can be, for example, water, oxygen, or ozone. In some embodiments, a co-reactant can be introduced into the reaction chamber. The co-reactant can be selected from hydrogen, hydrogen plasma, oxygen, air, water, ammonia, hydrazine, alkylhydrazine, borane, silane, ozone, and a combination thereof.

[0132] In some embodiments, the formation of the layer of the first conductive material 611 may be performed using the following process conditions. The substrate temperature may be between about 160° C. and about 300° C. The evaporator temperature may be about 175° C. The pressure of the reaction chamber may be about 5 mbar. The solvent of the first precursor and the second precursor may be toluene.

[0133] Reference Fig.12 , a first etch-back process is performed to remove a portion of the first conductive material 611. In some embodiments, in the first etch-back process, an etch rate ratio of the first conductive material 611 to the first dielectric material 601 may be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. After the first etch-back process, the first dielectric material 601 remaining in the word line trench 703 may be regarded as a plurality of bottom conductive layers 221.

[0134] Reference Fig.13 , a layer of a first liner material 621 may be conformally formed on the layer of the first dielectric material 601 and the bottom conductive layer 221. In some embodiments, the first liner material 621 may be a material having an etch selectivity to the first dielectric material 601. In some embodiments, the first dielectric material 601 may be a material having an etch selectivity to the pad nitride 105. In some embodiments, the first liner material 621 may be, for example, a sp 2 In some embodiments, the first liner material 621 may be, for example, a material including carbon having a hexagonal crystal structure. In some embodiments, the first liner material 621 may be, for example, graphene, graphite, etc.

[0135] In some embodiments, a layer of first liner material 621 is formed on a catalyst substrate and then transferred to Fig.12 The catalyst substrate may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, alloys of iron and nickel, alloys of copper and nickel, alloys of nickel and molybdenum, alloys of gold and nickel, and cobalt and copper.

[0136] In some embodiments, the layer of first liner material 621 can be formed with the help of a catalyst. The catalyst can be a single crystal metal or a polycrystalline metal, a binary alloy, or a liquid metal. The single crystal metal or the polycrystalline metal can be, for example, nickel, copper, cobalt, platinum, silver, ruthenium, iridium, or palladium. The binary alloy can be, for example, an alloy of iron and nickel, an alloy of copper and nickel, an alloy of nickel and molybdenum, an alloy of gold and nickel, and an alloy of cobalt and copper. The liquid metal can be, for example, liquid gallium, liquid indium, or liquid copper.

[0137] In some embodiments, a catalytic conductive layer (not shown for clarity) may be conformally formed on the layer of first dielectric material 601 and on the bottom conductive layer 221. A layer of first liner material 621 may be formed on the catalytic conductive layer. The catalytic conductive layer may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, iron-nickel alloy, copper-nickel alloy, nickel-molybdenum alloy, gold-nickel alloy, cobalt alloy, and copper.

[0138] Reference Fig.14 , a layer of second conductive material 613 may be formed on the layer of first liner material 621 and completely fill word line trench 703. In some embodiments, second conductive material 613 may be, for example, tungsten, tungsten nitride, or a combination thereof. In some embodiments, the layer of second conductive material 613 may be formed by, for example, pulse nucleation, chemical vapor deposition, physical vapor deposition, or other applicable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0139] Reference Fig.15, a second etch-back process is performed to remove a portion of the second conductive material 613. In some embodiments, in the second etch-back process, an etch rate ratio of the second conductive material 613 to the first liner material 621 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the second etch-back process, the remaining second conductive material 613 in the word line trench 703 may be regarded as a plurality of intermediate conductive layers 223.

[0140] Reference Fig.16 , a layer of a second liner material 623 may be conformally formed on the layer of the first liner material 621 and the intermediate conductive layer 223. In some embodiments, the second liner material 623 may be a material having an etching selectivity to the first dielectric material 601. In some embodiments, the second liner material 623 may be the same material as the first liner material 621. In some embodiments, the second liner material 623 may be a material having an etching selectivity to the pad nitride 105. In some embodiments, the second liner material 623 may be, for example, a material including sp 2 In some embodiments, the second liner material 623 may be, for example, a material including carbon having a hexagonal crystal structure. In some embodiments, the second liner material 623 may be, for example, graphene, graphite, etc.

[0141] In some embodiments, a layer of second liner material 623 may be formed on a catalyst substrate and then transferred to Fig.15 The catalyst substrate may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, alloys of iron and nickel, alloys of copper and nickel, alloys of nickel and molybdenum, alloys of gold and nickel, and cobalt and copper.

[0142] In some embodiments, the layer of second liner material 623 can be formed with the help of a catalyst. The catalyst can be a single crystal metal or a polycrystalline metal, a binary alloy, or a liquid metal. The single crystal metal or the polycrystalline metal can be, for example, nickel, copper, cobalt, platinum, silver, ruthenium, iridium, or palladium. The binary alloy can be, for example, an alloy of iron and nickel, an alloy of copper and nickel, an alloy of nickel and molybdenum, an alloy of gold and nickel, and an alloy of cobalt and copper. The liquid metal can be, for example, liquid gallium, liquid indium, or liquid copper.

[0143] In some embodiments, a catalytic conductive layer (not shown for clarity) may be conformally formed on a layer of first liner material 621 and on intermediate conductive layer 223. A layer of second liner material 623 may be formed on the catalytic conductive layer. The catalytic conductive layer may include nickel, copper, cobalt, platinum, silver, ruthenium, iridium, palladium, iron-nickel alloy, copper-nickel alloy, nickel-molybdenum alloy, gold-nickel alloy, and cobalt alloy and copper.

[0144] Reference Fig.17, a layer of a third conductive material 615 may be formed on the layer of the second liner material 623 and completely fill the word line trench 703. A planarization process, such as chemical mechanical polishing, is performed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the third conductive material 615 may be, for example, molybdenum or other suitable conductive materials.

[0145] In some embodiments, the third conductive material 615 can be formed by a chemical vapor deposition process. Fig.16 The intermediate semiconductor element shown can be exposed to a molybdenum precursor and a reactant. In some embodiments, the reactant can flow continuously, and the flow of the molybdenum precursor to the processing chamber can be turned on and off.

[0146] In some embodiments, the molybdenum precursor may include a molybdenum halide. In some embodiments, the molybdenum halide may include molybdenum fluoride, molybdenum chloride, or a combination thereof. In some embodiments, the molybdenum precursor may be passed through a carrier gas. Fig.16 The intermediate semiconductor element shown. In some embodiments, a carrier gas can flow through an ampoule including a molybdenum precursor. In some embodiments, the carrier gas can be an inert gas. In some embodiments, the inert gas can include one or more of nitrogen (N2), argon (Ar), and helium (He).

[0147] In some embodiments, the flow rate of the molybdenum precursor can be in the range of from 100 standard liters per minute (slm) to 1000slm, from 100slm to 700slm, from 100slm to 400slm, from 400slm to 1000slm, from 400slm to 700slm, or from 700slm to 1000slm. In some embodiments, the duration of the molybdenum precursor can be in the range of 0.3 seconds to 5 seconds, 0.3 seconds to 3 seconds, 0.3 seconds to 1 second, 1 second to 5 seconds, 1 second to 3 seconds, or 3 seconds to 5 seconds.

[0148] In some embodiments, Fig.16 The intermediate semiconductor element shown in can be exposed to a continuous flow or multiple pulses of a molybdenum precursor. In some embodiments, the multiple pulses of the molybdenum precursor can have a waiting time in the range of from 0.3 seconds to 30 seconds, 0.3 seconds to 10 seconds, 0.3 seconds to 5 seconds, 0.3 seconds to 1 second, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds.

[0149] In some embodiments, each pulse of the molybdenum precursor may be applied for a duration ranging from 0.3 seconds to 5 seconds, from 0.3 seconds to 3 seconds, from 0.3 seconds to 1 second, from 1 second to 5 seconds, from 1 second to 3 seconds, or from 3 seconds to 5 seconds. In some embodiments, at least one of the multiple pulses of the molybdenum precursor may be applied for a duration ranging from 0.3 seconds to 5 seconds, 0.3 seconds to 3 seconds, 0.3 seconds to 1 second, 1 second to 5 seconds, 1 second to 3 seconds, or 3 seconds to 5 seconds.

[0150] In some embodiments, the reactants may include an oxidant, a reductant, or a combination thereof. In some embodiments, the reactants may include hydrogen, ammonia, silane, polysilane, or a combination thereof. In some embodiments, the silane may be selected from one or more of disilane, trisilane, tetrasilane, higher order silane, and substituted silane. In some embodiments, the first reactant may be passed through a carrier gas. Fig.16 The intermediate semiconductor element shown. In some embodiments, the carrier gas can be an inert gas. In some embodiments, the inert gas can include one or more of N2, Ar and He.

[0151] In some embodiments, the flow rate of the reactant can be in the range of from 0.5slm to 15slm, from 0.5slm to 10slm, from 0.5slm to 5slm, from 5slm to 15slm, from 5slm to 10slm, or from 10slm to 15slm. In some embodiments, the duration of the reactant can be from 0.5 seconds to 10 seconds, from 0.5 seconds to 5 seconds, from 0.5 seconds to 1 second, from 1 second to 10 seconds, from 1 second to 5 seconds, or from 5 seconds to 10 seconds.

[0152] In some embodiments, Fig.16 The intermediate semiconductor element shown can be exposed to a continuous flow or multiple pulses of reactants. In some embodiments, multiple pulses of reactants can have a waiting time in the range of from 0.3 seconds to 30 seconds, from 0.3 seconds to 10 seconds, from 0.3 seconds to 5 seconds, from 0.3 seconds to 1 second, from 0.5 seconds to 5 seconds, from 1 second to 30 seconds, from 1 second to 10 seconds, from 1 second to 5 seconds, from 5 seconds to 30 seconds, from 5 seconds to 10 seconds, or from 10 seconds to 30 seconds.

[0153] In some embodiments, each pulse of reactant can be applied to a duration in the range of from 0.5 second to 10 seconds, from 0.5 second to 5 seconds, from 0.5 second to 1 second, from 1 second to 10 seconds, from 1 second to 5 seconds, or from 5 seconds to 10 seconds. In some embodiments, at least one of a plurality of pulses of reactant can be applied to a duration in the range of from 0.5 second to 10 seconds, from 0.5 second to 5 seconds, from 0.5 second to 1 second, from 1 second to 10 seconds, from 1 second to 5 seconds, or from 5 seconds to 10 seconds.

[0154] In some embodiments, the layer of the third conductive material 615 can be formed at a pressure in a range from 2 Torr to 60 Torr, from 2 Torr to 40 Torr, from 2 Torr to 20 Torr, from 20 Torr to 60 Torr, from 20 Torr to 40 Torr, or from 40 Torr to 60 Torr. In some embodiments, the layer of the third conductive material 615 can be formed at a temperature in a range from 350° C. to 550° C., from 350° C. to 500° C., from 350° C. to 450° C., from 350° C. to 400° C., from 400° C. to 550° C., from 400° C. to 500° C., from 400° C. to 450° C., from 450° C. to 550° C., from 450° C. to 500° C., or from 500° C. to 550° C.

[0155] In some embodiments, an annealing process may be performed after forming the layer of the third conductive material 615. In some embodiments, the temperature of the annealing process may be performed at a temperature higher than the temperature at which the layer of the third conductive material 615 is formed. In some embodiments, the annealing process may be performed at a temperature ranging from 100° C. to 550° C., from 100° C. to 450° C., from 100° C. to 350° C., from 100° C. to 250° C., from 200° C. to 550° C., from 200° C. to 450° C., from 200° C. to 350° C., from 300° C. to 550° C., from 300° C. to 450° C., or from 400° C. to 550° C.

[0156] In some embodiments, the environment of the annealing process may include one or more inert gases (eg, molecular nitrogen, argon) or reducing gases (eg, molecular hydrogen or ammonia).

[0157] In some embodiments, the duration of the annealing process may be in the range of 1 hour to 24 hours, 1 hour to 20 hours, 1 hour to 15 hours, 1 hour to 10 hours, 1 hour to 5 hours, 5 hours to 24 hours, 5 hours to 20 hours, 5 hours to 15 hours, 5 hours to 10 hours, 10 hours to 24 hours, 10 hours to 20 hours, 10 hours to 15 hours, 15 hours to 24 hours, 15 hours to 20 hours, or 20 hours to 24 hours. The annealing process may increase the density of the layer of the third conductive material 615, reduce the resistivity, and / or increase the purity.

[0158] Reference Fig.18 , a third etch-back process is performed to remove a portion of the third conductive material 615. In some embodiments, in the third etch-back process, an etch rate ratio of the third conductive material 615 to the second liner material 623 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0159] After the third etch-back process, the remaining second liner material 623 in the plurality of word line trenches 703 may be regarded as a plurality of top conductive layers 225 .

[0160] Reference Fig.19 , a removal process is performed to remove a portion of the second liner material 623, the first liner material 621, and the first dielectric material 601. In some embodiments, the removal process can be a multi-stage etching process. For example, the removal process can be a two-stage anisotropic dry etching process. The etching chemistry of each stage can be different to provide different etching selectivities.

[0161] In some embodiments, during the first stage of the removal process, the etch rate ratio of the second liner material 623 (and the first liner material 621) to the first dielectric material 601 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the first stage of the removal process, the etch rate ratio of the second liner material 623 (and the first liner material 621) to the top conductive layer 225 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0162] In some embodiments, during the second stage of the removal process, the etch rate ratio of the first dielectric material 601 to the pad nitride 105 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the second stage of the removal process, the etch rate ratio of the first dielectric material 601 to the plurality of top conductive layers 225 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0163] Reference Fig.19 , after the removal process, the second liner material 623 remaining in the word line trench 703 can be regarded as a plurality of top liner layers 233. The top liner layer 233 can have a U-shaped cross-sectional profile. The first liner material 621 remaining in the word line trench 703 can be regarded as a plurality of bottom liner layers 231. The bottom liner layer 231 can have a U-shaped cross-sectional profile. The first dielectric material 601 remaining in the word line trench 703 can be regarded as a plurality of word line dielectric layers 211. The word line dielectric layer 211 can have a U-shaped cross-sectional profile.

[0164] In some embodiments, the top surface 211TS of the word line dielectric layer 211 , the top surface 231TS of the bottom liner layer 231 , the top surface 233TS of the top liner layer 233 , and the top conductive layer 225 may be substantially coplanar.

[0165] Reference Fig. 20 , forming a layer of covering material 603 to completely fill word line trench 703. In some embodiments, covering material 603 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or other applicable insulating materials. In some embodiments, covering material 603 may be, for example, germanium oxide. In some embodiments, the layer of covering material 603 may be formed by, for example, chemical vapor deposition, atomic layer deposition, or other applicable deposition processes.

[0166] For example, when forming the layer of capping material 603 by atomic layer deposition, the atomic layer deposition process may include using a vapor phase germanium precursor and an oxygen-containing reactant (also referred to as an oxygen source) in alternating and sequential contact with each other. Fig.19 The intermediate semiconductor element is shown such that a layer of germanium precursor is formed on the surface of the intermediate semiconductor element, and the oxygen-containing reactant subsequently forms a layer of capping material 603 with the germanium precursor.

[0167] In detail, the germanium precursor may be directed to a Fig.19 The process chamber of the intermediate semiconductor element shown in the figure contacts the surface of the intermediate semiconductor element in the form of a gas phase pulse. Excess germanium precursor and reaction byproducts (if any) can be removed from the intermediate semiconductor element and the surface of the intermediate semiconductor element and from the surface close to the intermediate semiconductor element and the intermediate semiconductor element.

[0168] In some embodiments, excess germanium precursor and reaction byproducts (if any) can be removed by purging. Purging can be accomplished, for example, with pulses of an inert gas such as nitrogen or argon. Purging a process chamber refers to removing gaseous precursors and / or gaseous byproducts from a process chamber, for example by evacuating the process chamber with a vacuum pump and / or by replacing the gas or nitrogen inside the process chamber with an inert gas such as argon. In some embodiments, the purge time can be between about 0.05 seconds and about 20 seconds, between about 1 second and about 10 seconds, or between about 1 second and about 20 seconds.

[0169] A gaseous oxygen source may be pulsed into the process chamber where it reacts with the germanium precursor on the surface of the intermediate semiconductor element to form a layer of capping material 603 formed of germanium oxide. Excess oxygen source and gaseous byproducts of the surface reaction may be removed from the intermediate semiconductor element, for example by purging them out of the process chamber with the aid of an inert gas.

[0170] The steps of pulsing and removing may be repeated until a desired thickness is formed on the intermediate semiconductor element.

[0171] In some embodiments, the germanium precursor is not a halide. In some embodiments, the germanium precursor may include a halogen in at least one ligand, but not in all ligands. In some embodiments, the germanium precursor may include germanium ethoxide or tetrakis(dimethylamino)germanium.

[0172] In some embodiments, the oxygen source may be water, ozone, oxygen plasma, oxygen radicals, or oxygen atoms. In some embodiments, the oxygen source is not water. In some embodiments, the germanium precursor used in the process may be a solid, liquid, or gaseous material under standard conditions (room temperature and atmospheric pressure), provided that the germanium precursor is in the gas phase prior to being introduced into the process chamber and contacting the intermediate semiconductor element.

[0173] It should be noted that in the present disclosure, "pulsing" a vaporized precursor onto a component means that the precursor vapor is directed into the processing chamber for a specified period of time. In some embodiments, the germanium precursor may be pulsed between about 0.05 seconds to about 10 seconds, about 0.1 seconds to about 5 seconds, or about 0.3 seconds to about 3.0 seconds. In some embodiments, the oxygen source may be pulsed between about 0.05 seconds to about 10 seconds, about 0.1 seconds to about 5 seconds, or about 0.2 seconds to about 3.0 seconds.

[0174] In some embodiments, the oxygen source may be a pulse of oxygen-containing gas, and may be a mixture of oxygen and an inert gas such as nitrogen or argon. In some embodiments, the oxygen source may be a pulse of molecular oxygen-containing gas. The oxygen content of the oxygen source gas may be between about 10% and about 25%. Thus, one of the oxygen sources may be air.

[0175] In some embodiments, the oxygen source can be molecular oxygen. In some embodiments, the oxygen source can include activated or excited oxygen species. In some embodiments, the oxygen source can include ozone. In some embodiments, the oxygen source can be pure ozone or a mixture of ozone, molecular oxygen and another gas, such as an inert gas such as nitrogen or argon.

[0176] Ozone can be produced by an ozone generator and can be introduced into the processing chamber with the help of an inert gas such as nitrogen or oxygen. In some embodiments, ozone can be between about 5 volume percent concentration (vol-%) and about 40vol-%, or a concentration between about 15vol-% and about 25vol-%. In some embodiments, the oxygen source can be an oxygen plasma. In some embodiments, ozone or a mixture of ozone and another gas can be pulsed into the processing chamber. In some embodiments, ozone can be formed in the processing chamber, for example, by directing an oxygen-containing gas through an arc. In some embodiments, an oxygen-containing plasma can be formed in the processing chamber. In some embodiments, a plasma can be formed upstream of the processing chamber in a remote plasma generator, and the plasma product can be directed to the processing chamber to contact the intermediate semiconductor element.

[0177] In some embodiments, the oxygen source may be an oxygen source other than water. Thus, in those embodiments no water is provided.

[0178] In some embodiments, the temperature at which the layer of capping material 603 is formed may be between about 20°C and about 600°C, between about 100°C and about 400°C, or between about 150°C and about 300°C.

[0179] In some embodiments, the layer of capping material 603 is a pure germanium oxide layer. That is, except for a small amount of impurities, no other metal or semi-metal elements are present in the layer of capping material 603. In some embodiments, the layer of capping material 603 may include less than 1 atomic percent (at%) of metal or semi-metal other than germanium. In some embodiments, the layer of capping material 603 may include less than about 5 at% of any impurity other than hydrogen, less than about 3 at% of any impurity other than hydrogen, or less than about 1 at% of any impurity other than hydrogen.

[0180] Reference Fig.21 and Fig. 22 , a planarization process is performed until the top surface of the pad nitride 105 is exposed. After the planarization process, the remaining capping material 603 can be regarded as the word line capping layer 213. In some embodiments, the planarization process can be an etching process, a chemical mechanical polishing process, or a combination thereof. At the current stage, the top surface of the pad nitride 105 and the top surface of the word line capping layer 213 can be substantially coplanar.

[0181] Reference Fig.21 and Fig. 22 The word line dielectric layer 211 , the word line cap layer 213 , the bottom conductive layer 221 , the middle conductive layer 223 , the top conductive layer 225 , the bottom pad layer 231 and the top pad layer 233 together constitute the word line structure 200 .

[0182] In some embodiments, the bottom liner layer 231 and the middle conductive layer 223 can be configured to cooperate with the bottom conductive layer 221 to adjust the work function to obtain a word line structure 200 with low resistance. Therefore, the performance of the word line structure 200 will be improved.

[0183] By using the word line cap layer 213 formed of germanium oxide, leakage of the word line structure 200 can be prevented and the trap density can be reduced. Therefore, the performance of the semiconductor device 1A can be improved.

[0184] In some embodiments, the word line structure 200 may have a work function greater than or equal to 4.3 eV. In some embodiments, the word line structure 200 may have a work function greater than or equal to 4.5 eV. In some embodiments, the word line structure 200 may have a work function greater than or equal to 4.3 eV, including greater than or equal to 4.4 eV, greater than or equal to 4.5 eV, greater than or equal to 4.6 eV, greater than or equal to 4.7 eV, greater than or equal to 4.8 eV, greater than or equal to 4.9 eV, greater than or equal to 5.0 eV, greater than or equal to 5.1 eV, or greater than or equal to 5.2 eV.

[0185] In some embodiments, the word line structure 200 has a total thickness of In some embodiments, the word line structure 200 may have a resistance less than or equal to 40 μΩ-cm, less than or equal to 30 μΩ-cm, less than or equal to 25 μΩ-cm, less than or equal to 20 μΩ-cm, or less than or equal to 15 μΩ-cm. In some embodiments, the word line structure 200 has a total thickness of less than or equal to 20 μΩ-cm. Under the present invention, it can have a resistance in the range of from 50 μΩ-cm to 5 μΩ-cm, from 40 μΩ-cm to 10 μΩ-cm, from 30 μΩ-cm to 10 μΩ-cm, from 25 μΩ-cm to 10 μΩ-cm, and from 20 μΩ-cm to 10 μΩ-cm.

[0186] Fig.23 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure; Fig.24 and Fig.25 is a cross-sectional view, showing Fig.23 The cross-sectional structures taken along the lines AA′ and BB′ represent a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Fig.26 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig. 27 and Fig.28 is a cross-sectional view, showing Fig.26 The cross-sectional structures taken along the lines AA′ and BB′ represent a partial process of manufacturing the semiconductor device 1A according to an embodiment of the present disclosure. Fig.29 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.30 and Fig.31 is a cross-sectional view, showing Fig.29 The cross-sectional structures taken along the lines AA′ and BB′ represent a partial process of manufacturing the semiconductor device 1A according to an embodiment of the present disclosure.

[0187] Reference Figure 1 and Figure 23 to Figure 27In step S15 , a plurality of openings 705 are formed in the first region R1 , and a plurality of in-groove spacers 301 are formed in the openings 705 .

[0188] Reference Fig.23 and Fig.24 , the opening 705 may be formed by a lithography process and a subsequent etching process. The bottom surface 705BS of the opening 705 may be located at a vertical level VL1 between the bottom surface 213BS of the word line cover layer 213 and the top surface 101TS of the substrate 101. In some embodiments, the opening 705 may have a square cross-sectional profile in a top view, but is not limited to this shape. In some embodiments, the opening 705 may have a rectangular, circular, or other suitable cross-sectional profile in a top view.

[0189] Reference Fig.25 , a layer of spacer material 605 is conformally formed on the pad nitride 105, the isolation layer 107 and the opening 705. In some embodiments, the layer of spacer material 605 can be formed by, for example, atomic layer deposition, chemical vapor deposition or other applicable deposition processes. In some embodiments, the spacer material 605 can be a material having etching selectivity to the word line cap layer 213. In some embodiments, the spacer material 605 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, boron nitride phosphorus, boron nitride carbon silicon or other applicable insulating materials.

[0190] Reference Fig.26 and Fig. 27 , a spacer etching process is performed to remove a portion of the spacer material 605. The remaining spacer material 605 can be regarded as the inner spacer 301 of the groove. In some embodiments, the spacer etching process can be an anisotropic etching process such as reactive ion etching.

[0191] In some embodiments, the groove inner spacer 301 may have a square ring cross-sectional profile in a top view, but is not limited to this shape. In some embodiments, the groove inner spacer 301 may have a rectangular ring, ring or other suitable cross-sectional profile in a top view.

[0192] In some embodiments, the bottom surface 301BS of the inner groove spacer 301 may be at a vertical level VL1 between the bottom surface 213BS of the word line cover layer 213 and the top surface 101TS of the substrate 101. In some embodiments, the top of the inner groove spacer 301 may be lower than the top surface 101TS of the substrate 101. In some embodiments, the portion of the inner groove spacer 301 extending along the direction X (top view) may be attached to the word line cover layer 213 (cross-sectional view). The portion of the inner groove spacer 301 extending along the direction Y (top view) may be attached to the substrate 101 (cross-sectional view).

[0193] Reference Figure 1 and Figure 28 to Figure 31 , in step S17 , a plurality of buried conductive layers 401 are formed in the openings 705 .

[0194] Reference Fig.28 , a layer of the fourth conductive material 617 is formed to cover the inner spacer 301 of the groove and completely fill the opening 705. In some embodiments, the layer of the fourth conductive material 617 can be formed by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, sputtering, electroplating, chemical plating or other applicable deposition processes. In some embodiments, the fourth conductive material 617 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide or a combination thereof.

[0195] Reference Fig.29 and Fig.30 , a planarization process is performed until the word line cap layer 213 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. The remaining fourth conductive material 617 can be regarded as a buried conductive layer 401. At this stage, the top surface 213TS of the word line cap layer 213 and the top surface of the buried conductive layer 401, as well as the top surface of the pad nitride 105 can be substantially coplanar. In some embodiments, the planarization process can be an etching process, a chemical mechanical polishing process, or a combination thereof.

[0196] Reference Fig.31 , a planarization process such as chemical mechanical polishing is performed until the top surface 101TS of the substrate 101 is exposed to remove the pad oxide 103 and the pad nitride 105. At this stage, the top surface of the buried conductive layer 401, the top surface 213TS of the word line cap layer 213 and the top surface 101TS of the substrate 101 are substantially coplanar.

[0197] The buried conductive layer 401 may include a bottom portion 411 and a top portion 413. The bottom portion 411 may be disposed in the opening 705. A bottom surface 411BS of the bottom portion 411 may contact the substrate 101. The bottom surface 411BS of the bottom portion 411 (i.e., the bottom surface of the buried conductive layer 401) and the bottom surface 301BS of the recessed inner spacer 301 may be substantially coplanar. The sidewall 411SW of the bottom portion 411 is surrounded by the recessed inner spacer 301. The bottom surface 411BS of the bottom portion 411 may be located at a vertical level VL1 higher than the bottom surface 213BS of the word line cover layer 213. Alternatively, in some embodiments, the bottom surface 411BS of the bottom portion 411 and the bottom surface 301BS of the recessed inner spacer 301 may be located at a vertical level (not shown) lower than the bottom surface 213BS of the word line cover layer 213.

[0198] The top portion 413 may be disposed on the bottom portion 411 and cover the top of the inner groove spacer 301. The top surface 413TS of the top portion 413 (i.e., the top surface of the buried conductive layer 401), the top surface 213TS of the word line cover layer 213, and the top surface 101TS of the substrate 101 are substantially coplanar. The sidewall 413SW of the top portion 413 and the sidewall 301SW of the inner groove spacer 301 may be substantially coplanar.

[0199] In some embodiments, a width ratio of a width W1 of a bottom surface 411BS of the bottom portion 411 to a width W2 of a top surface 413TS of the top portion 413 may be between about 0.5 and about 0.95. In some embodiments, a ratio of a thickness T1 of the in-groove spacer 301 to a width W2 of a top surface 413TS of the top portion 413 may be between about 0.025 and about 0.25. In some embodiments, a height ratio of a height H1 of the in-groove spacer 301 to a height H2 of the buried conductive layer 401 may be between about 0.5 and about 0.85.

[0200] The electric field near the buried conductive layer 401 can be reduced by using the inner spacer 301 of the groove. Therefore, the gate-induced-drain-leakage (GIDL) will be reduced due to the reduction of the electric field. Accordingly, the performance of the semiconductor device 1A will be improved.

[0201] Fig.32 FIG. 4 is a top view illustrating an intermediate semiconductor element in another embodiment of the present disclosure. Fig.33 is a cross-sectional view, showing Fig.32 The cross-sectional structure taken along the A-A' and B-B' lines.

[0202] Reference Fig.32 and Fig.33 , the semiconductor element 1B may have Fig.31 The structure shown is similar to the structure. Fig.32 and Fig.33 Zhongyu Fig.31 The same or similar elements are marked with like reference numerals, and repeated description is omitted.

[0203] Reference Fig.32 and Fig.33 The semiconductor element 1B may include a plurality of source electrodes SR and a plurality of drain electrodes DR. The source electrodes SR may be respectively and correspondingly disposed in the first region R1. The drain electrodes DR may be respectively and correspondingly disposed in the second region R2. The recessed inner spacers 301 and the plurality of buried conductive layers 401 may be respectively and correspondingly disposed in the source electrodes SR.

[0204] The source SR and the drain DR may be formed by an implantation process. The implantation process may employ, for example, an n-type dopant. An n-type dopant may be added to an intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. In a silicon-containing substrate, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the doping concentration of the source SR and the drain DR may be between about 1E19 atoms / cm^3 and about 1E21 atoms / cm^3; other dopant concentrations less than or greater than the above ranges may also be used in the present application.

[0205] In some embodiments, an annealing process is performed to activate the source SR and the drain DR. The annealing process may have a process temperature between about 800° C. and about 1250° C. The annealing process may have a process duration between about 1 millisecond and about 500 milliseconds. The annealing process may be, for example, rapid thermal annealing, laser spike annealing, or flash lamp annealing.

[0206] One aspect of the present disclosure provides a semiconductor device, including a substrate; a plurality of word line structures disposed in the substrate; a buried conductive layer, including: a bottom portion disposed in the substrate and between the word line structures; and a top portion disposed in the substrate, on the bottom portion and between the word line structures; and a recessed inner spacer disposed in the substrate and between the word line structures, surrounding the bottom portion and covered by the top portion. A top surface of the top portion, a top surface of the substrate and the top surfaces of the word line structures are substantially coplanar. A bottom surface of the recessed inner spacer is substantially coplanar with a bottom surface of the bottom portion. A side wall of the recessed inner spacer is substantially coplanar with a side wall of the top portion.

[0207] Due to the design of the semiconductor device disclosed in the present invention, the spacer 301 in the groove can be used to reduce the electric field near the buried conductive layer 401. Therefore, due to the reduction of the electric field, the drain leakage caused by the gate can be reduced. In this way, the performance of the semiconductor device 1A will be improved.

[0208] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0209] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a base; A plurality of word line structures are disposed in the substrate; A buried conductive layer comprising: a bottom portion disposed in the substrate and between the word line structures; and a top portion disposed in the substrate, on the bottom portion, and between the plurality of word line structures; and A groove inner spacer is disposed in the substrate and between the plurality of word line structures, surrounds the bottom, and is covered by the top. wherein a top surface of the top portion, a top surface of the base, and top surfaces of the plurality of word line structures are substantially coplanar, wherein a bottom surface of the inner spacer of the groove and a bottom surface of the bottom are substantially coplanar, A side wall of the inner spacer of the groove is substantially coplanar with a side wall of the top.

2. The semiconductor device as claimed in claim 1, wherein the plurality of word line structures respectively comprise: a word line dielectric layer disposed in the substrate and having a U-shaped cross-sectional profile; a bottom conductive layer in the substrate and on the word line dielectric layer; and a word line capping layer located in the substrate and on the word line dielectric layer and the bottom conductive layer, The vertical level of a bottom surface of the word line covering layer is lower than that of the bottom conductive layer.

3. The semiconductor device as claimed in claim 2, wherein each of the plurality of word line structures further comprises: An intermediate conductive layer is located between the bottom conductive layer and the word line covering layer.

4. The semiconductor device as claimed in claim 3, wherein each of the plurality of word line structures further comprises: A bottom liner layer is located between the middle conductive layer and the bottom conductive layer, and between the middle conductive layer and the word line covering layer.

5. The semiconductor device as claimed in claim 4, wherein each of the plurality of word line structures further comprises: A top conductive layer is located between the middle conductive layer and the word line covering layer.

6. The semiconductor device as claimed in claim 5, wherein each of the plurality of word line structures further comprises: A top liner layer is located between the middle conductive layer and the top conductive layer, and between the top conductive layer and the word line dielectric layer.

7. The semiconductor device as claimed in claim 6, wherein the bottom liner layer and the top liner layer include sp 2 A material made of mixed carbon atoms. 8 . The semiconductor device as claimed in claim 7 , wherein the word line capping layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide or germanium oxide. 9 . The semiconductor device of claim 8 , wherein the word line dielectric layer comprises a high-k material. 10 . The semiconductor device as claimed in claim 9 , wherein the bottom conductive layer comprises titanium, titanium nitride, silicon, silicon germanium or a combination thereof. 11 . The semiconductor device as claimed in claim 10 , wherein the middle conductive layer comprises tungsten, tungsten nitride or a combination thereof.

12. The semiconductor device of claim 11, wherein the top conductive layer comprises molybdenum. 13 . The semiconductor device of claim 12 , wherein a width ratio of a bottom surface width of the bottom portion to a top surface width of the top portion is between about 0.5 and about 0.

95. 14 . The semiconductor device of claim 12 , wherein a ratio of a thickness of the spacer in the groove to a width of a top surface of the top portion is between about 0.025 and about 0.

25. 15 . The semiconductor device of claim 12 , wherein a height ratio of a height of the spacer in the groove to a height of the buried conductive layer is between about 0.5 and about 0.

85. 16 . The semiconductor device as claimed in claim 12 , wherein the inner spacer of the groove comprises a square ring-shaped cross-sectional profile in a top view. 17 . The semiconductor device as claimed in claim 12 , wherein the buried conductive layer comprises a square cross-sectional profile in a top view. 18 . The semiconductor device as claimed in claim 12 , wherein the bottom liner layer and the top liner layer comprise the same material.

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