Ideal diode circuit and implementation method thereof

Abstract

The invention relates to the technical field of circuits, in particular to an ideal diode circuit and an implementation method thereof, and the circuit comprises m input connectors, m gating circuits and an output power connector, the first input power supply ends of the m gating circuits are jointly connected with a high-level input end, m diodes are connected between the m input connectors and the high-level input end in a one-to-one correspondence mode, the negative electrodes of the m diodes are further jointly connected with one end of a load resistor, and the other end of the load resistor is grounded; the ith input connector is connected with the second input power supply end of the ith gating circuit; the input connector is used for switching on input power; the gating circuit is used for comparing the voltage values of the input power supplies connected with the m input connectors and conducting a path between the input connector connected with the input power supply with the maximum voltage value and the output power supply end, so that the output power supply connector is used for connecting the input power supply with the highest voltage value; according to the invention, priority gating of multiple paths of power supplies can be realized.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an ideal diode circuit and a realization method thereof. Background Art

[0002] In existing circuit designs, the priority selection of multiple input power sources is usually achieved using components such as diodes or relays. However, these traditional methods have some shortcomings. For example, the forward voltage drop of the diode is large, which leads to severe heating when a large current passes through it, and the relay has problems such as slow response speed and short life. Therefore, a new ideal diode circuit is needed to solve these problems. Summary of the invention

[0003] To solve the above problems, the present invention provides an ideal diode circuit and an implementation method thereof, aiming to provide a circuit that can effectively implement multi-channel input voltage priority selection to ensure that the input power supply with the highest voltage is selected for output among multiple input power supplies, thereby improving the stability and reliability of the power supply system.

[0004] In order to achieve the above object, the present invention provides the following technical solutions: In one aspect, the present invention provides an ideal diode circuit, comprising: m input connectors, m gating circuits and an output power connector; The gating circuit includes a first input power terminal, a second input power terminal and an output power terminal; The first input power supply terminals of the m gating circuits are commonly connected to the high-level input terminal, and m diodes are connected one-to-one between the m input connectors and the high-level input terminal, the input connectors are connected to the positive electrodes of the diodes, and the negative electrodes of the diodes are connected to the high-level input terminal; the negative electrodes of the m diodes are also commonly connected to one end of a load resistor, and the other end of the load resistor is grounded; The i-th input connector is connected to the second input power supply terminal of the i-th selection circuit; wherein 1≤i≤m, m is an integer greater than 1; The input connector is used to connect the input power supply; the selection circuit is used to compare the voltage values ​​of the input power supplies connected to the m input connectors, and to connect the path between the input connector connected to the input power supply with the largest voltage value and the output power supply end, so that the output power supply connector is used to connect the input power supply with the highest voltage value.

[0005] Furthermore, the gating circuit further comprises: a first resistor, a second resistor, a first triode, a second triode, a first MOS transistor and a second MOS transistor; The base of the first transistor is connected to the first input power supply terminal. The emitter of the first transistor, one end of the first resistor and the source of the first MOS transistor are commonly connected to the second input power supply end, the collector of the first transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the base of the second transistor; The other end of the first resistor, the gate of the first MOS transistor and the gate of the second MOS transistor are commonly connected to the collector of the second triode, and the emitter of the second triode is grounded; The drain of the first MOS tube is connected to the drain of the second MOS tube, and the source of the second MOS tube is connected to the output power supply end.

[0006] Furthermore, the gating circuit further includes a third resistor, the base of the first transistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the first input power supply end.

[0007] Furthermore, the first transistor is a PNP transistor.

[0008] Furthermore, the second transistor is an NPN transistor.

[0009] Furthermore, the first MOS tube is a PMOS tube.

[0010] Furthermore, the second MOS tube is a PMOS tube.

[0011] Furthermore, the diode is a rectifier diode or a fast diode.

[0012] Furthermore, the resistance of the load resistor is 5.1K ohms, and when current passes through the diode, the diode generates a voltage drop.

[0013] On the other hand, the present invention further provides a method for realizing an ideal diode circuit, which is applied to any of the above-mentioned ideal diode circuits, and the method comprises the following steps: When m of the input connectors are connected to input power, the selection circuit compares the voltage values ​​of the input power sources connected to the m input connectors, and switches on the path between the input connector connected to the input power source with the largest voltage value and the output power source end, so that the output power connector is used to connect to the input power source with the highest voltage value.

[0014] The beneficial effects of the present invention are as follows: the present invention provides an ideal diode circuit and an implementation method thereof, and the present invention utilizes the characteristic that the voltage drop of the diode is greater than the voltage difference between the base and the emitter of the triode to realize the function of high-voltage gating. It can effectively realize the priority selection of multiple input voltages, ensure that the input power supply with the highest voltage is selected for output among the multiple input power supplies, thereby improving the stability and reliability of the power supply system. At the same time, since the ideal diode circuit of the present invention has a small voltage drop, it generates less heat when a large current passes through, and is suitable for high-power occasions. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 is a circuit schematic diagram of an ideal diode circuit in an embodiment of the present invention; Figure 2 is a circuit schematic diagram of a gating circuit in an embodiment of the present invention; Figure 3 It is an overall schematic diagram of an ideal diode circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0018] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0019] In the description of the present invention, if there are words such as "several", it means one or more, "more" means more than two, greater than, less than, exceed, etc. are understood as not including the number, and above, below, within, etc. are understood as including the number.

[0020] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0021] refer to Figure 1 and Figure 2 , an embodiment of the present invention provides an ideal diode circuit, comprising: m input connectors J, m gating circuits 100 and an output power connector Jout; The gating circuit 100 includes a first input power terminal VCC1_IN, a second input power terminal VCC2_IN and an output power terminal VCC_OUT; The first input power supply terminals VCC1_IN of the m gating circuits 100 are commonly connected to the high level input terminal VCC_HIGH, and m diodes D are connected one by one between the m input connectors J and the high level input terminal VCC_HIGH, the input connectors J are connected to the anode of the diode D, and the cathode of the diode D is connected to the high level input terminal VCC_HIGH; the cathodes of the m diodes D are also commonly connected to one end of a load resistor, and the other end of the load resistor is grounded; The i-th input connector J is connected to the second input power supply terminal VCC2_IN of the i-th gating circuit 100; wherein 1≤i≤m, and m is an integer greater than 1; The input connector J is used to connect the input power supply; the selection circuit 100 is used to compare the voltage values ​​of the input power supplies connected to the m input connectors J, and to connect the path between the input connector J connected to the input power supply with the largest voltage value and the output power supply terminal VCC_OUT, so that the output power connector Jout is used to connect the input power supply with the highest voltage value.

[0022] As a preferred embodiment of the above, the gating circuit 100 further includes: a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2, a first MOS transistor Q3 and a second MOS transistor Q4; The base of the first transistor Q1 is connected to the first input power supply terminal VCC1_IN. The emitter of the first transistor Q1, one end of the first resistor R1 and the source of the first MOS transistor Q3 are commonly connected to the second input power supply terminal VCC2_IN, the collector of the first transistor Q1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the base of the second transistor Q2; The other end of the first resistor R1, the gate of the first MOS transistor Q3 and the gate of the second MOS transistor Q4 are commonly connected to the collector of the second triode Q2, and the emitter of the second triode Q2 is grounded; The drain of the first MOS transistor Q3 is connected to the drain of the second MOS transistor Q4 , and the source of the second MOS transistor Q4 is connected to the output power supply terminal VCC_OUT.

[0023] As a preferred embodiment of the above embodiment, the gating circuit 100 further includes a third resistor R3, the base of the first transistor Q1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the first input power terminal VCC1_IN.

[0024] As a preference of the above embodiment, the first transistor Q1 is a PNP transistor.

[0025] As a preference of the above embodiment, the second transistor Q2 is an NPN transistor.

[0026] As a preference of the above embodiment, the first MOS tube Q3 is a PMOS tube.

[0027] As a preference of the above embodiment, the second MOS tube Q4 is a PMOS tube.

[0028] As a preference of the above embodiment, the diode D is a rectifier diode or a fast diode.

[0029] As a preference for the above embodiment, the resistance of the load resistor is 5.1K ohms, and when current passes through the diode D, the diode D generates a voltage drop.

[0030] The working principle of the present invention is as follows: refer to Figure 3 , m=4 is set. In one embodiment, the priority of the power supply is realized as follows: the input voltage VCC1 of the first input connector J1> the input voltage VCC2 of the second input connector J2> the input voltage VCC3 of the third input connector J3> the input voltage VCC4 of the fourth input connector J4. That is, when any one or more of the input voltages VCC1 of the first input connector J1, VCC2 of the second input connector J2, VCC3 of the third input connector J3, and VCC4 of the fourth input connector J4 are input simultaneously, the power supply output VCC_OUT is selected and outputted according to the priority of the input voltage VCC1 of the first input connector J1> the input voltage VCC2 of the second input connector J2> the input voltage VCC3 of the third input connector J3> the input voltage VCC4 of the fourth input connector J4.

[0031] The resistance of the load resistor is 5.1K ohms, which is a dummy load relative to the diode D. According to the parameters of the rectifier diode D of model 1N4007, when the diode D passes 1mA current, the voltage drop is 0.8V. Therefore, the role of the load resistor is to make the diode D produce a 0.8V voltage drop. That is, the voltage of the high-level input terminal VCC_HIGH is equal to the highest voltage among the four voltages VCC1, VCC2, VCC3, and VCC4 minus 0.8V.

[0032] Assuming that the input voltage VCC1 of the first input connector J1 is not the highest voltage, the first transistor Q1 in the first selection circuit 100 is turned off (the conduction voltage of the transistor is generally within 0.5V, and the conduction voltage of the rectifier diode D1N4007 drops 0.8V under the condition of 1mA current), and then the second transistor Q2 is turned off, and finally the first MOS transistor Q3 and the second MOS transistor Q4 are turned off, and the output voltage VCC_OUT is not equal to VCC1.

[0033] Assuming that the input voltage VCC1 of the first input connector J1 is the highest voltage, the first transistor Q1 in the first selection circuit 100 is turned on, and then the second transistor Q2 is turned on, and finally the first MOS transistor Q3 and the second MOS transistor Q4 are turned on, and the output voltage VCC_OUT is equal to VCC1.

[0034] As for the second input connector J2 , the third input connector J3 and the fourth input connector J4 , the principle is the same as that of the first input connector J1 , and finally only the highest input voltage among the four input voltages VCC1 , VCC2 , VCC3 , and VCC4 can be turned on.

[0035] If the two input voltages are the same, the two paths will be turned on at the same time, which is the same as the case of an ordinary diode D, that is, the two input voltages are equal and equal to the output voltage VCC_OUT.

[0036] Regarding the choice of diode D: The present invention utilizes the characteristic that the voltage drop of the diode D is greater than the voltage difference between the base and the emitter of the transistor to realize the function of high-voltage gating, that is, the voltage drop of the diode D must be greater than the conduction voltage of the transistor.

[0037] The present invention can select a rectifier diode (model 1N4007) or a fast diode (model 1N4148), the voltage drop of the rectifier diode is 0.8V> the voltage drop of the fast diode is 0.5V, and the embodiment selects a suitable diode D according to whether the deviation of the 4-way input voltage is large. If the deviation of the 4-way input voltage is greater than 0.5V, the rectifier diode D can be selected, and if the deviation of the 4-way input voltage is less than 0.5V, the fast diode D can be selected.

[0038] In addition, an embodiment of the present invention provides a method for implementing an ideal diode circuit, which is applied to the ideal diode circuit described in any of the above embodiments, and the method includes the following steps: When m of the input connectors are connected to input power, the selection circuit compares the voltage values ​​of the input power sources connected to the m input connectors, and switches on the path between the input connector connected to the input power source with the largest voltage value and the output power source end, so that the output power connector is used to connect to the input power source with the highest voltage value.

[0039] The embodiments described in the embodiments of the present invention are intended to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention. Those skilled in the art can appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present invention are also applicable to similar technical problems.

[0040] Those skilled in the art will appreciate that the technical solutions shown in the figures do not limit the embodiments of the present invention and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0041] The device embodiments described above are merely illustrative, and the circuits described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed over multiple network circuits. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0042] Those skilled in the art will appreciate that all or some of the steps in the method disclosed above, the main control chip, and the functional modules / circuits in the device may be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0043] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, main control chip, product or device that includes a series of steps or circuits is not necessarily limited to those steps or circuits clearly listed, but may include other steps or circuits that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] It should be understood that in the present invention, "at least one (item)" refers to one or more, and "plurality" refers to two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can represent: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0045] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above circuits is only a logical function division. There may be other division methods in actual implementation, such as multiple circuits or components can be combined or integrated into another main control chip, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or circuits, which can be electrical, mechanical or other forms.

[0046] The circuits described as separate components may or may not be physically separated, and the components shown as circuits may or may not be physical circuits, that is, they may be located in one place or distributed over multiple network circuits. Some or all of the circuits may be selected according to actual needs to achieve the purpose of the present embodiment.

[0047] In addition, each functional circuit in each embodiment of the present invention may be integrated into one processing circuit, or each circuit may exist physically separately, or two or more circuits may be integrated into one circuit. The above integrated circuit may be implemented in the form of hardware or in the form of software functional circuit.

[0048] The preferred embodiments of the embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of rights of the embodiments of the present invention is not limited thereby. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present invention should be within the scope of rights of the embodiments of the present invention. Although the description disclosed in the present invention has been quite detailed and several of the embodiments are described in particular, it is not intended to be limited to any of these details or embodiments or any particular embodiment, but should be regarded as providing a broad possible interpretation of these claims by reference to the attached claims, taking into account the prior art, so as to effectively cover the intended scope disclosed by the present invention. In addition, the above describes the present invention with the foreseeable embodiments of the inventor, the purpose of which is to provide a useful description, and those non-substantial changes to the present invention that have not yet been foreseen may still represent equivalent changes to the present disclosure.

Claims

1. An ideal diode circuit, characterized in that: include: m input connectors, m gating circuits and an output power connector; The gating circuit includes a first input power terminal, a second input power terminal and an output power terminal; The first input power supply terminals of the m gating circuits are commonly connected to the high-level input terminal, and m diodes are connected one-to-one between the m input connectors and the high-level input terminal, the input connectors are connected to the positive electrodes of the diodes, and the negative electrodes of the diodes are connected to the high-level input terminal; the negative electrodes of the m diodes are also commonly connected to one end of a load resistor, and the other end of the load resistor is grounded; The i-th input connector is connected to the second input power supply terminal of the i-th selection circuit; wherein 1≤i≤m, m is an integer greater than 1; The input connector is used to connect the input power supply; the selection circuit is used to compare the voltage values ​​of the input power supplies connected to the m input connectors, and to connect the path between the input connector connected to the input power supply with the largest voltage value and the output power supply end, so that the output power supply connector is used to connect the input power supply with the highest voltage value.

2. An ideal diode circuit according to claim 1, characterized in that: The gating circuit further includes: a first resistor, a second resistor, a first triode, a second triode, a first MOS transistor and a second MOS transistor; The base of the first transistor is connected to the first input power supply terminal. The emitter of the first transistor, one end of the first resistor and the source of the first MOS transistor are commonly connected to the second input power supply end, the collector of the first transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the base of the second transistor; The other end of the first resistor, the gate of the first MOS transistor and the gate of the second MOS transistor are commonly connected to the collector of the second triode, and the emitter of the second triode is grounded; The drain of the first MOS tube is connected to the drain of the second MOS tube, and the source of the second MOS tube is connected to the output power supply end.

3. An ideal diode circuit according to claim 2, characterized in that: The gating circuit further includes a third resistor, the base of the first transistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the first input power supply end.

4. An ideal diode circuit according to claim 2, characterized in that: The first transistor is a PNP transistor.

5. An ideal diode circuit according to claim 4, characterized in that: The second transistor is an NPN transistor.

6. An ideal diode circuit according to claim 2, characterized in that: The first MOS tube is a PMOS tube.

7. An ideal diode circuit according to claim 6, characterized in that: The second MOS tube is a PMOS tube.

8. An ideal diode circuit according to claim 1, characterized in that: The diode is a rectifier diode or a fast diode.

9. An ideal diode circuit according to claim 8, characterized in that: The resistance of the load resistor is 5.1K ohms. When current passes through the diode, the diode generates a voltage drop.

10. A method for realizing an ideal diode circuit, characterized in that: The ideal diode circuit according to any one of claims 1 to 9, characterized in that the method comprises the following steps: When m of the input connectors are connected to input power, the selection circuit compares the voltage values ​​of the input power sources connected to the m input connectors, and switches on the path between the input connector connected to the input power source with the largest voltage value and the output power source end, so that the output power connector is used to connect to the input power source with the highest voltage value.

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