Motor control circuit, motor control IC, and motor drive control method

Abstract

The invention provides a motor control circuit, a motor control IC and a motor drive control method. A motor control circuit (10) that supplies a drive voltage to a brushless DC motor (5) via a motor drive unit (2) is provided with: a current zero point detection unit (13) that detects a voltage corresponding to a drive current flowing through a coil of the motor and that detects a timing at which the drive current becomes zero; a position detection signal generation unit (12) that outputs a reference position detection signal (FGoffset) on the basis of the Hall signal generated by the Hall element (6); a phase adjustment unit (14) that adjusts the phase of a target position detection signal (LAFG) after the next cycle of the reference position detection signal on the basis of the timing at which the drive current detected by the current zero point detection unit becomes zero and the reference position detection signal; and a drive control unit (17) that controls and outputs the timing at which the drive voltage is switched so as to match the phase switching point of the target position detection signal.

Description

Technical Field

[0001] The invention relates to a motor control circuit, a motor control IC and a motor drive control method. Background Art

[0002] In a brushless DC motor, in order to make the motor rotate efficiently, it is known that when a rotor having a magnet rotates, the rotation position of the rotor is grasped based on a Hall element output signal detected by a Hall element or by calculating the back electromotive force (BEMF) generated in a stator coil, and a drive current flows in the same phase as the rotation of the rotor. (For example, Patent Document 1)

[0003] In this technology, basically, the driving voltage applied to both ends of the coil is switched in phase with the Hall element output signal or BEMF, so that the driving current flows and the motor is rotated.

[0004] Here, according to the characteristics of the coil of the brushless DC motor (V=L*dI / dt), the drive current changes with a time delay relative to the switching of the drive voltage on / off. In addition, in order to increase the rotation speed of the motor, the required current becomes larger, and the larger the current, the greater the time delay.

[0005] Thus, when the motor rotates at high speed, the phase of the drive current is offset from the phase indicating the actual position of the rotor, so that the drive force cannot be fully transmitted to the torque. Even if the current is increased, the rotation speed does not increase proportionally as expected, and the efficiency decreases.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2004-153921 Summary of the invention

[0007] Therefore, in view of the above situation, the present invention provides a motor control circuit that can improve the efficiency of the motor when it rotates at high speed, and can rotate at a sufficiently high speed through a predetermined current amount, and can rotate with less current even at the same rotation speed.

[0008] A motor control circuit according to one embodiment of the present invention provides a drive voltage to a brushless DC motor via a motor drive unit, and the motor control circuit includes:

[0009] a current zero point detection unit for detecting a voltage corresponding to a drive current flowing through a coil of the motor to detect a timing when the drive current becomes zero;

[0010] a position detection signal generating unit that outputs a position detection signal serving as a reference based on a Hall signal generated by the Hall element;

[0011] a phase adjustment unit that adjusts the phase of a target position detection signal after the next cycle of the reference position detection signal based on the timing at which the drive current is zero detected by the current zero point detection unit and the reference position detection signal; and

[0012] A drive control unit controls the timing of switching the drive voltage so as to match the phase switching point of the target position detection signal and outputs the control voltage.

[0013] According to one embodiment, the motor control circuit can improve the efficiency of the motor when it rotates at a high speed, and can rotate the motor at a sufficiently high speed with a predetermined current amount, and can rotate the motor with a smaller current even at the same rotation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing a configuration of a motor drive control device according to an embodiment of the present invention.

[0015] Figure 2 This is a circuit diagram of a current zero point detection unit, a position detection signal generation unit, and a phase adjustment unit.

[0016] Figure 3 This is a diagram for explaining the flow of current in the H-bridge circuit and the motor when the phase of the driving voltage is reversed.

[0017] Figure 4 It is a diagram showing the operation according to the situation when the adjustment signal Offset Enable is OFF in the current zero point detection unit.

[0018] Figure 5 This is a diagram showing the input-output characteristics of the inverter included in the current zero point detection unit.

[0019] Figure 6 It is a diagram showing the operation according to the situation when the adjustment signal Offset Enable is turned on in the current zero point detection unit.

[0020] Figure 7 This is a diagram for explaining the overall operation of a comparative example in which the advance angle adjustment is not performed.

[0021] Figure 8 This is a diagram for explaining the signal operation during stable rotation in a motor drive control device.

[0022] Fig. 9 This is a schematic flowchart of control during stable rotation according to one embodiment.

[0023] Fig.10 This is a detailed flowchart of current zero point detection during stable rotation according to one embodiment.

[0024] Fig.11It is a diagram for explaining the overall operation when the advance angle adjustment of the present invention is performed. DETAILED DESCRIPTION

[0025] Hereinafter, the embodiments will be described with reference to the drawings. In each of the drawings, the same components are denoted by the same reference numerals, and overlapping descriptions may be omitted.

[0026] First, refer to Figure 1 , Figure 2 , the structure of a motor drive control device according to one embodiment of the present invention is described. Figure 1 It is a diagram showing a configuration of a motor drive control device according to an embodiment of the present invention. Figure 2 This is a circuit diagram of a current zero point detection unit, a position detection signal generation unit, and a phase adjustment unit.

[0027] The motor drive control device 4 is incorporated in a fan motor for cooling a heat generating component such as a processor in an electronic device such as a notebook personal computer, for example. The motor driven by the motor drive control device 4 is a brushless DC (Direct Current) motor (BLDC).

[0028] The motor drive control device 4 is a circuit for driving a single-phase motor 5 for rotating a cooling fan, for example, and is configured to include a control circuit 10, an H-bridge circuit 2, and a detection resistor 3. The control IC 1 (motor control IC) is a semiconductor integrated circuit for controlling a motor drive unit, and is configured to include a terminal in the control circuit 10. In addition, the motor drive control device 4 inputs a Hall signal from a Hall element 6.

[0029] The control circuit 10 includes a PWM signal generating unit 11, a position detection signal generating unit 12, a current zero point detecting unit 13, a phase adjusting unit 14, an output control unit / soft switching period generating unit 15, and a gate driver 16. The output control unit / soft switching period generating unit 15 and the gate driver 16 function as a drive control unit 17.

[0030] The H-bridge circuit 2 is a motor driving unit and is composed of PchFETM1 and M2 and NchFETM3 and M4. PchFETM1 functions as a first upper switch, NchFETM4 functions as a first lower switch, PchFETM2 functions as a second upper switch, and NchFETM3 functions as a second lower switch.

[0031] The detection resistor 3 is connected to the H-bridge circuit 2 and is used when detecting the current flowing through the coil L of the single-phase motor 5 .

[0032] The rotor (not shown) of the single-phase motor 5 is provided with a magnet, and the Hall element 6 is fixed so as to be able to detect the magnetic field of the magnet provided on the rotor, and the Hall element 6 outputs the Hall signals IN1 and IN2 of the voltage level corresponding to the intensity of the detected magnetic field to the terminal. As the rotor rotates, the magnet also rotates, and the Hall element 6 detects the change of the magnetic field accompanying the rotation of the magnet, thereby detecting the position of the rotor. In addition, the Hall signals IN1 and IN2 of this embodiment are, for example, sinusoidal signals with an amplitude of a predetermined voltage level, and are output to the terminal of the control IC1. In addition, the Hall signals IN1 and IN2 are not limited to sinusoidal waves.

[0033] The position detection signal generating unit 12 compares the levels of the Hall signals IN1 and IN2 and generates an FG signal (frequency generation) which is a signal whose frequency changes according to the rotation speed of the single-phase motor 5 .

[0034] Specifically, the position detection signal generating unit 12 includes hysteresis comparators 21 and 22 , glitch filters 23 and 24 , a signal processing unit 25 , and an offset processing unit 26 .

[0035] Hysteresis comparators 21 and 22 compare the levels of Hall signals IN1 and IN2. When inverted signals are input at close times, a whisker-like glitch pulse may be generated in the output due to the difference in delay time of the noise signal near it. Glitch filters 23 and 24 remove unnecessary glitch pulses so that the pulses do not adversely affect the next-stage logic circuit, i.e., the signal processing unit 25, as noise.

[0036] On this basis, the signal processing unit 25 generates an FG signal, which becomes a low level (hereinafter referred to as the "L" level) when the level of the Hall signal IN1 is higher than the level of the Hall signal IN2, and becomes a high level (hereinafter referred to as the "H" level) when the level of the Hall signal IN1 is lower than the level of the Hall signal IN2.

[0037] The offset processing unit 26 stores a predetermined amount of offset (a period shorter than the phase adjustment range), and outputs a position detection signal FG_offset obtained by advancing the phase of the FG signal as a position detection signal during stable rotation.

[0038] In this way, the position detection signal generating unit 12 outputs the position detection signal FG consistent with the Hall signal generated by the Hall element as a reference at startup. During stable rotation, the position detection signal FG_offset is output based on the phase that is advanced (offset) by a predetermined amount from the Hall signal. Thus, in a state where the rotation is unstable such as during startup, the motor is driven at the switching position of the actual Hall signal at which the motor can reliably operate, and during stable rotation, the motor is driven at a position where the phase switching is suitable for the motor characteristics. In addition, in this example, an example is shown in which the offset position detection signal FG_offset is advanced in phase relative to the position detection signal FG, but the position detection signal FG_offset may also be a signal that is delayed by a predetermined amount in phase relative to the position detection signal FG depending on the situation.

[0039] The PWM (Pulse Width Modulation) signal generating unit 11 generates a PWM signal which is a switching signal for driving the PchFETs M1 and M2 and the NchFETs M3 and M4 constituting the H-bridge circuit 2 based on the position detection signal FG or FG_offset.

[0040] The duty ratio of the PWM signal generated by the PWM signal generator 11 is fixed, and the output voltage Vout does not change. In this control, when switching the drive voltage, soft switching is performed in stages between H and L, and the control of the soft switching is performed by the output control unit / soft switching period generator 15 at the subsequent stage.

[0041] The current zero point detection unit 13 detects the voltage Vsns between the H-bridge circuit 2 and the detection resistor 3 during the current monitoring period, which is an angular period before and after the phase switching point in the position detection signal serving as a reference.

[0042] The voltage Vsns between the H-bridge circuit 2 and the detection resistor 3 is calculated by (fixed resistance value Rsns of the detection resistor 3)×(current Idr flowing through the coil L). Therefore, the detection voltage Vsns can be said to be a voltage corresponding to the drive current Idr flowing through the coil L.

[0043] The sampling signal SW_SAMP_A, the standby signal SW_OFFSET_A, and the adjustment signal Offset Enable are input to the current zero point detection unit 13. The adjustment signal Offset Enable is turned on when it is desired to improve or change the motor characteristics. For example, when an offset occurs in the actual Vsns level or the reference GND level due to wiring impedance, it is used to eliminate the offset. That is, the on / off of the adjustment signal Offset Enable is not operated in conjunction with some action in a series of actions, but is in accordance with the initial setting of whether an offset is desired to be added to the level of the current zero point detection.

[0044] In detail, the current zero point detection unit 13 includes a switch group 31, a voltage comparison circuit 30, and a latch processing unit 33 as a permanent circuit used regardless of the on / off of the adjustment signal Offset Enable. The switches 311 and 312 constituting the switch group 31 switch the input end of the voltage comparison circuit 30 to the detection voltage Vsns and the ground voltage GND based on the on / off (or high / low) state of the sampling signal SW_SAMP_A and the standby signal SW_OFFSET_A as two signals. The voltage comparison circuit 30 includes capacitors 301, 303, inverters 302, 304, and 305, and also includes switches 306 and 307 that short-circuit the inverters 302 and 304, respectively. The latch processing unit 33 outputs a state notification signal Zero_det_latch based on the result of the zero point output Zero detection, which is the output of the voltage comparison circuit 30.

[0045] Furthermore, the current zero point detection unit 13 includes a switch 32, a constant current source 34 connected to a resistor 342, a switch group 35, and a capacitor 308, as an additional offset circuit (adjustment circuit) used only when the adjustment signal Offset Enable is turned on. When the adjustment signal Offset Enable is turned on, the switch 32 is turned on, the adjustment circuit is connected, the capacitor 308 is connected as a part of the voltage comparison circuit 30a, and the constant voltage source 34 or the ground voltage GND is connected to the capacitor 308 by the operation of the switch group 35.

[0046] In more detail, when the adjustment signal Offset Enable is turned on, the capacitor (offset capacitor) 308 is connected in parallel with the capacitor 301 at the front stage of the inverter 302 as part of the voltage comparison circuit 30a. The constant voltage source 34 generates a predetermined constant voltage that becomes an offset voltage. The switches 351 and 352 constituting the switch group 35 switch the input end of the offset capacitor 308 to the voltage Vofs based on the constant voltage source 34 and the ground voltage GND based on the on / off of the sampling signal SW_SAMP_A and the standby signal SW_OFFSET_A. In this case, in the voltage comparison circuit 30a, the value having an offset from the GND level is compared with the detection voltage Vsns and the comparison result is output. In this way, the constant voltage source 34 that generates the offset level is selectively used according to the status of the adjustment signal OffsetEnable.

[0047] like Figure 2 and the following Figure 4As shown, when the switch 32 is turned off by the adjustment signal Offset Enable, the current zero point detection unit 13 switches the internal switches 311, 312, 306, and 307 on / off by the sampling signal SW_SAMP_A used for current zero point detection and the standby signal SW_OFFSET_A used during the current detection standby period in the current monitoring period.

[0048] In the current zero point detection unit 13, during the period of input sampling signal SW_SAMP_A, the voltage stored in capacitors 301 and 303 is compared with the ground voltage by inverters 302, 304, and 305 functioning as comparators. And when the detection voltage Vsns is less than 0, the output Zerodetection becomes H at the timing zero point of the input sampling signal SW_SAMP_A. Figures 4 to 6 The operation of the current zero point detection unit 13 will be described in detail.

[0049] Then, the latch processing unit 33 sets the state notification signal Zero_det_latch, which is a latch output signal and a continuous signal, to H at the timing when the sampling signal SW_SAMP_A drops to L, and maintains the H state until the next sampling signal SW_SAMP_A drops, and again takes in the state of the zero point output Zerodetection at the timing of the sampling signal SW_SAMP_A dropping. If the zero point output Zero detection is H, the output state notification signal Zero_det_latch remains H. If Vsns is greater than 0 and Zero detection is L, the output state notification signal Zero_det_latch switches to L and maintains the state until the next sampling signal SW_SAMP_A drops. This action is repeated within a predetermined current monitoring period. In addition, for the details of the action in the current zero point detection unit 13, according to Figure 8 , Fig.10 This will be described later.

[0050] With such a configuration, the current zero point detection unit 13 converts the state of the motor current into a continuous state notification signal Zero_det_latch during the current monitoring period, rather than converting it into a discrete signal through PWM. As a result, the end timing of the detection state of the state notification signal Zero_det_latch corresponding to the state notification of the driving current can be recognized as the timing of the current flowing from zero to the positive direction without being affected by the on / off operation of PWM.

[0051] In addition, the phase adjustment unit 14 adjusts the phase of the target position detection signal after the next cycle of the reference position detection signal based on the output result of the current zero point detection unit 13 and the reference position detection signal FG or FG_offset, and outputs it as a lead angle position detection signal (Lead_angle FG, hereinafter referred to as LAFG signal).

[0052] In detail, Figure 2 As shown, the phase adjustment unit 14 includes a phase switching times counter 41 , an intra-cycle time counter 42 , and a LAFG signal generation unit 43 .

[0053] The phase switching count counter 41 counts the number of phase switching times (in this example, the number of times the signal falls from H to L) of the position detection signal (FG or FG_offset) output from the position detection signal generating unit 12 .

[0054] For example, when the rotation is stable, the phase adjustment (advance angle adjustment) of the drive current is performed every time the phase of the FG signal is switched 16 times. Therefore, the phase switching number counter 41 counts the number of phase switching times k, and when the last phase adjustment is the 15th time, the counter of the cycle time counter 42 is started to start the current zero point detection unit 13 to monitor the current zero point.

[0055] The intra-cycle time counter 42 starts the time counter to monitor the current zero point near the phase switching time point of the FG signal before the phase adjustment object. The intra-cycle time counter 42 counts the time within the half cycle T of the immediately preceding FG signal (or FG_offset signal), and when the time reaches T×(180°-θ) / 180°, the monitoring operation of the current zero point (current zero crossing point) is started, and the current monitoring period is set.

[0056] During the current monitoring period, the intra-cycle time counter 42 outputs the sampling signal SW_SAMP_A used in the current zero point detection and the standby signal SW_OFFSET_A used in the period other than the current detection to the current zero point detection unit 13. Then, after the time of the half cycle T×(180°+θ) / 180°, the current zero point monitoring operation is terminated. In addition, θ is set to an arbitrary value between 30° and 60°, for example.

[0057] The LAFG signal generation unit 43 outputs the LAFG signal, which is a FG signal whose phase (advanced angle or delayed angle) is adjusted with respect to the FG signal or the FG_offset signal, based on the detection result of the current zero point.

[0058] The output control unit / soft switching period generator 15 adjusts the timing for changing the driving voltage by controlling the PWM signal, that is, the voltage on / off timing, based on the LAFG signal.

[0059] The output control unit / soft switching period generator 15 internally generates a signal for instructing a period for soft switching the single-phase motor 5 based on the internally generated voltage and the position detection signal FG or FG_offset output from the position detection signal generator.

[0060] Thus, in the output control unit / soft switching period generator 15, the duty ratio is gradually changed before the opposite point of the FG signal / or FG_offset. Figure 7 When the output voltage Vout increases as in the period Ti, the duty ratio is gradually increased, and when the output voltage Vout decreases as in the period Td, the duty ratio is gradually decreased. Furthermore, when the soft switching period ends, the duty ratio of the PWM signal becomes predetermined or zero.

[0061] Then, the output control unit / soft switching period generating unit 15 generates control signals IN1H, IN2H, IN1L, IN2L and outputs them to the gate driver 16. The control signals IN1H, IN2H, IN1L, IN2L are set to soft switches that change the periods of H and L in stages when switching the driving voltages of the FETs M1, M2, M3, M4 used to switch the H-bridge circuit 2 respectively.

[0062] The gate driver 16 controls each MOSFET of the H-bridge circuit 2 to change the drive current Idr that drives the motor coil L of the single-phase motor 5. Specifically, the gate driver 16 outputs gate control voltages GH1, GH2, GL1, and GL2 for turning on / off the gates of the FETs M1, M2, M3, and M4 of the H-bridge circuit 2, respectively.

[0063] Here, use Figure 3 The flow of the driving current will be described. Figure 3 2 is an explanatory diagram of the flow of current in the H-bridge circuit 2 when the phase of the driving voltage is reversed. Figure 3 In FIG. 1 , (a) shows the current flow when the first switches M1 and M4 are turned on before the FG signal is switched, (b) shows the current flow when the second switches M2 and M3 are turned on just after the switching, and (c) shows the current flow when the second switches M2 and M3 are turned on a little after the switching. Figure 3 In FIG. 1 , the single-phase motor 5 is shown as the coil L, and other single-phase motors include reverse voltage, resistance, etc., but they are omitted from the drawing.

[0064] When generating a positive drive current Iout, for example, the gate driver 16 turns off the FETs M2 and M3 as the second switch and turns on the FETs M1 and M4 as the first switch through a PWM signal. Figure 3 As shown in (a) of FIG. 8 , the drive current flows in the motor coil L in the direction of Idr1 , and a positive-side detection voltage Vsns is generated in the detection resistor 3 .

[0065] For example, when the gate driver 16 switches the driving phase to disconnect FETM1 and M4 and connect FETM2 and M3 while the current flows through the motor coil L in the direction of Idr1, the direction of the current cannot be changed quickly due to the characteristics of the coil, and the current flows directly in the direction of Idr1 through the connected FETM2 and M3. At this time, the driving voltage Vout is negative, but the driving current Iout is still positive.

[0066] According to the current direction here, in FETM2 and M3, negative current flows from GND through the detection resistor 3 from the source side to the drain side. That is, the current flows from the GND level to the Figure 3 Since the current flows in the direction of the arrow in (b), a negative detection voltage Vsns is generated in the detection resistor 3.

[0067] As time goes on, the direction of the current flowing through coil L changes, as shown in Figure 3 Therefore, the drive current flows through the motor coil L of the motor 5 in the direction of Idr2. At this time, the drive voltage Vout is negative, the drive current Iout is also negative, and a voltage Vsns on the positive side is generated in the detection resistor 3.

[0068] (Details of Operation of Current Zero Point Detection Section)

[0069] Here, use Figures 4 to 6 The operation of the current zero point detection unit 13 will be described in detail.

[0070] Figure 4 1 and 2 are diagrams showing operations according to situations when the adjustment signal Offset Enable is turned off in the current zero point detection unit 13 . Figure 5 1 is an input-output characteristic diagram of the inverter included in the current zero point detection unit 13 . Figure 6 1 and 2 are diagrams showing operations according to situations when the adjustment signal Offset Enable is turned on in the current zero point detection unit 13 .

[0071] First, use Figure 4 , Figure 5The operation of the current zero point detection unit 13 when the adjustment signal Offset Enable is turned off is described. When the adjustment signal Offset Enable is turned off, the switch 32 is turned off, and the switch 32, the constant voltage source 34, the switch group 35, and the capacitor 308 as the adjustment circuit are not used at all. Figure 4 The record is omitted.

[0072] In detail, Figure 4 As shown in (a), in the current zero point detection unit 13, first, when SW_OFFSET_A is at the H level and SW_SAMP_A is at the L level, the switch (FET) 312 is turned on, thereby biasing one end of the capacitor 301 to the GND level. In addition, by turning on the switch 306, the input and output of the inverter 302 become the intermediate potential Vth2 that is neither H nor L according to the characteristics of the inverter, and the other end of the capacitor 301 accumulates charge to the intermediate potential Vth2. Therefore, the charge corresponding to the difference between them (Vc1 = Vth2-0) is accumulated in the capacitor 301.

[0073] In addition, by turning on the switch 307, the input and output of the inverter 304 become the intermediate potential Vth4 which is neither H nor L according to the characteristics, the intermediate potential Vth2 generated by the inverter 302 is biased at one end of the capacitor 303, and the intermediate potential Vth4 generated by the inverter 304 is biased at the other end, and the charge corresponding to the difference between them (Vc3=Vth4-Vth2) is accumulated in the capacitor 303. Through the above operation, the offset voltages (Vc1, Vc3) accumulated and generated in the capacitors 301 and 303 respectively when the GND level is used as a reference become the reference of the operating points of the inverters 302 and 304.

[0074] Here, use Figure 5 The inverter threshold in the current zero point detection unit will be described. Figure 5 is an input-output characteristic diagram of the inverters 302 and 304 included in the current zero point detection unit. Here, it is assumed that the characteristics of the two inverters are slightly different. Figure 5 In FIG. 1 , the input-output characteristic of the inverter 302 at the first stage is indicated by a dashed line, and the input-output characteristic of the inverter 304 at the second stage is indicated by a solid line.

[0075] In the voltage comparison circuit 30, the level difference (Vsns-GND) of the primary input voltage needs to be detected at a very small level. Therefore, in the primary inverter 302, (Vsns-GND (0)) is amplified to (302_OUT-Vth2). Moreover, even if the characteristics are offset, due to the effect of the input capacitor 303, it will become the form of adding 302_OUT-Vth2 to the intermediate potential Vth4 and input to the second-stage inverter 304. Then, it is amplified by the inverter 304 to become a level 304_OUT very close to the H level. If it is amplified to this, according to the input 305_IN (=304_OUT) of the third-stage inverter 305, it can be seen that the output of the third-stage inverter 305 becomes the so-called "L level".

[0076] Thus, the three-stage inverter is used to amplify the signal level, and the input capacitors 301 and 303 are not affected by the characteristics of the inverter, and the input voltage level of the inverter can be added based on the threshold level of the inverter. Thus, the small voltage level of the detection voltage Vsns can also be outputted at two values ​​of so-called H / L.

[0077] In detail, Figure 4 As shown in (a) of FIG. 1 , after the charge corresponding to the offset voltage is accumulated in the capacitors 303 and 304, the standby signal SW_OFFSET_A is switched to the L level state and the sampling signal SW_SAMP_A is switched to the H level state. Figure 4 As shown in (b) of FIG. 3 , the switch (FET) 312 is turned off and the switch 311 is turned on, so that one end of the capacitor 301 is biased to the detection voltage Vsns. Figure 3 (a) Figure 3 As in state (c), when the potential of the detection voltage Vsns is higher than the GND level, the voltage at the other end of the capacitor 301 rises from the above-mentioned intermediate potential by the potential amount of Vsns (Vth2+Vsns) according to the offset voltage accumulated in the capacitor 301.

[0078] In addition, Figure 4 In the state (b), switches 306 and 307 are turned off, so inverters 302 and 304 operate purely as inverters. When the potential of the detection voltage Vsns is higher than the GND level, as described above, the input voltage of the inverter 302 rises from the intermediate potential Vth2 by the potential of Vsns, thereby exceeding the phase switching point of the inverter 302, the input becomes H, the output of the inverter 302 shifts to L, and the output Figure 5 The output voltage 302_OUT is shown.

[0079] In the subsequent capacitor 303, in addition to the original intermediate potential Vth4, a potential of (302_OUT-Vth2) is accumulated (Vc3=Vth4-(302_OUT-Vth2)) according to the output voltage of the inverter 302.

[0080] Therefore, if Figure 5 As shown, in the inverter 304, the input is lower than the phase switching point and becomes L, so that the output of the inverter 304 becomes H. In addition, the inverter 305 of the next stage performs the opposite operation to the inverter 304, and the input of the inverter 305 becomes H, so that the output of the inverter 305, that is, the Zero_detection signal, becomes L.

[0081] On the other hand, in Figure 3 When the potential of the detection voltage Vsns is lower than the GND level as in the state (b) of Figure 4 As shown in (c), the voltage at the other end of the capacitor 301 is reduced by the potential amount of Vsns from the above-mentioned intermediate potential Vth2 according to the offset voltage accumulated in the capacitor 301 (Vc1=Vth2-Vsns). As a result, the input of the inverter 302 becomes L, and the output is transferred to H. After that, the capacitor 303, the switch 307 and the inverter 304 also perform the same operation as above, and in the inverter 304, the input becomes H, thereby the output becomes L, and the input of the inverter 305 becomes L, thereby the output of the inverter 305, that is, the Zero_detection signal becomes H.

[0082] The Zero_detection signal outputted from the voltage comparison circuit 30 is inputted to the latch processing unit 33. The latch processing unit 33 outputs a continuous state notification signal Zero_det_latch (see FIG. 1 ) of switching between H and L only when the H and L of the Zero_detection signal change during the intermittent discontinuous on period of the switch 311 for taking in the detection voltage Vsns and the on periods before and after. Figure 8 ).

[0083] Thus, the current zero point detection unit 13 detects that the drive current reaches zero point by detecting the timing when the voltage Vsns corresponding to the output current Iout switches from zero or a negative value to a positive value, and notifies the state notification signal Zero_det_latch at the timing when it changes from H to L.

[0084] And, use Figure 6 The operation of the current zero point detection unit 13 when the adjustment signal Offset Enable is turned on will be described. Figure 6In the adjustment circuit of FIG. 1 , an example is schematically shown in which, in order to set the positive side offset, the standby signal SW_OFFSET_A is input to the switch 351 and the sampling signal SW_SAMP_A is input to the switch 352. Therefore, when the switch 32 is turned on by the adjustment signal Offset Enable, the current zero point detection unit 13 switches the internal switches 311, 312, 306, 307 and the switches 351 and 352 on / off by the sampling signal SW_SAMP_A used for the detection of the current zero point and the signal SW_OFFSET_A used during the current detection standby period in the current monitoring period.

[0085] In detail, Figure 6 As shown in (a), in the current zero point detection unit 13, first, in the state where SW_OFFSET_A is at the H level and SW_SAMP_A is at the L level, the switch (FET) 312 is turned on, and the switch 352 in the adjustment circuit is turned on. As a result, the voltage Vofs (voltage based on the constant voltage source) connected to the ground from the constant voltage VDD generated by the constant voltage source 34 via the resistor 342 is biased to one end of the capacitor 308. On the other hand, at the other end of the capacitor 308, the voltage of the intermediate potential Vth2 of the connection destination is formed, and therefore the difference (Vc8=Vth2-Vofs)) is accumulated in the capacitor 308. In addition, in this state, since capacitors 301 and 308 are connected in parallel with inverter 302, the offset voltage (Vc1) generated by accumulating in capacitor 301 with the GND level as a reference is compared with the offset voltage (Vc8) generated by accumulating in capacitor 301 with the GND level as a reference, and the voltage adjusted by charging and discharging becomes the reference of the operating point of inverter 302.

[0086] As described above, after the charge of the offset voltage is accumulated in the capacitors 303, 304, and 308, the standby signal SW_OFFSET_A switches to the L level state, and the sampling signal SW_SAMP_A switches to the H level state, and as shown in FIG. Figure 6 As shown in (b), the switch (FET) 312 is turned off and the switch 311 is turned on, so that one end of the capacitor 301 is biased to the detection voltage Vsns. Moreover, by turning on the switch 351, as shown in FIG. Figure 6 As shown in (b), the capacitor 301 is discharged to the capacitor 308. If the capacitance of the capacitor 308 is 1 / 20 of the capacitance of the capacitor 301, the input voltage of the inverter 302 becomes [Vth2-Vofs / 20+Vsns].

[0087] Here, in Figure 3 (a) Figure 3When the potential of the detection voltage Vsns is higher than the GND level as in the state (c) of FIG. 1 , the detection voltage Vsns is further compared with the offset voltage Vofs / 20. When the detection voltage Vsns is larger than the positive offset voltage Vofs / 20, Vth2-Vofs / 20+(Vsns(+))>Vth2 is achieved, the input of the inverter 302 becomes H, and the output of the inverter 302 shifts to L. Thereafter, the capacitor 303, the switch 307, and the inverter 304 also perform the same operation as described above, and in the inverter 304, the input becomes L, thereby the output becomes H, and the input of the inverter 305 becomes H, thereby the output of the inverter 305, that is, the Zero_detection signal becomes L.

[0088] On the other hand, when the detection voltage Vsns is compared with the offset voltage Vofs / 20, if the positive detection voltage (Vsns) is smaller than the positive offset voltage Vofs / 20, Vth2-Vofs / 20+(Vsns(+))<Vth2 is achieved, the input of the inverter 302 becomes L, and the output of the inverter 302 shifts to H. Thereafter, the capacitor 303, the switch 307, and the inverter 304 also perform the same operation as described above, and in the inverter 304, the input becomes H, thereby the output becomes L, and the input of the inverter 305 becomes L, thereby the output of the inverter 305, that is, the Zero_detection signal becomes H.

[0089] In addition, in Figure 3 When the detection voltage Vsns is negative as in the state (b) of Figure 6 As shown in (c), there is no need to compare Vofs / 20, and it becomes Vth2-Vofs / 20+(Vsns(-))<Vth2, so the input of the inverter 302 becomes L, and the output of the inverter 302 is transferred to H. After that, the capacitor 303, the switch 307, and the inverter 304 also perform the same operation as above, and in the inverter 304, when the input becomes H, the output becomes L, and the input of the inverter 305 becomes L, and the output of the inverter 305, that is, the Zero_detection signal becomes H.

[0090] In this way, by connecting the adjustment circuit including the constant voltage source 34 using the adjustment signal Offset Enable, the threshold level of the inverter 302 in the voltage comparison circuit can be offset relative to the GND level. Figure 6 In the example shown, the zero point of the detection voltage Vsns is simply changed from the GND level to the level of positive Vofs / 20.

[0091] In addition, Figure 6In the embodiment, by inputting the standby signal SW_OFFSET_A to the switch 351 and the sampling signal SW_SAMP_A to the switch 352, the zero point of the detection voltage Vsns changes from the GND level to the level of positive Vofs / 20, but as Figure 2 As shown in the brackets of , by inputting the standby signal SW_OFFSET_A to the switch 352 and the sampling signal SW_SAMP_A to the switch 351 , the zero point of the detection voltage Vsns can be changed from the GND level to a level of negative Vofs / 20.

[0092] Based on the offset generation of the additional adjustment circuit, the adjustment function is turned on / off for the purpose of correcting the offset between the GND level of the motor current zero point detection unit 13 and the GND level of the device (the entire motor drive device 4) when the offset occurs due to, for example, a difference in wiring impedance, or providing an offset to avoid malfunction when erroneous detection / malfunction occurs due to slight noise near GND. In addition, the adjustment function is turned on / off without being linked to the FG cycle at the timing other than the current monitoring period.

[0093] (Comparative Example)

[0094] Figure 7 This is a diagram for explaining the overall operation of a comparative example in which the advance angle adjustment is not performed.

[0095] In a BLDC motor, due to the characteristics of the coil (V=L*dI / dt), the drive current changes with a time delay relative to the switching of the drive voltage on / off. Figure 7 In the example of , the zero point of the driving current Iout is delayed by a time D relative to the zero point (zero crossing point) of the driving voltage Vout.

[0096] Here, in order to increase the speed of the motor, the required current becomes larger, and the larger the current, the greater the time delay. Thus, when the motor rotates at high speed, the phase of the driving current is offset from the phase of the actual position of the motor detected by the Hall element, so that the driving force cannot be fully transmitted to the torque. Even if the current is increased, the speed will not increase proportionally as expected, and the efficiency will decrease.

[0097] (Motion Control)

[0098] Therefore, in the present invention, the timing of changing the drive voltage is adjusted based on the timing of the actual current zero point detected, thereby performing control so that the phase switching point of the position detection signal FG or FG_offset coincides with the zero crossing point of the drive current.

[0099] Here, use Figure 8 Action diagram and Fig. 9 , Fig.10 The flowchart of FIG. 1 illustrates a case where an advance angle control is performed every 16 phase switchings as an example of control in the present invention. Figure 8 This is a diagram for explaining the signal operation during stable rotation in a motor drive control device. Fig. 9 This is a schematic flowchart of control during stable rotation according to one embodiment of the present invention. Fig.10 This is a detailed flowchart of current zero point detection during stable rotation according to one embodiment of the present invention. As described above, in the present invention, the current zero point in the actual drive current is detected and control is performed in a manner consistent with the rotor position detection signal.

[0100] exist Figure 8 , Fig. 9 , Fig.10 The operation during stable rotation (high-speed rotation) is shown in . The position detection signal of the rotor that becomes the target position during high-speed rotation is the FG_offset signal.

[0101] exist Figure 8 , it is shown that one step (predetermined amount) of the advance angle control is equivalent to one cycle of the PWM signal and is an example of 1 / 1024 (≈0.35 degrees) of one cycle of the FG signal.

[0102] When to start Fig. 9 When the lead angle is adjusted, first in step S101 the LAFG signal generating unit 43 makes the LAFG signal (Lead_angle FG) and the FG_offset signal in phase.

[0103] Then, in S102 , when the phase switching occurs in the FG_offset signal, the phase switching number counter 41 increases the phase switching number k of the FG_offset signal by 1 ( S103 ).

[0104] Before the number of phase switching times k becomes 15 ("No" in S104), current zero point detection and advance angle adjustment are not performed. After repeatedly performing S102 and S103, if the number of phase switching times k becomes 15 ("Yes" in S104), the next step is entered, and the intra-cycle time counter 42 starts counting the time within the half cycle T of the FG_offset signal (S105).

[0105] If the intra-cycle time counter 42 counts to the time of half cycle T×(180°-θ) / 180° (S106), it starts monitoring the current and starts the current zero point detection operation (S107). Fig.10 We will describe them together later. Figure 8 The operation diagram shows an example in which the starting angle of the current zero point detection operation is -45° of the phase switching of the FG_offset signal.

[0106] After that, when the intra-cycle time counter 42 counts to half cycle T×(180°+θ) / 180°, the current monitoring period ends, and the current zero point monitoring operation ends (S108). Figure 8 The operation diagram shows an example in which the end angle of the current zero point check operation (current monitoring period) is +44.65° of the phase switching of the FG_offset signal.

[0107] Here, in parallel with the current zero point detection process, as the phase of the FG_offset signal is switched, the drive voltage decreases with a gradient, and the drive current also switches phases (S109). When the number of phase switching times k of the FG_offset signal reaches 16, the number of phase switching times k of the FG_offset signal is reset to 0 (S110).

[0108] After that, the process proceeds to the FG phase adjustment (advance angle adjustment) step of S111 to S117.

[0109] First, between S106 and S108, if Figure 8 As shown, first, it is confirmed whether the current zero point is detected, that is, the LAFG signal generation unit 43 confirms whether the state notification signal Zero_det_latch output during the current monitoring period is H (detection state) (S111).

[0110] When the current zero point is not detected (No in S111), it is considered that the phase of the drive current is greatly delayed relative to the current monitoring period, and the phase of LAFG is advanced by one step (S114). In addition, one step of the phase change of LAFG in the next cycle is equivalent to one cycle of the PWM signal, and is greatly shortened than the current monitoring period in the FG_offset signal, for example, 0.35 degrees.

[0111] When the current zero point is detected (YES in S111 ), it is checked whether a fall of the state notification signal Zero_det_latch is detected (end of the detection state).

[0112] When the drop of the state notification signal Zero_det_latch is not detected (No in S112), it means that the end point of the current monitoring period is within the period when the state notification signal Zero_det_latch remains H. Therefore, it is considered that the phase of the drive current is greatly delayed relative to the current monitoring period, making the phase of LAFG one step forward (S114).

[0113] When the fall of the state notification signal Zero_det_latch is detected (Yes in S112 ), the fall timing is compared with the phase switching timing of k=16 of the FG_offset signal ( S113 ).

[0114] When the falling timing of the state notification signal Zero_det_latch is later than the phase switching timing of the FG_offset signal (Yes in S113 ), the phase of the LAFG is advanced by one step ( S114 ).

[0115] When the falling timing of the state notification signal Zero_det_latch is before the phase switching timing of the FG_offset signal (No in S113), the phase of LAFG is delayed backward by one step (S115).

[0116] Through S111 to S115, the switching timing of LAFG in the next cycle of the FG_offset signal is determined, and the driving voltage generated by the output control unit / soft switching period generation unit 15 and the gate driver 16 is controlled in coordination with the switching timing of LAFG, thereby adjusting the timing of voltage change (S116).

[0117] Here, use Fig.10 The detection of the current zero point during the current monitoring period will be described in detail.

[0118] If the intra-cycle time counter 42 counts to the half cycle T×(180°-θ) / 180°( Fig. 9 S107), then start monitoring the current and start the current zero point detection action (START).

[0119] First, the state notification signal Zero_det_latch is reset to L ( S201 ).

[0120] Before the driving PWM signal is turned on, the standby signal SW_OFFSET_A is turned off ( S202 ), and when the driving PWM signal (1N1H of driving M1 ) is turned on at the timing of the PWM cycle ( S203 ), the sampling signal SW_SAMP_A is turned on at the same time ( S204 ).

[0121] In soft switching, the on-time is controlled to be gradually shortened as the current approaches 0 in the PWM cycle. However, during the current monitoring period, if there is a portion of the on-time of the driving PWM signal that is less than t (1.0 μs) (Yes in S205), the on-time is set longer to be greater than t (1.0 μs) (S206). Figure 8 2 shows an example in which the minimum value of the PWM on period is set to 1.1 μs, t=1.0 μs.

[0122] When all the on-periods of the driving PWM signals are longer than t (1.0 μs) (No in S205 ), adjustment is unnecessary and the process proceeds to the next step.

[0123] Thereafter, when the sampling signal SW_SAMP_A is turned on, the detection voltage Vsns is monitored for a predetermined period t (1.0 μs) ( S207 ).

[0124] Then, the monitoring result of the detection voltage Vsns is output to the latch processing unit 33 as a zero point output Zero detection (S208).

[0125] Then, in the latch processing unit 33, the zero point output Zero detection is sampled after the sampling signal SW_SAMP_A is turned on and a predetermined period t (1.0 μs) has passed (S209).

[0126] As a result of sampling, when the zero point output Zero detection input to the latch processing unit 33 is H during the on-period of the sampling signal SW_SAMP_A ("Yes" in S210), that is, when the timing detection voltage Vsns sampled by SW_SAMP_A is negative, the output voltage Vout<0 and the output current Iout≥0 are in a state, and the state notification signal Zero_det_latch is H (detection state) (S211).

[0127] On the other hand, when the zero point output Zero detection input to the latch processing unit 33 is L during the on-period of the sampling signal SW_SAMP_A (Yes in S210), that is, when the detection voltage Vsns is not detected to be negative at the timing of sampling by SW_SAMP_A, the state notification signal Zero_det_latch is L. At this time, when the state notification signal Zero_det_latch does not rise, the state of L is maintained. On the other hand, when the state notification signal Zero_det_latch rises in the previous PWM cycle, the state of the output voltage Vout<0 and the output current Iout<0 is reached, the current is lower than the zero point, the state notification signal Zero_det_latch falls, and the detection state ends (S212).

[0128] Then, the state of the state notification signal Zero_det_latch is maintained (S213).

[0129] On the other hand, in parallel with the high-low switching operation of the state notification signal in S210 to S213, when the PWM off period arrives in S214, the sampling signal SW_SAMP_A is turned off and the standby signal SW_OFFSET_A is turned on (S215).

[0130] Then, the next driving PWM on period is waited for (S216). If it is within the current monitoring period (No in S217), the process returns to before S202 and the current zero point detection operation is repeated in each PWM cycle.

[0131] On the other hand, when the intra-cycle time counter 42 counts the time of the half cycle T×(180°+θ) / 180° (YES in S217 ), the current monitoring is stopped and the current monitoring period ends (END).

[0132] In addition, in the above Figure 8 , Fig. 9 , Fig.10 The operation during steady rotation in which the rotation is stable is described above, but the phase control (advance angle control) of the drive current can also be performed in a state other than the steady rotation state.

[0133] exist Figure 8 In the example, the phase of the FG_offset signal is ahead of the phase of the FG signal. The phase offset of the drive current relative to the phase of the BEMF of the rotor detected by the position detection signal of the Hall element 6 is larger during high-speed rotation than during startup. Therefore, it is preferred to switch the original FG signal to the reference signal during soft start as a power startup, and switch the FG_offset signal to the reference signal during high-speed rotation.

[0134] Specifically, at startup and restart after the motor is locked, the PWM input as the speed control input changes and the speed varies, so the output phase switching (advance angle control) is performed according to the FG signal. At this time, the phase adjustment is preferably performed more frequently during the rotation variation until the rotation is stable, for example, every 2 cycles of the FG signal, than when the rotation is stable.

[0135] In addition, the difference between starting and restarting and stable rotation is that in the current zero point detection during the current monitoring period, Fig.10 During the period when the PWM signal (IN2H driving M2) is turned on in the control, the sampling signal SW_SAMP_A is turned on at the same time.

[0136] (Current after advance angle adjustment)

[0137] Fig.11 It is a diagram for explaining the overall operation when the advance angle adjustment of the present invention is performed.

[0138] exist Fig.11 As described above, in the previous phase switching of the FG_offset signal, the lead angle of the LAFG signal of the next cycle is adjusted based on the result of the zero crossing point of the detection current, thereby slightly advancing the timing of the change of the drive voltage. As a result, the zero crossing point of the current Iout slightly delayed from the change of the output voltage Vout coincides with the phase switching (falling) of the FG_offset signal.

[0139] In this way, when the motor rotates at high speed, the phase of the driving current is consistent with the phase of the Hall signal indicating the actual position of the motor, thereby the driving force is fully transmitted to the torque, and if the current is increased, the speed increases proportionally as expected, and the efficiency is improved. Therefore, the motor control circuit of the present invention can improve the efficiency of the single-phase motor when rotating at high speed, and can rotate at a high speed sufficiently by a predetermined current amount, and can rotate with less current even at the same speed.

[0140] (Variant 1)

[0141] In the above example, as the detection timing of the phase switching of the position detection signal (FG or FG_offset), an example of detecting the phase turning point from falling from H to L is described, but the detection of the phase switching may also detect the phase turning point from rising from L to H. In this case, as the zero point detection of the current corresponding to the time point when the position detection signal rises from L to H, the timing of the transition from negative to positive is monitored and detected.

[0142] (Variant 2)

[0143] In the above Figure 1 , a structure using FETs as switches of the H-bridge circuit is described, but the switches of the H-bridge may also be constituted by bipolar transistors.

[0144] (Variant 3)

[0145] In addition, the motor control circuit of the present invention is not only applicable to a single-channel H-bridge, but also applicable to a 1.5-channel H-bridge (three half-bridge) BLDC motor.

[0146] As mentioned above, although the preferred embodiments and the like have been described in detail, the present invention is not limited to the above-mentioned embodiments and the like, and various modifications and substitutions can be made to the above-mentioned embodiments and the like without departing from the scope described in the scope of claims.

[0147] Explanation of symbols

[0148] 1 motor control IC;

[0149] 2H bridge circuit (motor drive unit);

[0150] 3. Detection resistor;

[0151] 4. Motor drive control device;

[0152] 5. Single-phase motor (brushless DC motor);

[0153] 6 Hall element;

[0154] 10. Control circuit (motor control circuit);

[0155] 11PWM signal generating unit;

[0156] 12 position detection signal generating unit;

[0157] 13. Current zero point detection unit;

[0158] 14 phase adjustment unit;

[0159] 15 output control unit / soft switching period generation unit;

[0160] 16 gate drivers;

[0161] 17 drive control unit;

[0162] 30, 30a voltage comparison circuit;

[0163] 301, 303 capacitors;

[0164] 302, 304, 305 inverters;

[0165] 306, 307 switches;

[0166] 308 capacitor (offset capacitor);

[0167] 31 switch group;

[0168] 311, 312 switches;

[0169] 32 switches;

[0170] 34 constant current source;

[0171] 35 switch group;

[0172] 351, 352 switches;

[0173] L coil;

[0174] M1PchFET (first upper switch, first switch);

[0175] M2PchFET (second upper switch, second switch);

[0176] M3NchFET (second lower switch, second switch);

[0177] M4NchFET (first lower switch, first switch);

[0178] Idr driving current;

[0179] The position detection signal that FG and the Hall signal are consistent (the position detection signal that becomes the reference);

[0180] FG_offset is a position detection signal that advances the phase (a position detection signal that becomes a reference);

[0181] LAFG (Lead_angleFG) becomes the position detection signal of the target (position detection signal after lead angle adjustment);

[0182] Vsns detection voltage (voltage corresponding to the drive current);

[0183] Zero_det_latch status notification signal;

[0184] SW_SAMP_A sampling signal (one of two signals);

[0185] SW_OFFSET_A standby signal (one of two signals);

[0186] Offset Enable adjusts the signal.

Claims

1. A motor control circuit that provides a driving voltage to a brushless DC motor via a motor driving unit, characterized in that: The motor control circuit comprises: a current zero point detection unit for detecting a voltage corresponding to a drive current flowing through a coil of the motor to detect a timing when the drive current becomes zero; a position detection signal generating unit that outputs a position detection signal serving as a reference based on a Hall signal generated by the Hall element; a phase adjustment unit that adjusts the phase of a target position detection signal after the next cycle of the reference position detection signal based on the timing at which the drive current is zero detected by the current zero point detection unit and the reference position detection signal; as well as A drive control unit controls the timing of switching the drive voltage so as to match the phase switching point of the target position detection signal and outputs the control voltage.

2. The motor control circuit according to claim 1, characterized in that: The current zero point detection unit is connected to the motor driving unit together with a grounded resistor. The current zero point detection unit detects that the drive current becomes a zero point when a detection voltage corresponding to the drive current becomes a negative value.

3. The motor control circuit according to claim 1, characterized in that: The current zero point detection unit is connected to the motor driving unit together with a grounded resistor. The current zero point detection unit detects that the drive current reaches a zero point by detecting a timing at which a detection voltage corresponding to the drive current switches from zero or a negative value to a positive value.

4. The motor control circuit according to claim 2 or 3, characterized in that: The current zero point detection unit monitors the drive current by using an angular period before and after a phase switching point in the reference position detection signal as a current monitoring period.

5. The motor control circuit according to claim 4, characterized in that: The current zero point detection unit receives two types of signals as input. The current zero point detection unit comprises: Voltage comparison circuit; a switch connected to an input terminal of the voltage comparison circuit, and switching the input voltage of the voltage comparison circuit to the detection voltage or the ground voltage according to the on / off of the signal; as well as a latch processing unit that outputs a state notification signal notifying the state of the drive current based on a comparison result of the voltage comparison circuit, The voltage comparison circuit has: a capacitor to which the input voltage is input; an inverter connected to the rear stage of the capacitor; as well as a switch that short-circuits the inverter during a period when the ground voltage is input according to the states of the two signals, The voltage comparison circuit compares the ground voltage and the detection voltage and outputs a comparison result.

6. The motor control circuit according to claim 5, characterized in that: The current zero point detection unit includes: an adjustment circuit connected via a switch that is turned on when an adjustment signal different from the two signals is turned on; The adjustment circuit comprises: a constant voltage source, which generates a constant voltage; an offset capacitor connected in parallel with the capacitor at a preceding stage of the inverter of the voltage comparison circuit; as well as a switch that switches a voltage input to one end of the offset capacitor to the ground voltage or the constant voltage according to a state of the signal, The voltage comparison circuit compares a value having an offset from the ground voltage with the detection voltage and outputs a comparison result.

7. The motor control circuit according to claim 4, characterized in that: The motor driving unit is an H-bridge circuit including a first upper switch, a second upper switch, a first lower switch, and a second lower switch. The motor control circuit further includes: a PWM generating unit that generates a PWM signal for switching between a state in which the first upper switch and the second upper switch in the H-bridge circuit are turned on and a state in which the first lower switch and the second lower switch are turned on, and outputs the PWM signal to the drive control unit. The current zero point detection unit generates a state notification signal notifying the state of the drive current during the current monitoring period. The state notification signal enters the detection state at the timing when the drive current becomes zero, and the state notification signal indicates the end of the detection state after one PWM cycle from the point when the drive current becomes zero.

8. The motor control circuit according to claim 7, characterized in that: During the current monitoring period, the phase adjustment unit advances the phase of the target position detection signal by a predetermined amount when the end of the detection state of the state notification signal is later than the phase switching of the reference position detection signal, and when the detection state or the end of the detection state is not output.

9. The motor control circuit according to claim 7, characterized in that: The phase adjustment unit delays the phase of the target position detection signal by a predetermined amount when the detection state of the state notification signal ends earlier than the phase switching of the reference position detection signal during the current monitoring period.

10. The motor control circuit according to claim 7, characterized in that: The phase adjustment unit causes the current zero point detection unit to monitor the drive current every predetermined number of phase switching points in the reference position detection signal, and adjusts the phase of the target position detection signal.

11. The motor control circuit according to claim 4, characterized in that: The position detection signal generating unit outputs a position detection signal consistent with the Hall signal generated by the Hall element as a reference when starting, and outputs a position detection signal whose phase is advanced or delayed by a predetermined amount from the Hall signal as a reference during stable rotation.

12. The motor control circuit according to claim 7, characterized in that: The drive control unit includes a soft switching period generation unit that adjusts a pulse width of PWM in stages when switching the drive voltage so that the switching of the drive voltage is performed as a soft switch with a gradient.

13. A motor control IC, characterized in that: The motor control circuit according to any one of claims 1 to 12 is a semiconductor integrated circuit that controls the motor drive unit.

14. A motor drive control method, providing a drive voltage to a brushless DC motor via a motor drive unit, characterized in that: The motor drive control method comprises the following steps: monitoring a voltage corresponding to a drive current flowing through a coil of the motor, and detecting a timing when the drive current reaches zero; Outputting a position detection signal that becomes a reference based on the Hall signal generated by the Hall element; adjusting the phase of the target position detection signal after the next cycle of the reference position detection signal based on the detected timing when the drive current is zero and the reference position detection signal; as well as The timing for changing the drive voltage is controlled so as to coincide with a phase switching point of the target position detection signal, and the controlled drive voltage is supplied to the motor drive unit.

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