Superconducting parameter amplifier and preparation method thereof

Abstract

The invention provides a superconducting parameter amplifier and a preparation method thereof, and the superconducting parameter amplifier comprises a Josephson junction array which is used for providing resonance nonlinearity; the ground capacitor is used for impedance matching; the linear cavity is used for phase matching; the coupling capacitor is used for coupling the linear cavity and the Josephson junction array; the first end of the Josephson junction array is connected with a signal source and used for receiving a pumping signal and an input signal, the second end of the Josephson junction array is connected with the first end of the ground capacitor and the first end of the coupling capacitor, the second end of the ground capacitor is grounded, the second end of the coupling capacitor is connected with the first end of the linear cavity, and the second end of the linear cavity is grounded. By optimizing the design and preparation process of the superconducting parameter amplifier, the linear cavity and the coupling structure are effectively improved, and the frequency response range of the superconducting parameter amplifier is greatly expanded, so that the quality of microwave quantum optics and superconducting quantum bit measurement signal processing can be effectively improved.

Description

Technical Field

[0001] The invention belongs to the field of superconducting electronics, and in particular relates to a superconducting parametric amplifier and a preparation method thereof. Background Art

[0002] Quantum computing is a new computing model that uses the principles of quantum mechanics to control quantum information units for computing. It has powerful parallel computing and simulation capabilities and has greater potential in efficiency than traditional information processing. Superconducting quantum chips are one of the physical systems with the potential to realize quantum computing. The main challenges faced by this technology route include quantum bit measurement. The superconducting parametric amplifier based on the nonlinearity of the Josephson junction is an important device in high-fidelity quantum bit reading because of its advantage of being close to the quantum limit noise level. It greatly improves the signal-to-noise ratio of the readout signal, making single-shot non-destructive readout of quantum bits possible.

[0003] However, existing superconducting parametric amplifiers have made significant progress in gain, but their frequency response range is still relatively limited, making it difficult to meet the needs of high-quality microwave quantum optics and superconducting quantum bit measurement signal processing.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a superconducting parametric amplifier and a preparation method thereof, so as to solve the problem that the frequency response range of the superconducting parametric amplifier in the prior art is relatively limited.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a superconducting parametric amplifier, which includes: a Josephson junction array for providing resonant nonlinearity; a ground capacitor for impedance matching; a linear cavity for phase matching; a coupling capacitor for coupling the linear cavity with the Josephson junction array; the first end of the Josephson junction array is connected to a signal source for receiving a pump signal and an input signal, the second end is connected to the first end of the ground capacitor and the first end of the coupling capacitor, the second end of the ground capacitor is grounded, the second end of the coupling capacitor is connected to the first end of the linear cavity, and the second end of the linear cavity is grounded.

[0007] Optionally, the Josephson junction array includes at least one Josephson junction, and the Josephson junction array provides resonant nonlinearity through Josephson junction parametric inductance.

[0008] Optionally, the ground capacitance and the Josephson junction variable inductor together constitute a characteristic impedance of a superconducting parametric amplifier for impedance matching.

[0009] Optionally, the superconducting parametric amplifier characteristic impedance satisfies the following formula:

[0010]

[0011] Among them, L l is the inductance per unit length of the Josephson junction array; C l is the capacitance per unit length of the capacitance to ground;

[0012] The above inductance per unit length L l Provided by the nonlinear inductance of the Josephson junction in the Josephson junction array, the nonlinear inductance satisfies the following formula:

[0013]

[0014] Among them, Φ0 is a single magnetic flux quantum, which is about 2.067×10 -15 Wb physical constant; I c is the critical current of the Josephson junction J; cosφ is the phase difference of the superconductor wave function on both sides of the Josephson junction;

[0015] The above capacitance per unit length C l Provided by the flat plate capacitor C in the ground capacitance, the capacitance satisfies the following formula:

[0016]

[0017] Where ε0 is the dielectric constant of vacuum; ε r is the relative dielectric constant of the dielectric insulating layer of the flat plate capacitor; S is the area of ​​the position where the upper electrode and the lower electrode of the flat plate capacitor face each other; d is the thickness of the dielectric insulating layer between the upper electrode and the lower electrode of the flat plate capacitor.

[0018] Optionally, the linear cavity includes a first capacitor and a first inductor, wherein the first end of the first capacitor and the first end of the first inductor are connected to the first end of the coupling capacitor, the second end of the first capacitor and the second end of the first inductor are connected to the ground, and the linear cavity improves the gain of the superconducting parametric amplifier through phase matching.

[0019] Optionally, the linear cavity includes one of a distributed linear cavity and a lumped linear cavity.

[0020] Optionally, the distributed linear cavity includes one of a coplanar waveguide structure, a microstrip line structure, a stripline structure and a slotted line structure.

[0021] Optionally, the superconducting parametric amplifier includes: a substrate; a lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure, wherein the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure is patterned to define a Josephson junction array and a lower electrode structure of a flat plate capacitor; a dielectric insulating layer formed on the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure, wherein the dielectric insulating layer is patterned to expose the Josephson junction array, have a through hole connected to the lower electrode structure of the flat plate capacitor, and a dielectric layer of the flat plate capacitor; a superconducting metal layer formed on the dielectric insulating layer, wherein the superconducting metal layer is patterned to form a connection structure of an upper electrode of a flat plate capacitor and a superconducting parametric amplifier.

[0022] Optionally, the material of the substrate includes one of a sapphire substrate and high-resistance silicon.

[0023] Optionally, the material of the lower superconducting layer and the upper superconducting layer in the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure includes one of superconducting niobium metal, superconducting aluminum metal and titanium nitride; the material of the insulating / metal barrier layer in the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure includes aluminum oxide and palladium-nickel alloy stack;

[0024] Optionally, the thickness of the lower superconducting layer is greater than its own magnetic field penetration depth, the thickness of the insulating / metal barrier layer is less than the coherence length of the lower superconducting layer, and the thickness of the insulating / metal barrier layer is inversely proportional to the critical current density of the Josephson junction, and the thickness of the upper superconducting layer is greater than its own magnetic field penetration depth.

[0025] Optionally, the material of the dielectric insulating layer includes one of silicon oxide, amorphous silicon and calcium fluoride; the material of the superconducting metal layer includes one of superconducting niobium metal, superconducting aluminum metal and titanium nitride.

[0026] Optionally, the superconducting parametric amplifier is used for single-shot non-destructive readout of quantum bits.

[0027] The present invention also provides a method for preparing a superconducting parametric amplifier, comprising the following steps: 1) providing a substrate; 2) preparing a lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure on the substrate; 3) etching the upper superconducting layer, the insulating / metal barrier layer and the lower superconducting layer in the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure in sequence to define a Josephson junction and a planar capacitor lower electrode structure; 4) depositing a dielectric insulating layer on the structure formed in step 3), and performing pattern etching above the Josephson junction and at a guide hole, wherein the guide hole is connected to the planar capacitor lower electrode structure; 5) growing a superconducting metal layer on the structure formed in step 4), and performing pattern etching to form a wiring superconducting metal layer, wherein the wiring superconducting metal layer includes a planar capacitor upper electrode and a connection structure of the superconducting parametric amplifier.

[0028] Optionally, step 1) further comprises the step of cleaning the substrate using a buffered hydrofluoric acid solution or a piranha solution, wherein the piranha solution comprises a mixture of concentrated sulfuric acid and hydrogen peroxide.

[0029] Optionally, the preparation method of the upper superconducting layer includes one of magnetron sputtering, thermal evaporation, electron beam evaporation and molecular beam epitaxy, and the pattern of the lower superconducting layer is defined by photolithography and inductively coupled plasma etching or ion beam etching steps; the preparation method of the insulating / metal barrier layer includes one of magnetron sputtering and plasma enhanced chemical vapor deposition, and the pattern of the insulating / metal barrier layer is defined by wet or dry etching; the preparation method of the upper superconducting layer includes one of magnetron sputtering, thermal evaporation, electron beam evaporation and molecular beam epitaxy, and the pattern of the lower superconducting layer is defined by photolithography and inductively coupled plasma etching or ion beam etching steps.

[0030] Optionally, the method for preparing the dielectric insulating layer comprises one of magnetron sputtering and plasma enhanced chemical vapor deposition, and the dielectric insulating layer is patterned by wet or dry etching.

[0031] Optionally, the preparation method of the superconducting metal layer comprises one of magnetron sputtering, thermal evaporation, electron beam evaporation, or molecular beam epitaxy, and the superconducting metal layer is patterned by photolithography and inductively coupled plasma etching or ion beam etching steps.

[0032] Optionally, one or more of steps 1) to 5) also include monitoring methods such as endpoint detection, step measurement and probe electrical testing to accurately control the etching depth and step shape indicators during the superconducting parametric amplifier preparation process to improve the consistency and reliability of the device.

[0033] As described above, the superconducting parametric amplifier and the preparation method thereof of the present invention have the following beneficial effects:

[0034] The present invention effectively improves the linear cavity and coupling structure by optimizing the design and preparation process of the superconducting parametric amplifier, greatly expanding the frequency response range of the superconducting parametric amplifier, thereby effectively improving the quality of microwave quantum optics and superconducting quantum bit measurement signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0036] Figure 1Shown is a schematic diagram of the circuit principle of a superconducting parametric amplifier according to an embodiment of the present invention.

[0037] Figure 2 Shown is a schematic diagram of the device structure of a superconducting parametric amplifier according to an embodiment of the present invention.

[0038] Figure 3 to Figure 6 Shown is a schematic structural diagram of each step of a method for preparing a superconducting parametric amplifier according to an embodiment of the present invention.

[0039] Figure 7 It shows a frequency domain gain schematic diagram of a superconducting parametric amplifier according to an embodiment of the present invention, wherein the abscissa represents the frequency of the signal and the ordinate represents the gain.

[0040] Component number description

[0041] 11 Josephson Junction Array

[0042] 12 Capacitance to ground

[0043] 13 Coupling capacitor

[0044] 14 Linear cavity

[0045] 3 Superconducting parametric amplifier

[0046] 31 Substrate

[0047] 32 Lower superconducting layer

[0048] 33 Insulation / metal barrier layer

[0049] 34 Upper superconducting layer

[0050] 35 Dielectric insulation layer

[0051] 36 Wiring superconducting metal layer

[0052] 37 Lower electrode structure

[0053] 38 Capacitor medium of flat plate capacitor

[0054] 39 Guide hole DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0057] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0058] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0059] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0060] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0061] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] like Figure 1As shown, this embodiment provides a superconducting parametric amplifier, which includes: a Josephson junction array 11, a ground capacitor 12, a linear cavity 14, and a coupling capacitor 13. The Josephson junction array 11 is used to provide resonant nonlinearity, the ground capacitor 12 is used for impedance matching, the linear cavity 14 is used for phase matching, and the coupling capacitor 13 is used to couple the linear cavity 14 with the Josephson junction array 11. The first end of the Josephson junction array 11 is connected to a signal source for receiving a pump signal and an input signal, and the second end is connected to the first end of the ground capacitor 12 and the first end of the coupling capacitor 13. The second end of the ground capacitor 12 is grounded, the second end of the coupling capacitor 13 is connected to the first end of the linear cavity 14, and the second end of the linear cavity 14 is grounded.

[0063] like Figure 1 As shown, the Josephson junction array 11 includes at least one Josephson junction J, a first end of which is connected to a signal source for receiving a pump signal and an input signal, and a second end is connected to a first end of a ground capacitor 12 and a first end of a coupling capacitor 13. The Josephson junction array 11 provides resonant nonlinearity through a Josephson junction parametric inductor.

[0064] like Figure 1 As shown, the first end of the ground capacitor 12 is connected to the Josephson junction array 11, and the second end is grounded. The ground capacitor 12 and the Josephson junction variable inductor together constitute the characteristic impedance of the superconducting parametric amplifier, which is used for impedance matching and eliminating reflection.

[0065] The characteristic impedance of the superconducting parametric amplifier satisfies the following formula:

[0066]

[0067] Among them, L l is the inductance per unit length of the Josephson junction array 11; C l is the capacitance per unit length of the ground capacitor 12.

[0068] In this embodiment, the above-mentioned inductance per unit length L l It is provided by the nonlinear inductance of the Josephson junction J in the Josephson junction array 11, and the nonlinear inductance satisfies the following formula:

[0069]

[0070] Among them, Φ0 is a single magnetic flux quantum, which is a physical constant of about 2.067×10-15Wb; I c is the critical current of the Josephson junction J; cosφ is the phase difference of the superconductor wave function on both sides of the Josephson junction.

[0071] In this embodiment, the above-mentioned capacitance per unit length C lProvided by the flat plate capacitor C in the ground capacitor 12, the capacitance satisfies the following formula:

[0072]

[0073] Among them, ε0 is the dielectric constant of vacuum, which is a physical constant of about 8.85×10-12F / m; ε r is the relative dielectric constant of the dielectric insulating layer 35; S is the area of ​​the position where the upper electrode of the flat plate capacitor and the lower electrode of the flat plate capacitor face each other; d is the thickness of the dielectric insulating layer 35 between the upper electrode of the flat plate capacitor and the lower electrode of the flat plate capacitor.

[0074] like Figure 1 As shown, the linear cavity 14 includes: a first capacitor Cr and a first inductor Lr, wherein: the first end of the first capacitor Cr is connected to the first end of the first inductor Lr and the first end of the coupling capacitor 13, and the second end of the first capacitor Cr is connected to the second end of the first inductor Lr and the ground. The linear cavity 14 improves the gain of the superconducting parametric amplifier through phase matching.

[0075] In some embodiments, the linear cavity 14 structure can be distributed or lumped.

[0076] In some embodiments, the distributed linear cavity 14 may be a coplanar waveguide, a microstrip line, a stripline, a slotted line or other structures.

[0077] like Figure 1 As shown, the first end of the coupling capacitor 13 is connected to the second end of the Josephson junction array 11 , and the second end is connected to the first end of the linear cavity 14 . The coupling capacitor 13 is used to couple the Josephson junction array 11 and the linear cavity 14 .

[0078] like Figure 2 As shown, in one embodiment, the superconducting parametric amplifier 3 includes: a substrate 31; a lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 structure, wherein the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 structure is graphically defined to define a Josephson junction array 11, a linear cavity 14 and a flat capacitor lower electrode structure 37; a dielectric insulating layer 35, formed on the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 structure, wherein the dielectric insulating layer 35 is graphically defined to expose the Josephson junction array 11, a through hole connected to the flat capacitor lower electrode structure 37 and a dielectric layer of the flat capacitor; a superconducting metal layer, formed on the dielectric insulating layer 35, wherein the superconducting metal layer is graphically defined to be a connection structure of a flat capacitor upper electrode and the superconducting parametric amplifier 3.

[0079] In one embodiment, the material of the substrate 31 includes a sapphire substrate 31 and high-resistance silicon.

[0080] In one embodiment, the materials of the upper superconducting layer 34 and the lower superconducting layer 32 in the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 structure include one of superconducting niobium metal, superconducting aluminum metal and titanium nitride; the material of the insulating / metal barrier layer 33 in the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 structure includes aluminum oxide and palladium-nickel alloy stack.

[0081] In one embodiment, the thickness of the upper superconducting layer 34 is greater than its own magnetic field penetration depth, the thickness of the insulating / metal barrier layer 33 is less than the coherence length of the upper superconducting layer 34, and the thickness of the insulating / metal barrier layer 33 is inversely proportional to the critical current density of the Josephson junction, and the thickness of the lower superconducting layer 32 is greater than its own magnetic field penetration depth.

[0082] In one embodiment, the material of the dielectric insulating layer 35 includes one of silicon oxide, amorphous silicon and calcium fluoride; the material of the superconducting metal layer includes one of superconducting niobium metal, superconducting aluminum metal and titanium nitride.

[0083] In one embodiment, the superconducting parametric amplifier 3 is used for single-shot non-destructive readout of quantum bits.

[0084] It should be noted that the Josephson junction is composed of two superconductors separated by a very thin non-superconducting layer. When there is no voltage, the current between the superconductors is called the Josephson current, and the movement of electrons through the obstacle is called the Josephson tunneling. When the current at both ends of the Josephson junction exceeds its critical current, the Josephson junction will release the single flux quantum. The critical current of the Josephson junction is determined by its area. The larger the area, the higher the critical current value. When the voltage at both ends of the Josephson junction is 0, superconducting current can exist in the junction. This is caused by the tunneling effect of the Cooper pairs in the superconductor. As long as the superconducting current is less than the critical current, the Josephson junction will always maintain the zero voltage phenomenon.

[0085] like Figure 3 to Figure 6 As shown, this embodiment also provides a method for preparing a superconducting parametric amplifier 3, and the preparation method comprises the following steps:

[0086] like Figure 3 As shown, firstly, step 1) is performed to provide a substrate 31; the material of the substrate 31 includes a sapphire substrate 31 and high-resistance silicon.

[0087] In one embodiment, step 1) further comprises the step of cleaning the substrate 31 using a buffered hydrofluoric acid solution or a piranha solution, wherein the piranha solution comprises a mixture of concentrated sulfuric acid and hydrogen peroxide.

[0088] like Figure 3As shown, step 2) is then performed to prepare a structure of a lower superconducting layer 32 - an insulating / metal barrier layer 33 - an upper superconducting layer 34 on the substrate 31 .

[0089] In one embodiment, the preparation method of the lower superconducting layer 32 includes one of magnetron sputtering, thermal evaporation, electron beam evaporation and molecular beam epitaxy, the preparation method of the insulating / metal barrier layer 33 includes one of magnetron sputtering and plasma enhanced chemical vapor deposition, and the preparation method of the upper superconducting layer 34 includes one of magnetron sputtering, thermal evaporation, electron beam evaporation and molecular beam epitaxy.

[0090] The materials of the upper superconducting layer 34 and the lower superconducting layer 32 in the structure of the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 include one of superconducting niobium metal, superconducting aluminum metal and titanium nitride; the materials of the insulating / metal barrier layer 33 in the structure of the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 include aluminum oxide and palladium nickel alloy stacking. The thickness of the lower superconducting layer 34 is greater than its own magnetic field penetration depth, the thickness of the insulating / metal barrier layer 33 is less than the coherence length of the lower superconducting layer 34, and the thickness of the insulating / metal barrier layer 33 is inversely proportional to the critical current density of the Josephson junction, and the thickness of the upper superconducting layer 32 is greater than its own magnetic field penetration depth.

[0091] like Figure 4 As shown, then step 3) is performed, the lower superconducting layer 32, the insulating / metal barrier layer 33 and the upper superconducting layer 34 in the structure of the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34 are etched in sequence, and a Josephson junction and a planar capacitor lower electrode structure 37 are defined, wherein the Josephson junction includes a three-layer structure of the lower superconducting layer 32-insulating / metal barrier layer 33-upper superconducting layer 34, and the planar capacitor lower electrode structure 37 can be a partially retained lower superconducting layer 32. The planar capacitor (C, Cr or Cc) can be used as a ground capacitor C, a first capacitor Cr or a coupling capacitor Cc of the linear cavity 14, and the corresponding capacitor function can be realized through different connection modes. In addition, the planar capacitor can be further prepared by metal / insulating medium deposition and metal / insulating medium etching processes based on the above-mentioned planar capacitor lower electrode structure 37, and the first inductor Lr of the linear cavity can be prepared simultaneously through the above-mentioned metal / insulating medium deposition and metal / insulating medium etching processes.

[0092] It should be noted that the lower superconducting layer 32 and the lower electrode structure 37 can be prepared based on the same metal layer, and the upper superconducting layer 34 and the wiring superconducting metal layer 36 can also be prepared based on the same metal layer, and are not limited to the examples listed above.

[0093] In one embodiment, the upper superconducting layer 34 can be patterned by photolithography (eg, coating photoresist and performing high-precision step-by-step exposure and development) and inductively coupled plasma etching or ion beam etching steps, as well as organic cleaning and chemical mechanical polishing.

[0094] In one embodiment, the insulating / metal barrier layer 33 may be patterned by wet or dry etching.

[0095] In one embodiment, the upper superconducting layer 34 can be patterned by photolithography (eg, coating photoresist and performing high-precision step-by-step exposure and development) and inductively coupled plasma etching or ion beam etching steps, as well as organic cleaning and chemical mechanical polishing.

[0096] like Figure 5 As shown, step 4) is then performed, a dielectric insulating layer 35 is deposited on the structure formed in step 3), and pattern etching is performed above the Josephson junction and at the guide hole 39, the guide hole 39 is exposed and used to connect the lower electrode structure 37 of the flat capacitor; the material of the dielectric insulating layer 35 includes one of silicon oxide, amorphous silicon and calcium fluoride; the material of the superconducting metal layer includes one of superconducting niobium metal, superconducting aluminum metal and titanium nitride. The dielectric insulating layer 35 located on the lower electrode structure 37 of the flat capacitor can be patterned into a capacitor dielectric 38 of the flat capacitor, or the dielectric insulating layer 35 can be completely removed and then the capacitor dielectric 38 of the flat capacitor can be re-deposited.

[0097] In one embodiment, the preparation method of the dielectric insulating layer 35 includes one of magnetron sputtering and plasma enhanced chemical vapor deposition, and the dielectric insulating layer 35 is patterned by wet or dry etching.

[0098] like Figure 6 As shown, step 5) is finally performed to grow a superconducting metal layer on the structure formed in step 4), and pattern etching is performed to form a wiring superconducting metal layer 36, wherein the wiring superconducting metal layer 36 includes the upper electrode of the planar capacitor and the connection structure of the superconducting parametric amplifier 3. The material of the wiring superconducting metal layer 36 can be superconducting niobium metal, superconducting aluminum metal or titanium nitride.

[0099] In one embodiment, the preparation method of the superconducting metal layer includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, or molecular beam epitaxy, and the superconducting metal layer is patterned by photolithography and inductively coupled plasma etching or ion beam etching steps.

[0100] In one embodiment, one or more of the above-mentioned preparation steps 1) to 5) also include monitoring means such as endpoint detection, step measurement and probe electrical testing to accurately control the etching depth and step shape indicators during the preparation process of the superconducting parametric amplifier 3 to improve the consistency and reliability of the device.

[0101] Figure 7 Schematic diagram of the frequency domain gain of the superconducting parametric amplifier 3 of this embodiment, wherein the abscissa represents the frequency of the signal and the ordinate represents the gain.

[0102] like Figure 7 As shown, the superconducting parametric amplifier 3 can achieve a gain of more than 15 dB in the frequency band of 3 GHz to 9 GHz, and a bandwidth of more than 6 GHz. The superconducting parametric amplifier 3 of the present invention can improve the quality of microwave quantum optics and superconducting quantum bit measurement signal processing.

[0103] As described above, the superconducting parametric amplifier and the preparation method thereof of the present invention have the following beneficial effects:

[0104] The present invention effectively improves the linear cavity and coupling structure by optimizing the design and preparation process of the superconducting parametric amplifier, greatly expanding the frequency response range of the superconducting parametric amplifier, thereby effectively improving the quality of microwave quantum optics and superconducting quantum bit measurement signal processing.

[0105] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0106] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A superconducting parametric amplifier, characterized in that: The superconducting parametric amplifier comprises: Josephson junction arrays to provide resonant nonlinearity; Capacitor to ground, used for impedance matching; Linear cavity for phase matching; A coupling capacitor, used for coupling the linear cavity with the Josephson junction array; The first end of the Josephson junction array is connected to a signal source for receiving a pump signal and an input signal, the second end is connected to a first end of the ground capacitor and a first end of a coupling capacitor, the second end of the ground capacitor is grounded, the second end of the coupling capacitor is connected to a first end of the linear cavity, and the second end of the linear cavity is grounded.

2. The superconducting parametric amplifier according to claim 1, characterized in that: The Josephson junction array includes at least one Josephson junction, and the Josephson junction array provides resonant nonlinearity through Josephson junction parametric inductance.

3. The superconducting parametric amplifier according to claim 2, characterized in that: The ground capacitance and the Josephson junction variable inductor together constitute the characteristic impedance of the superconducting parametric amplifier, which is used for impedance matching.

4. The superconducting parametric amplifier according to claim 3, characterized in that: The characteristic impedance of the superconducting parametric amplifier satisfies the following formula: Among them, L l is the inductance per unit length of the Josephson junction array; C l is the capacitance per unit length of the capacitance to ground; The above inductance per unit length L l Provided by the nonlinear inductance of the Josephson junction in the Josephson junction array, the nonlinear inductance satisfies the following formula: Among them, Φ0 is a single magnetic flux quantum, which is about 2.067×10 -15 Wb physical constant; I c is the critical current of the Josephson junction J; cosφ is the phase difference of the superconductor wave function on both sides of the Josephson junction; The above capacitance per unit length C l Provided by the flat plate capacitor C in the ground capacitance, the capacitance satisfies the following formula: Where ε0 is the dielectric constant of vacuum; ε r is the relative dielectric constant of the dielectric insulating layer of the flat plate capacitor; S is the area of ​​the position where the upper electrode and the lower electrode of the flat plate capacitor face each other; d is the thickness of the dielectric insulating layer between the upper electrode and the lower electrode of the flat plate capacitor.

5. The superconducting parametric amplifier according to claim 1, characterized in that: The linear cavity includes a first capacitor and a first inductor, wherein the first end of the first capacitor and the first end of the first inductor are connected to the first end of the coupling capacitor, the second end of the first capacitor and the second end of the first inductor are connected to the ground, and the linear cavity improves the gain of the superconducting parametric amplifier through phase matching.

6. The superconducting parametric amplifier according to claim 1, characterized in that: The linear cavity includes one of a distributed linear cavity and a lumped linear cavity.

7. The superconducting parametric amplifier according to claim 6, characterized in that: The distributed linear cavity includes one of a coplanar waveguide structure, a microstrip line structure, a stripline structure and a slotted line structure.

8. The superconducting parametric amplifier according to claim 1, characterized in that: The superconducting parametric amplifier comprises: substrate; A lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure, wherein the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure is graphically defined to form a Josephson junction array and a planar capacitor lower electrode structure; A dielectric insulating layer is formed on the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure, wherein the dielectric insulating layer is patterned to expose the Josephson junction array, a through hole connected to the lower electrode structure of the flat capacitor, and a dielectric layer of the flat capacitor; A superconducting metal layer is formed on the dielectric insulating layer, and the superconducting metal layer is patterned into a connection structure of an upper electrode of a planar capacitor and a superconducting parametric amplifier.

9. The superconducting parametric amplifier according to claim 8, characterized in that: The material of the substrate includes one of a sapphire substrate and high-resistance silicon.

10. The superconducting parametric amplifier according to claim 8, characterized in that: The material of the lower superconducting layer and the upper superconducting layer in the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure comprises one of superconducting niobium metal, superconducting aluminum metal and titanium nitride; The material of the insulating / metal barrier layer in the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure includes aluminum oxide and palladium-nickel alloy stacking.

11. The superconducting parametric amplifier according to claim 8, characterized in that: The thickness of the lower superconducting layer is greater than its own magnetic field penetration depth, the thickness of the insulating / metal barrier layer is less than the coherence length of the lower superconducting layer, and the thickness of the insulating / metal barrier layer is inversely proportional to the critical current density of the Josephson junction, and the thickness of the upper superconducting layer is greater than its own magnetic field penetration depth.

12. The superconducting parametric amplifier according to claim 8, characterized in that: The material of the dielectric insulating layer includes one of silicon oxide, amorphous silicon and calcium fluoride; the material of the superconducting metal layer includes one of superconducting niobium metal, superconducting aluminum metal and titanium nitride.

13. The superconducting parametric amplifier according to claim 1, characterized in that: The superconducting parametric amplifier is used for single-shot non-destructive readout of quantum bits.

14. A method for preparing a superconducting parametric amplifier according to any one of claims 1 to 13, characterized in that: Includes steps: 1) providing a substrate; 2) preparing a lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure on the substrate; 3) etching the upper superconducting layer, the insulating / metal barrier layer and the lower superconducting layer in the lower superconducting layer-insulating / metal barrier layer-upper superconducting layer structure in sequence to define a Josephson junction and a lower electrode structure of a planar capacitor; 4) depositing a dielectric insulating layer on the structure formed in step 3), and performing pattern etching above the Josephson junction and at the guide hole, wherein the guide hole is connected to the lower electrode structure of the planar capacitor; 5) growing a superconducting metal layer on the structure formed in step 4), and performing pattern etching to form a wiring superconducting metal layer, wherein the wiring superconducting metal layer includes the upper electrode of the planar capacitor and the connection structure of the superconducting parametric amplifier.

15. The method for preparing a superconducting parametric amplifier according to claim 14, characterized in that: Step 1) also includes the step of cleaning the substrate using a buffered hydrofluoric acid solution or a piranha solution, wherein the piranha solution includes a mixture of concentrated sulfuric acid and hydrogen peroxide.

16. The method for preparing a superconducting parametric amplifier according to claim 14, characterized in that: The preparation method of the upper superconducting layer includes one of magnetron sputtering, thermal evaporation, electron beam evaporation and molecular beam epitaxy, and the pattern of the lower superconducting layer is defined by photolithography and inductively coupled plasma etching or ion beam etching steps; The preparation method of the insulating / metal barrier layer includes one of magnetron sputtering and plasma enhanced chemical vapor deposition, and the insulating / metal barrier layer is patterned by wet or dry etching; The preparation method of the upper superconducting layer includes one of magnetron sputtering, thermal evaporation, electron beam evaporation and molecular beam epitaxy, and the pattern of the lower superconducting layer is defined by photolithography and inductively coupled plasma etching or ion beam etching steps.

17. The method for preparing a superconducting parametric amplifier according to claim 14, characterized in that: The preparation method of the dielectric insulating layer includes one of magnetron sputtering and plasma enhanced chemical vapor deposition, and the dielectric insulating layer is patterned by wet or dry etching.

18. The method for preparing a superconducting parametric amplifier according to claim 14, characterized in that: The preparation method of the superconducting metal layer comprises one of magnetron sputtering, thermal evaporation, electron beam evaporation or molecular beam epitaxy, and the superconducting metal layer is patterned by photolithography and inductively coupled plasma etching or ion beam etching.

19. The method for preparing a superconducting parametric amplifier according to claim 14, characterized in that: One or more of steps 1) to 5) also includes monitoring means such as endpoint detection, step measurement and probe electrical testing to accurately control the etching depth and step shape indicators during the superconducting parametric amplifier preparation process to improve the consistency and reliability of the device.

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