Digital-to-analog converter and calibration method and calibration system thereof

Abstract

The invention discloses a digital-to-analog converter and a calibration method and a calibration system thereof. The digital-to-analog converter comprises: a DAC circuit for providing an analog output current according to a digital input signal; the analog signal circuit is connected with the DAC circuit and used for converting analog output current into analog output voltage, and the digital-to-analog converter is further used for providing calibration current for a connection path of the DAC circuit and the analog signal circuit through the analog calibration circuit under the condition that quantization errors exist in the analog output voltage. And carrying out arithmetic logic operation on the error calibration coefficient and the digital input signal to adjust the analog output current of the DAC circuit. According to the digital-to-analog converter, the quantization error of the digital-to-analog converter is calibrated by adopting a mode of combining digital domain calibration in the analog calibration circuit and the DAC circuit, a large number of switches and resistors do not need to be arranged in the analog calibration circuit, and the area and the cost of the circuit are reduced while the circuit precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a digital-to-analog converter and a calibration method and a calibration system thereof. Background Art

[0002] Digital-to-analog converters (DACs) are key components that convert digital signals into analog signals and are widely used in communications, audio processing, measuring instruments, and other fields. Current-mode core DACs are the first choice for many high-performance applications due to their high precision and high speed. However, current-mode core DACs usually output in the form of current, and require an inverting amplifier to convert the current signal into a voltage signal for subsequent processing and use.

[0003] In practical applications, the performance of the reverse amplifier has an important impact on the overall output accuracy of the digital-to-analog converter. During the chip manufacturing process, due to process limitations and component matching errors, the output voltage of the digital-to-analog converter will produce various forms of quantization errors. Among them, zero-point error and gain error are the most representative and most important errors.

[0004] Zero-point error means that ideally, when the digital input signal is zero, the output voltage of the digital-to-analog converter should be zero. However, due to component mismatch and other process errors, the actual output voltage may deviate from the zero value, resulting in zero-point error. This error will affect the accuracy and linearity of the digital-to-analog converter, and thus affect the performance of the entire system.

[0005] Gain error means that ideally, the output voltage of the DAC should be proportional to the digital input signal. However, due to component matching errors and other process factors, the actual output voltage gain may deviate from the ideal value, resulting in gain error. This error will affect the output range and linearity of the DAC, and thus affect the overall performance of the system.

[0006] In order to reduce zero-point error and gain error, various compensation and calibration measures are usually required during the design and manufacturing process. For example, these errors can be reduced by adjusting circuit parameters, adding calibration circuits, or using higher-precision components. In addition, during use, the output voltage can also be corrected by software calibration to improve the accuracy and performance of the digital-to-analog converter.

[0007] However, the traditional calibration method has the following disadvantages: first, the number of calibration circuits is large, and as the calibration accuracy increases, the area of ​​the calibration circuit tends to increase exponentially; second, the traditional calibration method usually completes the calibration and solidifies the circuit before the chip leaves the factory. However, since the physical quantity will drift as the circuit ages, the error will become larger over time, and it is impossible to readjust or reconfigure it more flexibly at the system level. Summary of the invention

[0008] In view of the above problems, an object of the present invention is to provide a digital-to-analog converter and a calibration method and system thereof, which can improve circuit accuracy while reducing circuit area and cost.

[0009] According to one aspect of the present invention, there is provided a digital-to-analog converter, comprising: a DAC circuit, for providing an analog output current according to a digital input signal; and an analog signal circuit connected to the DAC circuit, for converting the analog output current into an analog output voltage, wherein the digital-to-analog converter is further used to provide a calibration current to a connection path between the DAC circuit and the analog signal circuit for coarse adjustment through an analog calibration circuit when there is a quantization error in the analog output voltage, and to perform arithmetic logic operations on an error calibration coefficient and the digital input signal to perform fine adjustment in the digital domain of the DAC circuit.

[0010] Optionally, the analog calibration circuit includes a first current branch and a second current branch, wherein the calibration current provided by the first current branch is used to increase the output current of the DAC circuit, and the calibration current provided by the second current branch is used to reduce the output current of the DAC circuit.

[0011] Optionally, the analog signal circuit includes an inverting amplifier.

[0012] Optionally, the analog signal circuit includes: a first resistor, whose first end is connected to the output of the DAC circuit; an operational amplifier, whose inverting input is connected to the second end of the first resistor, whose non-inverting input is connected to ground, and whose output is used to provide the analog output voltage; and a second resistor, connected between the inverting input and output of the operational amplifier.

[0013] Optionally, the first current branch includes a first switch and a third resistor connected in series between a first reference voltage and the inverting input terminal of the operational amplifier, and the second current branch includes a second switch and a fourth resistor connected in series between a second reference voltage and the inverting input terminal of the operational amplifier, wherein the first switch and the second switch are not turned on at the same time, and the turning on and off of the first switch and the second switch are controlled by the offset direction of the quantization error.

[0014] Optionally, when the offset direction of the quantization error is negative, the first switch is turned on, and when the offset direction of the quantization error is positive, the second switch is turned on.

[0015] Optionally, the third resistor and the fourth resistor have the same resistance value.

[0016] Optionally, the first reference voltage and the second reference voltage are provided by a reference voltage source of the DAC circuit.

[0017] Optionally, the error calibration coefficient includes a zero-point error coefficient and a gain error coefficient, and the arithmetic logic operation includes adding the zero-point error coefficient to the digital input signal, or multiplying the digital input signal by the gain error coefficient and then adding the resultant to the digital input signal.

[0018] Optionally, when the offset direction of the quantization error is negative, the zero-point error coefficient or the gain error coefficient is a negative value; when the offset direction of the quantization error is positive, the zero-point error coefficient or the gain error coefficient is a positive value.

[0019] According to another aspect of the present invention, a calibration method for a digital-to-analog converter is provided, comprising: in the case where a quantization error exists in the analog output voltage of the digital-to-analog converter, providing a calibration current to a connection path between a DAC circuit and an analog signal circuit through an analog calibration circuit; and determining an error calibration coefficient according to the analog output voltage, and applying the error calibration coefficient to a digital input signal of the DAC circuit to perform arithmetic and logical operations to perform fine-tuning in the digital domain of the DAC circuit.

[0020] According to another aspect of the present invention, a calibration system is provided, comprising: the above-mentioned digital-to-analog converter; a test circuit for testing the type and offset direction of the quantization error of the analog output voltage of the digital-to-analog converter, and generating an error calibration coefficient and a control signal of the analog calibration circuit according to the test result; and a digital calibration circuit for performing arithmetic logic operations on the error calibration coefficient and the digital input signal to adjust the analog output current of the DAC circuit.

[0021] In summary, the digital-to-analog converter provided in the embodiment of the present invention adopts a combination of an analog calibration circuit and a digital domain calibration inside a DAC circuit to calibrate the quantization error of the digital-to-analog converter. First, a calibration current is provided on the signal chain of the digital-to-analog converter through the analog calibration circuit to determine the direction and maximum range of the quantization calibration. Then, an error calibration coefficient is introduced on the digital input signal to perform fine-tuning in the digital domain. Therefore, there is no need to arrange a large number of switches and resistors in the analog calibration circuit, which is beneficial to reducing the area and cost of the circuit while improving the circuit accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0023] Figure 1 A schematic diagram of the structure of a traditional digital-to-analog converter is shown.

[0024] Figure 2 A schematic diagram showing the structure of a traditional digital-to-analog converter when a zero-point error occurs.

[0025] Figure 3 A schematic structural diagram showing a conventional calibration method for a digital-to-analog converter is shown.

[0026] Figure 4 A schematic structural diagram of a calibration system according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0027] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0028] Many specific details of the present invention are described below, such as component structures, materials, dimensions, processing techniques and technologies, in order to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0029] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuit, a programmable circuit, a state machine circuit and / or an element that can store instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0030] Figure 1 FIG. 2 shows a schematic diagram of the structure of a traditional digital-to-analog converter. Figure 1As shown, in a conventional digital-to-analog converter 100, a DAC circuit 110 obtains an analog output current Iout according to a digital input signal code, and then converts it into an analog output voltage Vout through an operational amplifier AMP connected in the form of an inverting amplifier. In the process of the DAC circuit 110 generating the analog output current Iout and converting the analog output current Iout into the analog output voltage Vout, due to the component matching error in the chip processing process, the analog output voltage Vout will eventually generate various forms of quantization errors, among which zero-point error and gain error are the most representative. It should be noted that since the DAC circuit 110 can be implemented through different topological architectures, this article does not discuss the specific topological architecture of the DAC circuit 110 in depth, but it can be determined that for any DAC circuit of any architecture, due to the non-matching characteristics within the circuit, or even due to the non-ideal effect of the circuit that provides the reference voltage for the DAC circuit, it is impossible to avoid generating a zero-point error or a gain error at the output of the DAC circuit.

[0031] like Figure 2 The schematic diagram of the structure of the traditional digital-to-analog converter when a zero-point error occurs is shown. Assuming that the equivalent input offset voltage of the operational amplifier AMP is VOFF, when the analog output current Iout is zero, the analog output voltage Vout is equal to VOFF. It can be seen that compared with the ideal zero point, Figure 2 The zero-point error of the analog output voltage Vout is the input offset voltage VOFF. The gain error of the analog output voltage Vout is caused by the mismatch between the resistors R2 and R1. Assuming that the resistor R1 is equal to the resistor R2 in an ideal situation, the gain of the operational amplifier AMP is -(R1+R2) / R1=-2. However, when there is a mismatch between the resistors R1 and R2, the resistor R2=R1*(1+Δ), that is, the gain of the operational amplifier AMP becomes -2*(1+Δ), thereby introducing a gain error of Δ in the analog output voltage Vout.

[0032] Figure 3 The schematic diagram of the structure of the traditional calibration method of the digital-to-analog converter is shown. According to the above description, the zero-point error and gain error of the existing digital-to-analog converter are caused by the non-ideal effect of the circuit, so the traditional calibration method is also completed in the form of an analog circuit. In general, the traditional calibration method will mostly choose to eliminate the error at the location where the error of the digital-to-analog converter occurs, or select a location on the entire analog signal transmission path for unified error calibration. Figure 3 As shown, the conventional calibration method makes the resistance value of the resistor R2 adjustable by designing a resistor trimming network composed of a resistor and a switch, and then eliminates the gain error of the circuit by using the resistor trimming network.

[0033] However, in certain specific scenarios, such as when the current flowing through the resistor is large, the size of the switch required in the resistor trimming network will be very large, which will increase the area and cost of the circuit. Considering this situation, the prior art also has a method of introducing calibration at the reference voltage VREF of the DAC circuit 110, such as Figure 3 As shown, the output current of the DAC circuit 110 Wherein R is a specific design parameter of the DAC circuit 110. In another calibration method in the prior art, the analog output current Iout is adjusted by adjusting the reference voltage VREF of the DAC circuit 110, and then the zero point error and gain error in the circuit are compensated.

[0034] The advantage of the calibration method of the prior art is that, since the calibration circuit also adopts the form of an analog circuit and has the same physical dimension as the form in which the error occurs in the circuit, the design and implementation of the calibration circuit is simple, and since the size of the physical quantity can be freely selected, a flexible calibration step can be provided in the circuit. However, the calibration method of the prior art will cause the area of ​​the digital-to-analog converter to increase, and its area will increase exponentially with the increase of the calibration accuracy. In addition, the calibration method of the prior art often requires the calibration to be completed and the circuit to be solidified before the chip leaves the factory. Since the physical quantity will drift as the circuit ages, the quantization error of the digital-to-analog converter will increase again with the increase of time, and the existing digital-to-analog converter cannot be readjusted or flexibly reconfigured at the system level, which greatly limits the service life and accuracy of the digital-to-analog converter.

[0035] Figure 4 FIG. 2 is a schematic diagram showing the structure of a calibration system according to an embodiment of the present invention. Figure 4 As shown, the calibration system includes a digital-to-analog converter 200, a test circuit 310 and a digital calibration circuit 320. Further, the digital-to-analog converter 200 includes a DAC circuit 210, an analog signal circuit 220 and an analog calibration circuit 230. Among them, the DAC circuit 210 is used to provide an analog output current Iout according to a digital input signal code. The analog signal circuit 220 is used to convert the analog output current Iout into an analog output voltage Vout. The analog calibration circuit 230 is connected to the signal chain between the DAC circuit 210 and the analog signal circuit 220, and is used to provide a calibration current to the signal path between the two when there is a quantization error in the analog output voltage Vout, so as to compensate for the error of the entire analog link including the DAC circuit. It can be understood that the DAC circuit 210, the analog signal circuit 220 and the analog calibration circuit 230 are integrated on the same chip.

[0036] Further, the test circuit 310 is used to receive the output current Iout of the DAC circuit 210 and / or the output voltage Vout of the subsequent analog signal circuit 220, and then test whether there is a quantization error on the entire analog link including the DAC circuit 210 according to the obtained output current Iout and / or output voltage Vout, and determine the type and offset direction of the quantization error when a quantization error occurs. The digital calibration circuit 320 is connected to the test circuit 310, and the test circuit 310 is also used to provide an error calibration coefficient to the digital calibration circuit 320 according to the test result when a quantization error occurs on the signal link of the digital-to-analog converter 200. The digital calibration circuit 320 performs an arithmetic logic operation on the error calibration coefficient and the digital input signal code, and then provides a digital signal codex to the DAC circuit 210, and adjusts the analog output current Iout of the DAC circuit 210 through the signal codex, and then compensates for the error of the DAC circuit 210 or compensates for the error generated by the DAC circuit 210 and one or more subsequent analog signal circuits 220.

[0037] Furthermore, the test circuit 310 may also include a memory, and a mapping table of the offset error of the output voltage Vout and the error calibration coefficient is stored in the memory. When a quantization error occurs in the entire analog link of the DAC circuit 210, the test circuit 310 determines the specific value of the error calibration coefficient according to the output voltage Vout and the mapping table. Furthermore, the memory may be configured to be stored and programmable by a user, so that the user can adjust the error calibration coefficient of the digital-to-analog converter 200.

[0038] Furthermore, the error calibration coefficient includes a zero-point error coefficient EZ and / or a gain error coefficient EG, and the digital calibration circuit 320 is used to add the zero-point error coefficient EZ to the digital input signal code, or to multiply the digital input signal code by the gain error coefficient EG and then add the resultant to the digital input signal code.

[0039] Furthermore, in the digital-to-analog converter 200 of the present embodiment, the DAC circuit 210 includes two reference terminals, one of which is used to connect to a reference voltage source VREFP, and the other of which is used to connect to a reference voltage source VREFM. The reference voltage source VREFP is used to provide a "positive reference voltage", and the reference voltage source VREFM is used to provide a "negative reference voltage". The analog calibration circuit 230 is also used to obtain the calibration current according to one of the reference voltage VREFP and the reference voltage VREFM when a quantization error occurs in the analog output voltage Vout.

[0040] It should be noted that the present invention does not limit the specific topology of the DAC circuit 210 , and those skilled in the art can select a current-mode DAC with any topology to implement the present invention according to specific circumstances.

[0041] Further, the analog signal circuit 220 of the present embodiment includes an inverting amplifier for converting an analog current into an analog voltage. Specifically, the analog signal circuit 220 includes a resistor R1, a resistor R2, and an operational amplifier AMP. The first end of the resistor R1 is connected to the output of the DAC circuit 210, the second end of the resistor R1 is connected to the inverting input terminal of the operational amplifier AMP, the non-inverting input terminal of the operational amplifier AMP is connected to the ground, the voltage source VOFF represents the input offset voltage of the operational amplifier AMP, the output terminal of the operational amplifier AMP is used to provide the analog output voltage Vout, and the resistor R2 is connected between the inverting input terminal and the output terminal of the operational amplifier AMP.

[0042] Further, the analog calibration circuit 230 includes a first current branch connected to the reference voltage VREFP, and a second current branch connected to the reference voltage VREFM, wherein the first current branch is used to provide a calibration current to the output of the DAC circuit 210 according to the reference voltage VREFP to increase the output current of the DAC circuit, and the second current branch is used to provide a calibration current to the output of the DAC circuit 210 according to the reference voltage VREFM to reduce the output current of the DAC circuit. Further, the first current branch includes a switch S1 and a resistor RA connected in series between the reference voltage VREFP and the inverting input terminal of the operational amplifier AMP, and the second current branch includes a switch S2 and a resistor RB connected in series between the reference voltage VREFM and the inverting input terminal of the operational amplifier AMP. For example, the resistance values ​​of the resistor RA and the resistor RB are equal, and the switch S1 and the switch S2 are not turned on at the same time, and the switch S1 and the switch S2 are controlled by the offset direction of the quantization error in the analog output voltage Vout. Furthermore, the test circuit 310 may also generate a switch signal K1 and a switch signal K2 according to the measured offset direction of the quantization error, and the switch signal K1 and the switch signal K2 are used to control the on and off of the switch S1 and the switch S2 respectively.

[0043] Furthermore, the digital calibration circuit 320 may also include an operation circuit, which may include an adder and a multiplier, wherein the adder is used to add the zero error coefficient EZ to the digital input signal code, thereby obtaining a signal codex. The multiplier may be used to multiply the digital input signal code by the gain error coefficient EG, and then add the multiplier to the digital input signal code through the adder, thereby obtaining the signal codex.

[0044] Combine the following Figure 4 The calibration method of the digital-to-analog converter according to the embodiment of the present invention is described in detail. Figure 4 As shown, when no quantization error occurs in the digital-to-analog converter 200, the switches S1 and S2 are both in the off state, so the output expression of the DAC circuit 210 is:

[0045]

[0046] Wherein, R represents the specific design index parameter in the DAC circuit 210. When a zero-point error occurs in the digital-to-analog converter 200, the test circuit 310 provides the zero-point error coefficient EZ to the digital calibration circuit 320, and determines the value of the zero-point error coefficient EZ and the conduction status of the switches S1 and S2 according to the offset direction of the zero-point error. For example, when the offset direction of the zero-point error is "negative", the value of the zero-point error coefficient EZ is negative (that is, the zero-point error coefficient EZ is less than zero); when the offset direction of the zero-point error is "positive", the value of the zero-point error coefficient EZ is positive (that is, the zero-point error coefficient EZ is greater than zero). It should be noted that the above-mentioned offset directions of "negative" and "positive" are relative, that is, when the analog output current Iout is zero, the analog output voltage Vout should also be zero under normal circumstances, and when the analog output voltage Vout is greater than zero, it can be considered that the offset direction of the zero-point error in the circuit is "positive"; and when the analog output voltage Vout is less than zero, it can be considered that the offset direction of the zero-point error in the circuit is "negative".

[0047] Further, if the offset direction of the zero-point error is "negative", the switch S1 is controlled to be turned on and the switch S2 is turned off. At this time, the calibration current VREFP / RA is provided to the output of the DAC circuit 210 through the first current branch to perform coarse adjustment on the DAC circuit 210 and the entire analog link. At this time, a zero-point correction range of VREFP / RA is equivalently introduced into the circuit, and then the digital input signal code is summed with the negative zero-point error coefficient EZ through the digital calibration circuit 320 to perform fine adjustment in the digital domain of the DAC circuit 210, wherein the value of the zero-point error coefficient EZ can be calculated by testing the chip after actual processing and then making the weighted output of the DAC circuit 210:

[0048]

[0049] As can be seen from the above formula, the analog output current Iout will be converted from current to voltage after passing through the inverting amplifier composed of the resistors R1 and R2 and the operational amplifier AMP, and the polarity of the analog output voltage Vout is opposite to the polarity of the analog output current Iout. Therefore, during the test, if a "negative" zero-point error appears on the analog output voltage Vout, it is necessary to introduce a "positive" trimming amount on the analog output current Iout to offset the negative zero-point error on the analog output voltage Vout. Therefore, the calibration method of this embodiment generally includes two processes. First, a maximum positive trimming range is introduced on the analog output current Iout of the DAC circuit 210 by the calibration current VREFP / RA for coarse adjustment, and then the zero-point error coefficient EZ digital input signal code is adjusted, so that a number less than the absolute value of VREFP is subtracted in the digital domain of the DAC circuit 210, so that the digital domain of the DAC circuit 210 is fine-tuned, and then a specific and accurate trimming value is obtained, and the accuracy of the trimming value is the same as the accuracy of the DAC circuit 210.

[0050] Similarly, when the offset direction of the zero-point error is "positive", the switch S2 is controlled to be turned on and the switch S1 is turned off. At this time, a maximum negative adjustment range is introduced into the circuit through the calibration current VREFM / RB, and then the digital input signal code is summed with the positive zero-point error coefficient EZ through the digital calibration circuit 320, so that a number smaller than the absolute value of VREFM is subtracted in the digital domain of the DAC circuit 210 to obtain a specific and accurate adjustment value, and then the weighted output of the DAC circuit 210 is obtained as follows:

[0051]

[0052] According to equations (2) and (3), the actual output of the DAC circuit 210 during the trimming process is:

[0053]

[0054] The relationship between the analog output voltage Vout, the analog output current Iout and the output voltage VDAC of the DAC circuit can be obtained by using Kirchhoff's current formula:

[0055] Iout×R1=VDAC-VOFF (5)

[0056] (VDAC-VOFF) / R1=(Vout-VOFF) / R2 (6)

[0057] By combining equations (4) to (6), the mapping relationship between the analog output voltage Vout and the zero-point error coefficient EZ can be obtained. The specific value of the zero-point error coefficient EZ can be obtained according to the mapping relationship, and then the zero-point error of the digital-to-analog converter 200 can be fine-tuned in the digital domain.

[0058] Similarly, when a gain error occurs in the digital-to-analog converter 200, the test circuit 310 provides the gain error coefficient EG to the digital calibration circuit 320, and determines the value of the gain error coefficient EG and the on and off of switches S1 and S2 according to the offset direction of the gain error. For example, when the offset direction of the gain error is "negative", the value of the gain error coefficient EG is negative (that is, the gain error coefficient EG is less than zero); when the offset direction of the gain error is "positive", the value of the gain error coefficient EG is positive (that is, the gain error coefficient EG is greater than zero). If the offset direction of the gain error is "negative", the switch S1 is controlled to be turned on and the switch S2 is turned off. At this time, the circuit is equivalent to introducing a gain correction range with a current size of VREFP / RA for coarse adjustment, and then the gain error coefficient EG is introduced into the digital input signal code as a multiplication factor through the digital calibration circuit 320 to perform fine adjustment in the digital domain of the DAC circuit 210, and finally the weighted output of DAC210 is obtained as:

[0059]

[0060] When the gain error is offset in the "positive" direction, switch S2 is turned on and switch S1 is turned off. At this time, the weighted output of DAC210 becomes:

[0061]

[0062] According to the above description, it can be understood that the quantization error of the digital-to-analog converter is calibrated by combining the sampling analog calibration and the digital domain calibration of the digital-to-analog converter in the embodiment of the present invention. Compared with the traditional analog calibration scheme, there is no need to arrange a large number of switches and resistors in the circuit, which can reduce the cost and area of ​​the circuit. In addition, since the zero point and full-scale voltage of the physical structure of the DAC circuit are fixed, the traditional digital calibration scheme simply performs calibration by changing the mapping relationship of the digital input signal code, which will lose part of the output range. The calibration method of the embodiment of the present invention is not limited by the physical structure of the DAC circuit, so the above-mentioned problem will not exist.

[0063] In summary, the digital-to-analog converter provided in the embodiment of the present invention adopts a combination of an analog calibration circuit and a digital domain calibration inside a DAC circuit to calibrate the quantization error of the digital-to-analog converter. First, a calibration current is provided on the signal chain of the digital-to-analog converter through the analog calibration circuit to determine the direction and maximum range of the quantization calibration. Then, an error calibration coefficient is introduced on the digital input signal to perform fine-tuning in the digital domain. Therefore, there is no need to arrange a large number of switches and resistors in the analog calibration circuit, which is beneficial to reducing the area and cost of the circuit while improving the circuit accuracy.

[0064] In addition, since the DAC circuit can perform precise numerical calculations and controls to implement complex calibration algorithms and compensation strategies, the digital-to-analog converter of the present invention can utilize high-resolution numerical calculations to refine the calibration process.

[0065] In addition, the calibration method of the present invention does not require fixed error parameters, and the programmability of the digital domain also enables the calibration process to be adjusted and optimized as needed. Therefore, the digital-to-analog converter of the present invention can easily implement different calibration algorithms and strategies during subsequent use without changing the hardware, and has higher flexibility.

[0066] It will be understood by those skilled in the art that the words "during", "when" and "when..." used in this article in connection with the operation of the circuit are not strict terms indicating an action that occurs immediately when the start-up action begins, but that there may be some small but reasonable delay or delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (for semiconductor doping concentrations, at least twenty percent (20%)) is a reasonable deviation from the accurate ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0067] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0068] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A digital-to-analog converter, comprising: a DAC circuit for providing an analog output current according to a digital input signal; as well as an analog signal circuit connected to the DAC circuit, for converting the analog output current into an analog output voltage, In which, the digital-to-analog converter is also used to provide a calibration current to the connection path between the DAC circuit and the analog signal circuit for coarse adjustment through an analog calibration circuit when there is a quantization error in the analog output voltage, and to perform arithmetic logic operations on the error calibration coefficient and the digital input signal to perform fine adjustment in the digital domain of the DAC circuit.

2. The digital-to-analog converter according to claim 1, wherein: The analog calibration circuit includes a first current branch and a second current branch. The calibration current provided by the first current branch is used to increase the output current of the DAC circuit, and the calibration current provided by the second current branch is used to reduce the output current of the DAC circuit.

3. The digital-to-analog converter according to claim 2, wherein: The analog signal circuit includes an inverting amplifier.

4. The digital-to-analog converter according to claim 3, wherein: The analog signal circuit comprises: a first resistor, a first end of which is connected to the output of the DAC circuit; an operational amplifier, whose inverting input terminal is connected to the second end of the first resistor, whose non-inverting input terminal is connected to ground, and whose output terminal is used to provide the analog output voltage; and The second resistor is connected between the inverting input terminal and the output terminal of the operational amplifier.

5. The digital-to-analog converter according to claim 4, wherein: The first current branch includes a first switch and a third resistor connected in series between a first reference voltage and an inverting input terminal of the operational amplifier. The second current branch includes a second switch and a fourth resistor connected in series between a second reference voltage and the inverting input terminal of the operational amplifier. The first switch and the second switch are not turned on at the same time, and the turning on and off of the first switch and the second switch are controlled by the offset direction of the quantization error.

6. The digital-to-analog converter according to claim 5, wherein: When the offset direction of the quantization error is negative, the first switch is turned on, and when the offset direction of the quantization error is positive, the second switch is turned on.

7. The digital-to-analog converter according to claim 5, wherein: The third resistor and the fourth resistor have the same resistance value.

8. The digital-to-analog converter according to claim 5, wherein: The first reference voltage and the second reference voltage are provided by a reference voltage source of the DAC circuit.

9. The digital-to-analog converter according to claim 6, wherein: The error calibration coefficient includes a zero point error coefficient and a gain error coefficient. The arithmetic logic operation includes adding the zero-point error coefficient to the digital input signal, or multiplying the digital input signal by the gain error coefficient and then adding the multiplied value to the digital input signal.

10. The digital-to-analog converter according to claim 9, wherein: When the offset direction of the quantization error is negative, the zero-point error coefficient or the gain error coefficient is a negative value; when the offset direction of the quantization error is positive, the zero-point error coefficient or the gain error coefficient is a positive value.

11. A method for calibrating a digital-to-analog converter according to any one of claims 1 to 10, comprising: In the case where there is a quantization error in the analog output voltage of the digital-to-analog converter, providing a calibration current to a connection path between the DAC circuit and the analog signal circuit through an analog calibration circuit; as well as An error calibration coefficient is determined according to the analog output voltage, and the error calibration coefficient is applied to a digital input signal of the DAC circuit to perform an arithmetic logic operation to perform fine adjustment in the digital domain of the DAC circuit.

12. A calibration system comprising: The digital-to-analog converter according to any one of claims 1 to 10; A test circuit, used for testing the type and offset direction of the quantization error of the analog output voltage of the digital-to-analog converter, and generating an error calibration coefficient and a control signal of the analog calibration circuit according to the test result; as well as The digital calibration circuit is used to perform an arithmetic logic operation on the error calibration coefficient and the digital input signal to adjust the analog output current of the DAC circuit.

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