Analog-to-digital converter, touch chip and electronic equipment
By introducing residual sampling and summing circuits into SAR ADC, the low conversion accuracy problem caused by noise and capacitive array mismatch is solved, and efficient noise shaping and accuracy improvement is achieved. 7 bits in a single sampling scheme and 12 bits in oversampling Conversion accuracy.
Patent Information
- Application Number
- CN202310835395.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-07
- Publication Date
- 2025-01-07
AI Technical Summary
Existing SAR ADCs have poor conversion accuracy due to mismatch between noise and capacitive arrays.
An analog-to-digital converter is designed to add residual sampling and summing circuits, and noise shaping is realized by successively approximating the register logic circuit and digital-to-analog conversion circuit. The residuals of the previous quantization result are quantized by subtracting the current input, and In the residual summing process, severe residual attenuation is avoided, and the conversion accuracy is improved.
The first-order noise shaping effect is achieved, which improves the conversion accuracy of the ADC. It can reach 7 bits under a single sampling solution, and can reach 12 bits under oversampling. The circuit is simple, avoiding the use of additional amplifiers.
Smart Images
Figure CN119276265A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of touch control technology, and in particular to an analog-to-digital converter, a touch control chip and an electronic device. Background Art
[0002] The analog-to-digital converter (ADC) is a circuit that is often used when processing, analyzing and applying analog signals such as light, electricity and magnetism. It can convert these analog signals into digital signals, which restricts the performance of the entire signal processing process. Depending on the application scenario, there are different requirements for the performance of the ADC. Among them, the ADC suitable for touch chips is usually a successive approximation register analog-to-digital converter (SAR ADC) with medium-to-high precision (about 12 bits), medium speed (about 1MSPS), low power consumption and small area.
[0003] Please refer to Figure 1 The traditional SAR ADC mainly includes a capacitive digital-to-analog conversion circuit CDAC, a comparator comp and a successive approximation register logic circuit SAR LOGIC, wherein CDAC converts the analog input signal Vin into a residual voltage Vp, and sends the residual voltage Vp to the comparator comp for comparison. The comparison result of the comparator comp is sent to the SAR LOGIC. The SAR LOGIC obtains a quantization result of corresponding accuracy (bit) according to the output of the comparator comp, and iterates accordingly.
[0004] However, the existing SAR ADC is prone to generating noise of the comparator comp and mismatch of the capacitor array in the CDAC, thus resulting in low conversion accuracy of the SAR ADC. Summary of the invention
[0005] An object of the present invention is to provide an analog-to-digital converter that can realize the function of noise shaping and improve the conversion accuracy of SARADC.
[0006] Another object of the present invention is to provide a touch control chip and an electronic device, which improve performance by applying the analog-to-digital converter of the present invention.
[0007] To achieve the above object, the present invention provides an analog-to-digital converter, which includes a digital-to-analog conversion circuit, a comparator, a successive approximation register logic circuit and a residual sampling summation circuit, wherein:
[0008] The successive approximation register logic circuit is coupled to the output terminal of the comparator and the control terminal of the digital-to-analog conversion circuit, and the successive approximation register logic circuit is used to generate a corresponding quantized digital signal according to each comparison result of the comparator;
[0009] The output terminal of the digital-to-analog conversion circuit is coupled to the first input terminal of the comparator, and the digital-to-analog conversion circuit is used to receive a common reference voltage signal and a current analog input signal, and generate a corresponding residual voltage based on the analog input signal and the common reference voltage under the control of the quantized digital signal outputted by the successive approximation register logic circuit each time;
[0010] The input end of the residual sampling and summing circuit is coupled to the output end of the digital-to-analog conversion circuit, and the output end is coupled to the second input end of the comparator. The residual sampling and summing circuit is used to sample the residual voltage outputted by the digital-to-analog conversion circuit each time to obtain a corresponding residual, and sum the residual obtained by the previous sampling and the common reference voltage and provide the summed sum to the comparator;
[0011] The comparator is used to compare the current output of the residual sampling and summing circuit with the current output of the digital-to-analog conversion circuit to obtain the current comparison result.
[0012] Optionally, the digital-to-analog conversion circuit is a capacitive digital-to-analog conversion circuit, and includes a plurality of capacitors and a plurality of switches, wherein the switches are coupled to corresponding capacitors, and the switches are opened and closed under the control of the quantized digital signal.
[0013] Optionally, the capacitance values of the plurality of capacitors in the digital-to-analog conversion circuit are in a binary proportional relationship.
[0014] Optionally, the residual sampling and summation circuit includes two branches respectively coupled between the output end of the digital-to-analog conversion circuit and the second input end of the comparator, and when one of the branches samples the residual voltage output by the digital-to-analog conversion circuit, the other branch sums the residual obtained from the previous sampling and the common reference voltage.
[0015] Optionally, each of the branches includes first to fourth switches and a sampling capacitor, wherein one end of the first switch is coupled to the output end of the digital-to-analog conversion circuit and the first input end of the comparator, the other end of the first switch is coupled to one end of the sampling capacitor and one end of the second switch, the other end of the sampling capacitor is coupled to one end of the third switch and one end of the fourth switch, the other end of the fourth switch is coupled to one end of a reset switch and the second input end of the comparator, the other end of the reset switch, the other end of the second switch and the other end of the third switch are all connected to a common reference voltage, the first switch and the third switch are opened and closed synchronously, the second switch and the fourth switch are opened and closed synchronously, and when the first switch is opened, the second switch is closed.
[0016] Optionally, when the control ends of the first switch and the third switch in one branch are coupled to a first clock signal, and the control ends of the second switch and the fourth switch are coupled to a second clock signal, the control ends of the first switch and the third switch in another branch are coupled to the second clock signal, and the control ends of the second switch and the fourth switch are coupled to the first clock signal; wherein the first clock signal and the second clock signal are two-phase non-overlapping clock signals generated based on the sampling clock of the analog-to-digital converter.
[0017] Based on the same inventive concept, the present invention also provides a touch control chip, which includes:
[0018] A charge amplifier is used to convert the touch signal on the touch screen into an analog voltage signal;
[0019] A programmable gain amplifier, used to amplify the analog voltage signal generated by the charge amplifier and output it as an analog input signal;
[0020] And the analog-to-digital converter according to the present invention is used to convert the analog input signal into a quantized digital signal.
[0021] Optionally, the touch control chip further includes a digital filter, an input end of which is coupled to an output end of the analog-to-digital converter, and the digital filter is used to filter out high-frequency components in the quantized digital signal.
[0022] Optionally, the touch control chip also includes a charging and discharging circuit, which couples the corresponding sensing channel of the touch screen and the charge amplifier and is used to charge or discharge the sensing channel to convert the touch signal on the sensing channel into a sensing voltage or a sensing charge to provide to the charge amplifier.
[0023] Based on the same inventive concept, the present invention further provides an electronic device, which includes a touch screen and a touch control chip as described in the present invention. The touch screen has a plurality of sensing channels, and the touch control chip is coupled to each of the sensing channels.
[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0025] 1. After adding the residual sampling and summing circuit to the existing analog-to-digital converter ADC, the analog-to-digital converter ADC quantizes the residual of the current input minus the last quantization result, and there is no serious residual attenuation in the residual summation process, which can approximately achieve the effect of first-order noise shaping and improve the ADC conversion accuracy.
[0026] 2. Further combining with oversampling technology can effectively improve the conversion accuracy of ADC. For example, when the conversion accuracy of the ADC of the present invention is 7 bits under a single sampling scheme, it can easily reach a conversion accuracy of 12 bits under an oversampling scheme. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0028] Figure 1 It is a schematic diagram of the circuit structure of a traditional SAR ADC.
[0029] Figure 2 FIG. 4 is a schematic diagram of the architecture of an analog-to-digital converter according to an embodiment of the present invention.
[0030] Figure 3 yes Figure 2 A schematic diagram of a specific example structure of an analog-to-digital converter is shown.
[0031] Figure 4 yes Figure 3 The working timing diagram of the analog-to-digital converter is shown.
[0032] Figure 5 FIG. 4 is a schematic diagram of the structure of a touch control chip according to an embodiment of the present invention.
[0033] Figure 6 It is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0034] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0035] The following is combined with Figures 2 to 6 The technical solution proposed by the present invention is further described in detail with specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0036] Please refer to Figure 2 An embodiment of the present invention provides an analog-to-digital converter, which includes a digital-to-analog conversion circuit CDAC, a comparator comp, a successive approximation register logic circuit SAR LOGIC and a residual sampling and summing circuit U0.
[0037] Among them, the input end of the successive approximation register logic circuit SAR LOGIC is coupled to the output end of the comparator comp, the output end of the successive approximation register logic circuit SAR LOGIC is coupled to the control end of the digital-to-analog conversion circuit CDAC, and the successive approximation register logic circuit SAR LOGIC is used to generate a corresponding quantized digital signal Dout according to each comparison result of the comparator comp.
[0038] The output end of the digital-to-analog conversion circuit CDAC is coupled to the first input end (e.g., the non-inverting input end +) of the comparator comp, one end of the digital-to-analog conversion circuit CDAC is also coupled to one end of a sampling switch p1, the other end of the sampling switch p1 receives the common reference voltage Vm (also called the common mode voltage) of the analog-to-digital converter, and the other end of the digital-to-analog conversion circuit CDAC also receives the current analog input signal Vin. The control end of the sampling switch p1 is controlled by the sampling clock clks of the analog-to-digital converter. The digital-to-analog conversion circuit CDAC is used to generate a corresponding residual voltage Vp based on the analog input signal Vin and the common reference voltage Vm under the control of the quantized digital signal Dout outputted by the successive approximation register logic circuit SAR LOGIC each time, and provide it to the first input end of the comparator comp.
[0039] The input end of the residual sampling and summing circuit U0 is coupled to the output end of the digital-to-analog conversion circuit CDAC and the first input end of the comparator comp, and the output end of the residual sampling and summing circuit U0 is coupled to the second input end (for example, the inverting input end) of the comparator comp. The residual sampling and summing circuit U0 is used to sample the residual voltage Vp outputted by the digital-to-analog conversion circuit CDAC each time to obtain the corresponding residual Vres, and provide the result Vm-Vres after summing the residual Vres obtained by the previous sampling and the common reference voltage Vm to the comparator comp. If the residual obtained by the previous sampling is Vres(n-1) and the residual obtained by the current sampling is Vres(n), then the voltage Vn of the second input end of the comparator comp is Vm-Vres, and the voltage Vp of the first input end of the comparator comp is Vn+Vres(n)=Vm-Vres(n-1)+Vres(n), and Vres(n) can reflect the current analog input signal Vin.
[0040] The comparator comp is used for comparing the voltage Vp at the first input terminal and the voltage Vn at the second input terminal thereof, and outputting the comparison result to the successive approximation register logic circuit SAR LOGIC.
[0041] The analog-to-digital converter (ADC) of the present embodiment is a NS (noise shaping) SAR ADC, which adopts an EF (Error-Feedback) structure, and defines the current analog input signal of the analog-to-digital converter as Vin(n), the current output quantized digital signal as Dout(n), the residual obtained by the current sampling of the residual sampling and summing circuit U0 as Vres(n), and the residual obtained by the last sampling (i.e., the residual of the last quantization result) as Vres(n-1), and the input and output expressions of the analog-to-digital converter are as follows:
[0042] V in (n) = D out(n)+V res (n)-V res (n-1);
[0043] Performing z-transform on the above equation yields:
[0044] V in (z) = D out (z)+V res (z)(1-z -1 ).
[0045] It can be seen that the analog-to-digital converter performs first-order noise shaping on the residual, and what is quantized is the residual of the current analog input signal minus the previous quantization result, thereby improving the ADC conversion accuracy. The summation operation of the residual and the current analog input signal is completed at the input end of the comparator, which can avoid the problem of serious residual attenuation caused by charge sharing when the CDAC sums the residual and the current analog input signal, and can also avoid the problem of requiring an additional amplifier when the CDAC sums the residual and the current analog input signal. The circuit is simple.
[0046] It should be understood that the digital-to-analog conversion circuit CDAC, the comparator comp, the successive approximation register logic circuit SARLOGIC and the residual sampling and summation circuit U0 can adopt any suitable circuit design in the art, as long as they can achieve their functions in the present invention, and the present invention does not make specific limitations on this.
[0047] As an example, see Figure 3 The digital-to-analog conversion circuit CDAC is a capacitive digital-to-analog conversion circuit, which may include j capacitors C1-Cj and a plurality of switches, which are adaptively coupled to corresponding capacitors and are opened and closed under the control of the quantized digital signal Dout output by the successive approximation register logic circuit SAR LOGIC. The capacitance values of the capacitors C1-Cj may be in a binary proportional relationship, for example, C1=C, C2=2*C1=2 1 *C, C3=2*C2==2 2 *C, and so on, Cj=2 j-1 *C.
[0048] Further exemplarily, the upper plates of all capacitors C1-Cj are coupled to one end of the sampling switch p1 and the first input end of the comparator comp, the lower plate of each capacitor is coupled to one end of four switches k1-k4, and the other end of switch k1 is coupled to the voltage lower limit Vl, the other end of switch k2 is coupled to the common reference voltage Vm, the other end of switch k3 is coupled to the voltage upper limit Vh, the other end of switch k4 is coupled to the current analog input signal Vin, and the control ends of switches k1-k4 are coupled to the corresponding quantized digital signal Dout output by the successive approximation register logic circuit SAR LOGIC. In addition, the other end of the sampling switch p1 receives the common reference voltage Vm, and the control end of the sampling switch p1 receives the sampling clock clks of the analog-to-digital converter. During the sampling phase of the analog-to-digital converter, clks is high, the potential of the upper plates of the capacitors C1-Cj is reset to the Vm potential, and the lower plates of the capacitors C1-Cj are connected to Vin. During the conversion phase of the analog-to-digital converter, clks is low, and the corresponding quantized digital signal Dout controls the lower plates of the capacitors C1-Cj to connect to Vh, Vl or Vm.
[0049] As an example, see Figure 3 The residual sampling and summing circuit U0 includes a reset switch p2 and two branches U01 and U02 respectively coupled between the output end of the digital-to-analog conversion circuit CDAC and the second input end of the comparator comp, and when the branch U01 samples the residual voltage Vp output by the digital-to-analog conversion circuit CDAC, the branch U02 sums the residual Vres sampled last time and the common reference voltage Vm to obtain Vn=Vm-Vres and provides it to the second input end of the comparator comp; when the branch U02 samples the residual voltage Vp output by the digital-to-analog conversion circuit CDAC, the branch U01 sums the residual Vres sampled last time and the common reference voltage Vm to obtain Vn=Vm-Vres and provides it to the second input end of the comparator comp.
[0050] Further exemplarily, the branches U01 and U02 each include the first to fourth switches and a sampling capacitor. The branch U01 includes the first switch m1, the second switch m2, the third switch m3, the fourth switch m4 and the sampling capacitor C01, one end of the first switch m1 is coupled to the output end of the digital-to-analog conversion circuit CDAC and the first input end of the comparator comp, the other end of the first switch m1 is coupled to one end of the sampling capacitor C01 and one end of the second switch m2, the other end of the sampling capacitor C01 is coupled to one end of the third switch m3 and one end of the fourth switch m4, the other end of the fourth switch m4 is coupled to one end of the reset switch p2 and the second input end of the comparator comp, the other end of the reset switch p2, the other end of the second switch m2 and the other end of the third switch m3 are coupled to one end of the reset switch p2 and the second input end of the comparator comp, the other end of the reset switch p2, the other end of the second switch m2 and the other end of the third switch m3 The common reference voltage Vm is connected to the branch U02, which includes a first switch m5, a second switch m6, a third switch m7, a fourth switch m8 and a sampling capacitor C02. One end of the first switch m5 is coupled to the output end of the digital-to-analog conversion circuit CDAC and the first input end of the comparator comp. The other end of the first switch m5 is coupled to one end of the sampling capacitor C02 and one end of the second switch m6. The other end of the sampling capacitor C02 is coupled to one end of the third switch m7 and one end of the fourth switch m8. The other end of the fourth switch m8 is coupled to one end of the reset switch p2 and the second input end of the comparator comp. The other end of the second switch m6 and the other end of the third switch m7 are both connected to the common reference voltage Vm. The control end of the reset switch p2 receives the reset clock signal S3.
[0051] Among them, the control ends of the first switch m1 and the third switch m3 of U01 are coupled to the first clock signal S1, the control ends of the second switch m2 and the fourth switch m4 of U01 are coupled to the second clock signal S2, the control ends of the first switch m5 and the third switch m7 of U02 are coupled to the second clock signal S2, and the control ends of the second switch m6 and the fourth switch m8 of U02 are coupled to the first clock signal S1. And the first clock signal S1 and the second clock signal S2 are two-phase non-overlapping clock signals generated based on the sampling clock clks of the analog-to-digital converter. Therefore, the first switch m1 and the third switch m3 of U01 and the second switch m6 and the fourth switch m8 of U02 are opened and closed synchronously, the second switch m2 and the fourth switch m4 of U01 and the first switch m5 and the third switch m7 of U02 are opened and closed synchronously, and when the first switch m1 is opened, the second switch m2 is closed.
[0052] Please combine Figure 4 In the timing sequence shown, taking the adjacent n-1th residual sampling and nth residual sampling as an example, the working process of the residual sampling and summing circuit U0 of this embodiment is as follows:
[0053] During the n-1th residual sampling, clks is high, S3 is high, S1 is low, and S2 is low, Vn=Vm is reset, then S2 jumps high, S3 jumps low, m5, m7, m2, and m4 are closed, m1, m3, m6, and m8 are disconnected, C2 is connected to Vp for sampling, and the n-1th residual Vres(n-1) is obtained, C1 is connected to Vn, and the residual Vres(n-2) of the previous sampling is summed with Vm to obtain Vn=Vm-Vres(n-2). After that, clk jumps low, and the n-1th residual sampling ends.
[0054] At the nth sampling, when the next clks is high, the second sampling starts, S3 jumps high, S1 is still low, S2 jumps low, and Vn=Vm is reset again. Then S1 jumps high, S3 jumps low, m1, m3, m6, m8 are closed, m5, m7, m2, m4 are disconnected, C1 is connected to Vp sampling, and the nth residual Vres(n) is obtained. C2 is connected to Vn, and the residual Vres(n-1) of the previous sampling is summed with Vm to obtain Vn=Vm-Vres(n-1). Then clk jumps low, and the nth residual sampling ends.
[0055] It can be seen from the working process of the residual sampling and summing circuit U0 described above that in the residual sampling and summing circuit U0 of this embodiment, when C1 is connected to Vp to sample the residual, C2 is connected to Vn and the residual of the previous sampling is summed with Vm. Conversely, when C2 is connected to Vp to sample the residual, C1 is connected to Vn and the residual of the previous sampling is summed with Vm. And the residual sampling and summing circuit U0 is constructed by sampling capacitors and multiple switches, which is simple to implement.
[0056] In addition, since the parasitic capacitance Cpar of the second input terminal (ie, the inverting input terminal) of the comparator comp is relatively small, as long as C1 / C2 takes a value much larger than Cpar, the attenuation of the residual in the summing process can be ignored.
[0057] Under oversampling technology, relatively Figure 1 The prior art shown, the analog-to-digital converter ADC of this embodiment, only needs to add the residual sampling and summing circuit U0, no additional amplifier is needed, and there is no serious residual attenuation, which can well achieve the effect of first-order noise shaping, improve the ADC conversion accuracy, and the ADC also has the advantages of simple circuit and fast speed. Further combined with oversampling technology, the conversion accuracy of the ADC can be efficiently improved. For example, when the conversion accuracy of the ADC of the present invention is 7 bits under the single sampling scheme, it can easily achieve a conversion accuracy of 12 bits under the oversampling scheme.
[0058] Based on the same invention concept, please refer to Figure 5 and Figure 6An embodiment of the present invention further provides a touch chip, which may adopt self-capacitance technology or mutual capacitance technology, and exemplarily includes a charge amplifier CA, a programmable gain amplifier PGA, and an analog-to-digital converter ADC as shown in the present invention.
[0059] Among them, the charge amplifier CA is used to convert the touch signal Csig (self-capacitance) or Cm-Csig (i.e., the equivalent mutual capacitance between the transmitting channel TX and the sensing channel RX on the touch screen 10) on the touch screen 10 into an analog voltage signal VOUT; the programmable gain amplifier PGA is used to amplify the analog voltage signal VOUT generated by the charge amplifier CA and output it as an analog input signal Vin; the analog-to-digital converter ADC is used to convert the analog input signal Vin into a quantized digital signal DOUT.
[0060] Optionally, the touch control chip further includes a digital filter DF, an input end of the digital filter DFDE is coupled to an output end of the analog-to-digital converter ADC, and the digital filter DF is used to filter out high-frequency components in the quantized digital signal DOUT.
[0061] Optionally, the touch control chip also includes a charge and discharge circuit U1, which is coupled to the corresponding sensing channel RX and charge amplifier CA of the touch screen 10 and is used to charge or discharge the sensing channel RX to convert the touch signal on the sensing channel RX into a sensing voltage VRX or a sensing charge to provide to the charge amplifier CA.
[0062] The touch detection circuit 12 is used to detect the capacitance change on the touch screen 10 . The detection result of the touch detection circuit 12 can be used to identify the position of the touch event on the touch screen 10 and determine the touch operation of the user.
[0063] In this embodiment, the touch chip may have a driving circuit 11 coupled to a transmission channel TX and a touch detection circuit 12 coupled to a corresponding sensing channel RX. The touch detection circuit 12 may have a plurality of touch detection branches, and the number of the touch detection branches is the same as the number of the sensing channels RX. The touch detection branches are coupled to the sensing channels RX in a one-to-one correspondence, and each touch detection branch includes a charge and discharge circuit U1, a charge amplifier CA, a programmable gain amplifier PGA and an analog-to-digital converter ADC coupled in sequence. The charge and discharge circuit U1, the charge amplifier CA and the programmable gain amplifier PGA together constitute a front-end circuit AFE of the analog-to-digital converter ADC.
[0064] For example, the touch screen 10 may be any touch screen such as an OLED touch screen, which may have m longitudinally extending transmission channels TX (ie, TX <1> ~TX <m>) and n transversely extending sensing channels RX (ie, RX <1> ~RX <n>), the intersection of each transmission channel TX and each sensing channel RX is a sensing node, and the values of m and n depend on the size and shape of the touch screen 10. Front-end circuit AFE <1> The input terminal of the sensing channel RX <1> Coupling, front-end circuit AFE <1> The output terminal is coupled to an analog-to-digital converter ADC <1> Input terminal; front-end circuit AFE <2> The input terminal of the sensing channel RX <2> Coupling, front-end circuit AFE <2> The output terminal is coupled to an analog-to-digital converter ADC <2> The input end of the front-end circuit AFE <n>The input terminal of the sensing channel RX <n>Coupling, front-end circuit AFE <n>The output terminal is coupled to an analog-to-digital converter ADC <n>The input terminal.
[0065] It should be understood that in this embodiment, each touch detection branch is coupled to a sensing channel RX in a one-to-one correspondence, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, at least part of the circuit in a touch detection branch can be shared by multiple sensing channels RX at the same time. For example, the PGAs of multiple sensing channels RX are coupled to the same ADC. For another example, a charge-discharge circuit U1 is coupled to the PGAs of multiple sensing channels RX at the same time. And no matter what specific circuit design is adopted, as long as the functions of the charge-discharge circuit U1, the charge amplifier CA, and the programmable gain amplifier PGA can be realized. Therefore, the charge-discharge circuit U1, the charge amplifier CA, and the programmable gain amplifier PGA in this embodiment can be implemented by any suitable circuit design.
[0066] Based on the same invention concept, please refer to Figure 6 An embodiment of the present invention further provides an electronic device, which includes a touch screen 10 and a touch control chip as described in the present invention. The touch screen 10 has a plurality of sensing channels RX, and the touch control chip is coupled to each of the sensing channels RX.
[0067] The touch control chip and the electronic device of the present invention have improved performance due to the adoption of the analog-to-digital converter of the present invention.
[0068] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.< / n> < / n> < / n> < / n> < / n> < / m>
Claims
1. An analog-to-digital converter, characterized in that: It includes a digital-to-analog conversion circuit, a comparator, a successive approximation register logic circuit and a residual sampling and summing circuit, wherein: The successive approximation register logic circuit is coupled to the output terminal of the comparator and the control terminal of the digital-to-analog conversion circuit, and the successive approximation register logic circuit is used to generate a corresponding quantized digital signal according to each comparison result of the comparator; The output terminal of the digital-to-analog conversion circuit is coupled to the first input terminal of the comparator, and the digital-to-analog conversion circuit is used to receive a common reference voltage signal and a current analog input signal, and generate a corresponding residual voltage based on the analog input signal and the common reference voltage under the control of the quantized digital signal outputted by the successive approximation register logic circuit each time; The input end of the residual sampling and summing circuit is coupled to the output end of the digital-to-analog conversion circuit, and the output end is coupled to the second input end of the comparator. The residual sampling and summing circuit is used to sample the residual voltage outputted by the digital-to-analog conversion circuit each time to obtain a corresponding residual, and sum the residual obtained by the previous sampling and the common reference voltage and provide the summed sum to the comparator; The comparator is used to compare the current output of the residual sampling and summing circuit with the current output of the digital-to-analog conversion circuit to obtain the current comparison result.
2. The analog-to-digital converter according to claim 1, wherein: The digital-to-analog conversion circuit is a capacitive digital-to-analog conversion circuit and includes a plurality of capacitors and a plurality of switches. The switches are coupled to corresponding capacitors and are opened and closed under the control of the quantized digital signal.
3. The analog-to-digital converter according to claim 2, wherein: The capacitance values of the plurality of capacitors in the digital-to-analog conversion circuit are in a binary proportional relationship.
4. The analog-to-digital converter according to any one of claims 1 to 3, characterized in that: The residual sampling and summing circuit includes two branches respectively coupled between the output end of the digital-to-analog conversion circuit and the second input end of the comparator, and when one of the branches samples the residual voltage output by the digital-to-analog conversion circuit, the other branch sums the residual obtained by the previous sampling and the common reference voltage.
5. The analog-to-digital converter according to claim 4, characterized in that Each of the branches includes first to fourth switches and a sampling capacitor, wherein one end of the first switch is coupled to the output end of the digital-to-analog conversion circuit and the first input end of the comparator, the other end of the first switch is coupled to one end of the sampling capacitor and one end of the second switch, the other end of the sampling capacitor is coupled to one end of the third switch and one end of the fourth switch, the other end of the fourth switch is coupled to one end of the reset switch and the second input end of the comparator, the other end of the reset switch, the other end of the second switch and the other end of the third switch are all connected to a common reference voltage, the first switch and the third switch are opened and closed synchronously, the second switch and the fourth switch are opened and closed synchronously, and when the first switch is opened, the second switch is closed.
6. The analog-to-digital converter according to claim 5, characterized in that When the control ends of the first switch and the third switch in one branch are coupled to the first clock signal, and the control ends of the second switch and the fourth switch are coupled to the second clock signal, the control ends of the first switch and the third switch in another branch are coupled to the second clock signal, and the control ends of the second switch and the fourth switch are coupled to the first clock signal; wherein the first clock signal and the second clock signal are two-phase non-overlapping clock signals generated based on the sampling clock of the analog-to-digital converter.
7. A touch chip, characterized in that: include: A charge amplifier is used to convert the touch signal on the touch screen into an analog voltage signal; A programmable gain amplifier, used to amplify the analog voltage signal generated by the charge amplifier and output it as an analog input signal; The analog-to-digital converter according to any one of claims 1 to 6, configured to convert the analog input signal into a quantized digital signal.
8. The touch control chip according to claim 7, characterized in that: It also includes a digital filter, whose input end is coupled to the output end of the analog-to-digital converter, and the digital filter is used to filter out high-frequency components in the quantized digital signal.
9. The touch control chip according to claim 7, characterized in that: It also includes a charging and discharging circuit, which is coupled to the corresponding sensing channel of the touch screen and the charge amplifier and is used to charge or discharge the sensing channel to convert the touch signal on the sensing channel into a sensing voltage or a sensing charge and provide it to the charge amplifier.
10. An electronic device, characterized in that: The invention comprises a touch screen and a touch control chip as described in any one of claims 7 to 9, wherein the touch screen has a plurality of sensing channels, and the touch control chip is coupled to each of the sensing channels.