FPGA (Field Programmable Gate Array) interface logic resource multiplexing structure and phased-array antenna beam forming system

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) interface logic resource multiplexing structure and a phased-array antenna beam forming system. The FPGA interface logic resource multiplexing structure comprises a transmitting end module and a receiving end module, the sending end module is used for firstly sending a verification sequence to the receiving end module, calibrating a receiving end, and sending user data to the receiving end module after calibration is completed; the calibration sequence and the user data are multi-bit wide data and are converted into high-speed serial data to be output; and the receiving end module is used for receiving the calibration sequence and the high-speed serial data, performing calibration according to the calibration sequence, and converting the high-speed serial data into low-speed parallel data to be output after the calibration is completed. By utilizing the scheme of the invention, the interface logic resource multiplexing can be flexibly and efficiently realized.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an FPGA interface logic resource multiplexing structure and a phased array antenna beam forming system. Background Art

[0002] Phased array antenna is an antenna that changes the shape of the radiation pattern by controlling the feeding phase of the radiating elements in the array antenna. The beam forming of the phased array antenna requires the cooperation of the beam control system and the beam forming system. The beam control system controls the beam forming system on each element of the antenna array, and controls the direction of the spatial synthetic beam of the radar wave by changing the amplitude and phase of the antenna element. When designing the hardware of the beam forming system, the main control board FPGA (Field-Programmable Gate Array) needs to transmit data with the beam forming system in multiple T / R components. The number of T / R components is determined by the number of elements in the antenna array, usually 16 or 64. Therefore, the number of interfaces on the main control board FPGA becomes an important factor restricting the size of the antenna array. When the main control board needs to transmit data to a large-scale antenna array, there will inevitably be insufficient interface logic resources.

[0003] For the above problems, traditional solutions usually choose serial communication protocols such as RS422 or RS485. The implementation of these protocols requires additional interface chips, which greatly increases the cost. By designing the main control board FPGA as a module and reusing the interface logic resources on the board, data transmission between FPGAs can be directly realized, which can more efficiently realize the control of the antenna array elements by the main control board FPGA. The general interface multiplexing solution is to correspond multiple signal pins in the FPGA chip to the same interface I / O. In different situations, the user selects a certain signal to correspond to the interface I / O by configuring the register.

[0004] For the input interface I / O multiplexing circuit, its structure is as follows Figure 1 The multiplexing of the interface logic is connected to the input interface I / O (i.e. Figure 1 Each input interface I / O has a distributor that only allows the input interface I / O to be connected to one internal signal pin at a time, ensuring that internal functions do not conflict when sharing the same input interface I / O.

[0005] Different from the input I / O multiplexing circuit, the structure of the output interface I / O multiplexing circuit is as follows Figure 2 As shown, it is necessary to connect each internal signal output pin to the output interface I / O (i.e. Figure 2A selector is added between the output pins in the FPGA and the internal signal pins in the FPGA. The selector only allows one internal signal pin to be connected to the output interface I / O at a time, so that the output of the internal signal pin can be passed to the FPGA pin at different times.

[0006] For interface logic resource multiplexing, the existing solution is to design a large number of signal control bits, such as Figure 1 and Figure 2 M1,…,Mn in the FPGA transmits different signals through the FPGA interface I / O in a time-sharing manner through the combinatorial logic of the control bits. The biggest disadvantage of this solution is that when the signal bit width is large or the multiplexing is high, too many control bits are required to control the internal signals, and the combinatorial logic for generating the control bits will consume additional resources on the FPGA chip. At the same time, in the phased array antenna beam control system, more signals with different bit widths need to be transmitted between FPGAs. If a set of combinatorial logic circuits for control is specially designed for each situation, the signal transmission efficiency will be greatly reduced. In addition, implementing the I / O multiplexing function only through combinatorial logic may cause timing problems, resulting in errors in sending and receiving data. Summary of the invention

[0007] The embodiments of the present invention provide an FPGA interface logic resource multiplexing structure and a phased array antenna beamforming system to flexibly and efficiently implement interface logic resource multiplexing.

[0008] On the one hand, an embodiment of the present invention provides an FPGA interface logic resource multiplexing structure, the multiplexing structure comprising: a transmitting end module and a receiving end module;

[0009] The transmitting end module is used to first send a check sequence to the receiving end module to calibrate the receiving end, and then send user data to the receiving end module after the calibration is completed; the calibration sequence and the user data are multi-bit width data and are converted into high-speed serial data output;

[0010] The receiving end module is used to receive the calibration sequence and the high-speed serial data, perform calibration according to the calibration sequence, and convert the high-speed serial data into low-speed parallel data for output after the calibration is completed.

[0011] Optionally, the receiving end module is further used to output a calibration indication signal train_done to the sending end module after the calibration is completed;

[0012] After receiving the calibration indication signal rain_done, the transmitting end module converts the received multi-bit width user data into high-speed serial data and outputs it to the receiving end module.

[0013] Optionally, the transmitting end module includes: a counter, a signal selector, and a parallel-to-serial converter;

[0014] The counter is used to start counting the parallel low-speed clock clk_100 after receiving the calibration indication signal train_done, output the counting signal cnt, and output the enabling signal data_en when counting to the set cycle number RATIO;

[0015] The signal selector is used to input the user data and the check sequence, and select to output the user data or the check sequence to the parallel-to-serial converter according to the counting signal cnt, the enable signal data_en, and the calibration indication signal train_done;

[0016] The parallel-to-serial converter is used to convert the received parallel data into high-speed serial data output according to the serial high-speed clock clk_400 and the parallel low-speed clock clk_100.

[0017] Optionally, the signal selector outputs the check sequence before the calibration indication signal train_done takes effect; stops outputting the check sequence after the calibration indication signal train_done takes effect, and outputs the user data after the enable signal data_en takes effect.

[0018] Optionally, the signal selector includes a first selector, a second selector, and a third selector connected in sequence;

[0019] The first selector is used to input the user data and output the user data to the second selector according to the counting signal cnt;

[0020] The second selector is used to input the user data and the non-check sequence, and select to output the user data or the non-check sequence as an output signal to the third selector according to the enable signal data_en;

[0021] The third selector is used to input the check sequence and the output signal, and select to output the check sequence or the output signal to the parallel-to-serial converter according to the calibration indication signal train_done.

[0022] Optionally, the receiving end module includes: a bit synchronization module, an input delay module, a serial-to-parallel converter, and a bit sliding module;

[0023] The bit synchronization module is used to perform edge detection on the calibration sequence, and output a delay indication signal INC to the input delay module when no edge is detected, output a bit slip signal bitslip to the bit slip module after two successful detections, and output the calibration indication signal train_done to the sending end module after the calibration is completed;

[0024] The input delay module is used to input the high-speed serial data, delay the high-speed serial data according to the output delay indication signal INC, and output the delayed high-speed serial data to the serial-to-parallel converter;

[0025] The serial-to-parallel converter is used to convert the input high-speed serial data into parallel data, and output the parallel data to the bit sliding module;

[0026] The bit slip module operates on the parallel low-speed clock clk_100, and is used to shift the input parallel data after receiving the bit slip signal bitslip; when the bit slip signal bitslip is not received, the input parallel data is transparently transmitted.

[0027] Optionally, the bit synchronization module includes a finite state machine, which performs edge detection on the calibration sequence and generates the calibration indication signal train_done, the delay indication signal INC, and the bit slip signal bitslip according to the detected state.

[0028] Optionally, the bit slip signal is a pulse signal, and its pulse width is one clock cycle of the working clock.

[0029] Optionally, the bit sliding module includes: an input register, an intermediate state register, and an output register.

[0030] Optionally, the receiving end module further includes: an output delay module, the output delay module includes a plurality of delay units, and is used to delay the parallel data output by the bit sliding module and output it to a corresponding user.

[0031] Optionally, the number of the delay units is determined according to the bit width of the user data.

[0032] On the other hand, an embodiment of the present invention further provides a phased array antenna beamforming system, the system comprising: a main control board, and one or more beamforming systems coupled to the main control board; each beamforming system is coupled to an antenna array element; the main control board and the beamforming system use the aforementioned FPGA interface logic resource multiplexing structure to achieve control of the antenna array element by the main control board, and data transmission between the main control board and the beamforming system on the antenna array element;

[0033] The transmitting end module is arranged on the main control board; and the receiving end module is arranged in the beam forming system.

[0034] The FPGA interface logic resource multiplexing structure and phased array antenna beamforming system provided in the embodiments of the present invention realize multi-bit width data transmission through a data I / O on the FPGA. The interface logic resource multiplexing structure is used for data transmission between the main control board FPGA and the beam generating system on the antenna array element in the phased array antenna beamforming system. The main control board can directly control multiple antenna array elements, which greatly saves logic resources on the FPGA chip, avoids the use of additional interface chips, and reduces system costs.

[0035] Furthermore, the transmitting module and the receiving module realize data calibration by sending a check sequence. Moreover, at the data receiving end, the bit synchronization and word synchronization of the data are jointly realized by the bit sliding module and the bit synchronization module, which greatly improves the accuracy of data transmission and reception.

[0036] Furthermore, by calling several transmitting modules and receiving modules, the bit width of the data processed by the serial-to-parallel converter, bit sliding module and bit synchronization module inside the module can be modified, and the bit width of the data to be transmitted can be configured to meet the transmission requirements of data with different bit widths and be flexibly used in different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the structure of realizing input interface I / O multiplexing through a distributor;

[0038] Figure 2 This is a schematic diagram of the existing structure of realizing output interface I / O multiplexing through a distributor;

[0039] Figure 3 It is a structural schematic diagram of a FPGA interface logic resource multiplexing structure provided by an embodiment of the present invention;

[0040] Figure 4 is a structural diagram of a sending end module in an embodiment of the present invention;

[0041] Figure 5 yes Figure 4 The working flow diagram of the sending end module shown;

[0042] Figure 6 is a structural diagram of a sending end module in an embodiment of the present invention;

[0043] Figure 7 yes Figure 6 A schematic diagram of the state conversion relationship of the bit synchronization module in the receiving end module shown;

[0044] Figure 8is a schematic diagram of three registers in a bit sliding module performing a shift operation in an embodiment of the present invention;

[0045] Fig. 9 It is a structural schematic diagram of a phased array antenna beamforming system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The principle and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.

[0047] In view of the problems that a large number of signal control bits need to be designed in the existing interface logic resource reuse scheme, which consumes a lot of FPGA chip resources, has poor flexibility, and is prone to causing errors in sending and receiving data, an embodiment of the present invention provides an FPGA interface logic resource reuse structure and a phased array antenna beamforming system using the resource reuse structure, so as to flexibly and efficiently realize interface logic resource reuse.

[0048] like Figure 3 FIG. 1 is a schematic diagram of a structure of an FPGA interface logic resource multiplexing structure provided by an embodiment of the present invention.

[0049] The FPGA interface logic resource multiplexing structure includes: a sending end module 301 and a receiving end module 302;

[0050] The transmitting end module 301 is used to first send a check sequence to the receiving end module to calibrate the receiving end, and then send user data to the receiving end module after the calibration is completed; the calibration sequence and the user data are multi-bit width data and are converted into high-speed serial data output;

[0051] The receiving end module 302 is used to receive the calibration sequence and the high-speed serial data, perform calibration according to the calibration sequence, and convert the high-speed serial data into low-speed parallel data for output after the calibration is completed.

[0052] Furthermore, the receiving end module 302 is further configured to output a calibration indication signal train_done to the sending end module 301 after the calibration is completed, so as to indicate that the calibration of the sending end module 301 is completed.

[0053] Correspondingly, after receiving the calibration indication signal train_done, the transmitting end module 301 converts the received multi-bit width user data into high-speed serial data and outputs it to the receiving end module 302 .

[0054] In a non-limiting embodiment, a specific structure of the sending end module 301 is as follows: Figure 4 shown.

[0055] Reference Figure 4 In this embodiment, the transmitting end module 301 includes: a counter 311, a signal selector 312, and a parallel-to-serial converter 313. Among them:

[0056] The counter 311 is used to start counting the parallel low-speed clock clk_100 after the sending end module 301 receives the calibration indication signal train_done, output the counting signal cnt (sometimes also referred to as the counting value cmt in the following description) to the signal selector 312, and output the enable signal data_en to the signal selector 312 when the counting reaches the set cycle number RATIO;

[0057] The signal selector 312 is used to input user data data_from_user and a check sequence 8'h2C, and select to output the user data or the check sequence to the parallel-to-serial converter according to the counting signal cnt and the enable signal data_en;

[0058] The parallel-to-serial converter 313 is used to convert the received parallel data into high-speed serial data for output according to the serial high-speed clock clk_400 and the parallel low-speed clock clk_100.

[0059] It should be noted that the bit widths of the check sequence 8'h2C and the user data data_from_user should remain the same, for example, they may be 8 bits, 16 bits, etc., which is not limited in the embodiment of the present invention.

[0060] In this embodiment, the count signal cnt and the enable signal data_en are output control signals of the signal selector 312, that is, which input of the signal selector 312 is selected as the output according to the states of the count signal cnt and the enable signal data_en. Specifically, when the calibration indication signal train_done is not effective, that is, when the transmitting end module 301 does not receive the calibration indication signal train_done, the counter 311 enters a reset state and does not count. During this period, the enable signal data_en is also in an invalid state. After receiving the calibration indication signal train_done, the counter 311 starts counting. When the count signal cnt accumulates to the specified number of cycles RATIO, the enable signal data_en is effective. At this time, the calibration indication signal train_done and the enable signal data_en are both effective, and the signal selector 312 outputs the user data data_from_user.

[0061] Furthermore, in order to enable the received signal of the receiving module 302 to accurately keep synchronization with the transmitted signal of the transmitting module 301, the signal selector 312 can also input a non-check sequence, and output the non-check sequence to the parallel-to-serial converter 313 after the calibration indication signal train_done takes effect and before the enable signal data_en takes effect.

[0062] The check sequence and the non-check sequence can be set arbitrarily, and the two should be different. In order to simulate real data, the check sequence preferably includes 10 and 1100, that is, includes the switching of 10 with one bit and two bits. For example, the check sequence is set to: 00101100.

[0063] It should be noted that, in practical applications, the signal selector 312 can be implemented by a three-choice logic chip, or by a single-choice and two two-choice logic chips, such as Figure 4 As shown in , this embodiment of the present invention is not limited to this.

[0064] Reference Figure 4 In this embodiment, the signal selector 312 includes a first selector 41, a second selector 42, and a third selector 43 connected in sequence. Wherein:

[0065] The first selector 41 is used for inputting the user data data_from_user, and outputting the user data data_from_user to the second selector 42 according to the counting signal cnt;

[0066] The second selector 42 is used to input the user data data_from_user and the non-check sequence 8'h2D, and select to output the user data data_from_user or the non-check sequence 8'h2D as an output signal to the third selector 43 according to the enable signal data_en;

[0067] The third selector 43 is used to input the check sequence 8′h2C and the output signal, and select to output the check sequence 8′h2C or the output signal to the parallel-to-serial converter 313 according to the calibration indication signal train_done.

[0068] The first selector 41 decomposes the 8×RATIO bit-width data into RATIO 8-bit width data, and selects them according to the count value cnt. The counter 311 will keep counting the low-speed clock clk_100, reset after counting to RATIO, and then count again.

[0069] It should be noted that RATIO is an internal attribute value that can be configured by the user. The purpose of setting RATIO is to improve the flexibility of the multiplexing structure to meet the application requirements of transmitting user data of different bit widths. Of course, if you only need to transmit fixed bit width data, such as 8-bit width data, you can also set RATIO to the default value of 1.

[0070] The second selector 42 sends data when the enable signal data_en is effective. The enable signal data_en will become effective only when the count value cnt reaches RATIO in the first round.

[0071] Figure 4 In the illustrated embodiment, the input signal of the transmitting module 301 includes a serial high-speed clock clk_400, a parallel low-speed clock clk_100, user data data_user from the user logic, a check sequence 8'h2C and a non-check sequence 8'h2D, and a calibration indication signal train_done; the output signal includes a serial data signal data_to_pin output to an output pin (output Pad), and the output pin is an I / O pin on the FPGA board. The bit width of the check sequence 8'h2C and the non-check sequence 8'h2D is the same as the bit width of the user data data_from_user, which is a parallel data signal, wherein the clock clk is connected to the serial high-speed clock clk_400, and the clock clk_div is connected to the parallel low-speed clock clk_100.

[0072] The rate of the serial data signal data_to_pin and the rate of the parallel data signal can be set as needed, and can be specifically determined by the frequencies of the two clocks clk and clk_div of the parallel-to-serial converter 313. For example, in a non-limiting embodiment, the rate of the serial data signal data_to_pin = the parallel data signal rate × 4.

[0073] Figure 5 The workflow of the sending end module 301 is shown below. Figure 4 and Figure 5 The working process of the sending end module 301 is described in detail.

[0074] Reference Figure 5 In step 501, the system is reset, at which time the counter is in a reset state, the counting signal cnt is 0, and the calibration indication signal train_done is invalid;

[0075] In step 502, a check sequence 8'h2C is sent to enable the receiving end module to perform calibration;

[0076] After the calibration is completed in step 503, the calibration indication signal train_done becomes effective;

[0077] In step 504, the counter starts counting and outputs a counting signal cnt, that is, a counting value; at this time, the signal selector 312 selects to output a non-check sequence 8'h2D;

[0078] In step 505, when the counter counts to the specified number of cycles RATIO (ie, the value of the counting signal cnt is RATIO), the enable signal data_en becomes effective;

[0079] In step 506, the data from the user, i.e., the user data data_user, enters the signal selector 312 after delayed copy extraction, is selected by the counting variable cnt, and enters the parallel-to-serial converter 313;

[0080] For example, the user data width is RATIO×8, RATIO=3, the upper 8 bits, namely [23:16], are transmitted when cnt=1; the middle 8 bits, namely [15:8], are transmitted when cnt=2; and the lower 8 bits, namely [7:0], are transmitted when cnt=3.

[0081] In step 507, the parallel-to-serial converter 313 performs parallel-to-serial conversion on the user data data_user and outputs high-speed serial data to the I / O pins on the FPGA board.

[0082] like Figure 6 FIG. 1 is a schematic diagram of a structure of a sending end module in an embodiment of the present invention.

[0083] Reference Figure 6 The transmitting module 302 includes: a bit synchronization module 321, an input delay module 322, a serial-to-parallel converter 323, and a bit sliding module 324. The bit synchronization module 321, the input delay module 322, the serial-to-parallel converter 323, and the bit sliding module 324 work on the same clock, that is, the parallel low-speed clock clk_100. Wherein:

[0084] The bit synchronization module 321 is used to perform edge detection on the calibration sequence, and output a delay indication signal INC to the input delay module 322 when no edge is detected, output a bit slip signal bitslip to the bit slip module 324 after two successful detections, and output a calibration indication signal train_done to the input delay module 322 after the calibration is completed. Figure 4 The transmitting end module 301 in FIG. It should be noted that the bit slip signal is a pulse signal, and its pulse width is one clock cycle of its working clock.

[0085] The input delay module 322 is used to input the high-speed serial data output by the sending end module 301, that is, from Figure 4 The serial data signal data_to_pin of the output pin can be Figure 6 In order to connect to the input pin of Figure 4 The output pin signal data_to_pin is distinguished in Figure 6 The signal of the input pin is marked as a serial data signal data_from_pin; the input delay module 322 delays the high-speed serial data according to the output delay indication signal INC, and outputs the delayed high-speed serial data to the serial-to-parallel converter 323;

[0086] The serial-to-parallel converter 323 is used to convert the input high-speed serial data into parallel data, and output the parallel data to the bit sliding module 324;

[0087] The bit slip module 324 operates on the parallel low-speed clock clk_100 and is used to shift the input parallel data after receiving the bit slip signal bitslip; when the bit slip signal bitslip is not received, the input parallel data is transparently transmitted.

[0088] In this embodiment, high-speed serial data enters the receiving end module 302 via the I / O pin on the FPGA board. The receiving end module 302 will first delay the serial data through the input delay module 322, and the delayed serial data will be converted into parallel data through the serial-to-parallel converter 323. In order to ensure that the data finally output to the user logic is consistent with the expectation, the output of the serial-to-parallel converter 323 needs to be shifted by the bit sliding module 324. The shifted data is fed back to the bit synchronization module 321, and the bit synchronization module 321 determines whether delay and shift are still required based on the feedback data. If the feedback data is different from the check sequence, delay and shift are required, and the delay indication signal INC is output to the input delay module 322, and the bit sliding signal bitslip is output to the bit sliding module 324. Among them, the delay indication signal INC is used to indicate how much the input delay module 322 delays the input high-speed serial data; the bit sliding signal bitslip is used to indicate that the data currently received by the bit sliding module 324 is different from the check sequence, triggering the bit sliding module 324 to perform a shift operation. If the fed-back data is the same as the check sequence, no delay or shift is required, and the output calibration indication signal train_done is fed back to the sending end module.

[0089] By setting the delay indication signal INC, the bit slip signal bitslip, and the high-speed and low-speed clocks, the received high-speed serial data can be delayed and converted into serial-to-parallel data as desired to obtain the required low-speed parallel data.

[0090] In practical applications, the bit synchronization module 321 can be implemented by a finite state machine, which generates a calibration indication signal train_done according to a current state and provides corresponding control signals for the input delay module 322 and the bit sliding module 324 .

[0091] The workflow of the state machine can be generally divided into four parts: (1) finding the first data edge; (2) finding the second data edge through the first data edge; (3) aligning the clock sampling edge with the data center to ensure that the clock is sampled in the data center; (4) comparing whether the parallel data sequence is correct, and outputting the bit slip signal bitslip to the bit slip module 324.

[0092] Figure 7 The state conversion relationship diagram of the bit synchronization module 321 is shown. The state of the state machine is represented by 5 bits, namely the numbers in brackets in each box.

[0093] Reference Figure 7 After the system is reset, the first sampling is performed and the edge detection is performed on the sampled data. If the first edge detection is successful, the next state is entered; otherwise, the delay indication signal INC is output to the input delay module 322, and the input delay module 322 adds a delay to the input serial data. It should be noted that each delay needs to add a delay of 1 delay unit tap (tap is the delay accuracy, that is, the minimum value of the delay) to the input serial data, and wait for 8 working clocks (that is, the parallel low-speed clock clk_100) cycles before performing edge detection again until the first edge detection is successful.

[0094] After the first edge detection is successful, the delay indication signal INC is output to the input delay module 322. The input delay module 322 increases the delay for the input serial data, searches for the check sequence, and compares the data with the check sequence. If the comparison fails, that is, the check sequence is not detected, the delay indication signal INC continues to be output to increase the delay; if the comparison is successful, the idle state 01100 is entered.

[0095] It should be noted that there is a counter in the state machine for counting the number of delay taps. After detecting the first edge and before detecting the second edge, the counter needs to be reset and the number of taps needs to be counted again. This process requires waiting for the counter to reset and stabilize, that is, entering the idle state 10000.

[0096] After the first edge detection, the state machine adds one to the detection count, and then enters state 00010 to re-detect the edge of the sampled data, that is, start the second edge detection.

[0097] Further considering that the sampled data may have jitter, that is, the data is unstable, in this case, there will be multiple edges. In this case, in state 00010, it is necessary to first determine whether the data at the current sampling moment is still near the first edge. If so, it is necessary to return to state 01111 and continue to output the delay indication signal INC to the input delay module 322. The input delay module 322 adds delay to the input serial data; if not, it indicates that the current sampling moment exceeds the first edge and the data has stabilized. At this time, it enters the edge counting state 01110. Then, the second edge detection officially begins.

[0098] The process of the second edge detection is similar to that of the first edge detection, and will not be described in detail here.

[0099] After the second edge detection is successful, the idle state 10010 is entered, and the counter is also waited for to be reset in the idle state.

[0100] After the counter is reset, it enters the delay halving state 01010. The delay halving means that the number of taps at the left and right edges of the data recorded by the counter is added and divided by 2 to align the sampling time with the data center. For example, the first check to the right edge delayed 10 taps, and the second check to the left edge delayed 2 taps. Then adjust the delay to 6 taps, and the sampling will be aligned with the data center, achieving delay halving. By aligning the clock sampling edge with the data center and completing the bit alignment function of the state machine, the stability of data sampling can be guaranteed.

[0101] Furthermore, considering that a decimal may appear when dividing by 2, in this case, the number of taps can be rounded up by reducing the delay again, that is, the two integers above and below the decimal are tried to select a more appropriate number of taps. At this point, bit synchronization is completed.

[0102] After the bit synchronization is completed, the word synchronization state is entered 00101. Bit synchronization can ensure that the data is sampled correctly, but the order of the data may differ from the expectation of the receiving module by several bits. At this time, the state machine outputs a bit slide signal to the bit slide module 324 for word alignment to achieve word synchronization.

[0103] During the word synchronization process, the sampled data and the check sequence will be compared. If they are inconsistent, the state will enter the bit sliding state 00110, and then return to the word synchronization state 00101, and the data after sliding will be compared with the check sequence until the sampled data is consistent with the check sequence, and the word synchronization is completed.

[0104] After word synchronization is completed, the entire calibration process is completed. At this time, the calibration indication signal train_done is output to the sending end module.

[0105] The bit slip module 324 includes: an input register, an intermediate state register, and an output register. When there is no pulse at the bit slip port of the bit slip module 324, no shift operation is performed, and the register only acts as a pipeline. When a pulse lasting one clock cycle is input to the bit slip port of the bit slip, the current bit will be skipped, and all other bits will be rearranged to a new position. The rearrangement of these bits must be maintained after the bit slip operation to ensure data stability. For 8-bit wide data, 8 shifts are required to traverse all data sequences, such as Figure 8 As shown, 1, 2, and 3 respectively indicate the input register, the intermediate state register, and the output register.

[0106] The bit sliding module 324 feeds back the data of different order to the bit synchronization module 321. Accordingly, the bit synchronization module 321 determines whether the data of the feedback is consistent with the expected value. When the sampled data meets the expectation, the state machine completes the bit synchronization and word synchronization and outputs the calibration indication signal train_done.

[0107] The FPGA interface logic resource multiplexing structure provided in the embodiment of the present invention realizes multi-bit width data transmission through a data I / O on the FPGA. The interface logic resource multiplexing structure is used for data transmission between the main control board FPGA and the beam generating system on the antenna array element in the phased array antenna beam forming system. The main control board can directly control multiple antenna array elements, which greatly saves logic resources on the FPGA chip, avoids the use of additional interface chips, and reduces system costs.

[0108] By utilizing the solution of the present invention, 8-bit wide data transmission can be realized through one data I / O on the FPGA, thus greatly saving I / O resources.

[0109] Continue to refer to Figure 6 In a non-limiting embodiment, the receiving end module 302 may further include an output delay module 325, and the output delay module 325 includes a plurality of delay units for delaying the parallel data output by the bit sliding module and outputting them to the corresponding user.

[0110] The number of the delay units can be determined according to the bit width of the user data. For example, if the bit width of the user data is 16 bits and the bit width of the serial-to-parallel converter output data is 8 bits, two delay units are required, and so on. The number of delay units can be flexibly set according to needs to meet the needs of data transmission with different bit widths.

[0111] It should be noted that in the above description, "serial data" is also referred to as "serial data signal" in some descriptions, and the two have the same meaning and there is no essential difference; similarly, "parallel data" is also referred to as "parallel data signal" in some descriptions, and the two have the same meaning and there is no essential difference.

[0112] Compared with the prior art, the solution of the present invention has the following advantages:

[0113] (1) The solution of the present invention can directly realize the communication between the main control board and the antenna array elements in the phased array antenna beamforming system by multiplexing the FPGA interface logic resources, without the need for additional interface chips, thus reducing costs.

[0114] (2) The solution of the present invention adds a calibration function before the user transmits data, realizes word synchronization and bit synchronization of the received and sent data, avoids possible timing problems, and improves the accuracy of data transmission.

[0115] (3) The solution of the present invention utilizes FPGA chips to design the entirety of the transmitting module and the receiving module, thereby avoiding the addition of a large number of control bits for selecting I / Os and saving logic resources on the FPGA chip.

[0116] (4) The solution of the present invention multiplexes a plurality of data interfaces with different bit widths. It only requires calling a number of transmitting modules and receiving modules to flexibly configure the data bit width to be transmitted. No additional combinational logic circuits for controlling the interface need to be designed. The solution can be conveniently applied to a variety of different scenarios to meet the transmission requirements of data with different bit widths.

[0117] Accordingly, an embodiment of the present invention further provides a phased array antenna beamforming system, such as Fig. 9 The figure shows a structural diagram of the system.

[0118] The phased array antenna beamforming system includes: a main control board 900 , and one or more beamforming systems 901 coupled to the main control board 900 ; each beamforming system 901 is coupled to an antenna array element via a T / R component 902 .

[0119] The aforementioned FPGA interface logic resource multiplexing structure is used between the main control board 900 and the beam forming system 901 to realize the control of the antenna array element by the main control board and the data transmission between the main control board and the beam forming system on the antenna array element.

[0120] Combined with the above Figure 3 ,exist Fig. 9In the phased array antenna beamforming system shown, the transmitting end module 301 in the FPGA interface logic resource multiplexing structure is arranged on the main control board 900 ; the receiving end module 302 is arranged in the beamforming system 901 .

[0121] It should be noted that an interface logic resource multiplexing structure can be set between each beam forming system 901 and the main control board 900 to realize data transmission between the beam forming system 901 and the main control board 900. In addition, as a beam control system, the main control board 900 can call several of the above interface logic resource multiplexing structures to modify the bit width of the data processed by its internal serial-to-parallel conversion module, bit sliding module and bit synchronization module, transmit data with a custom bit width, and realize interface I / O multiplexing in different situations. For example, if the user wants to transmit 24-bit data through an IO port, the RATIO can be set to 3; or the RATIO can be set to 1, and then three of the above interface resource multiplexing structures including the transmitting end module and the receiving end module are instantiated.

[0122] It can be seen that the FPGA interface logic resource multiplexing structure scheme of the present invention is applied to the signal transmission between the beam control system and the beam generating system in the process of phased array antenna beam forming. It can use fewer interface resources to realize multi-bit data transmission between the main control board FPGA and the array element system according to a certain multiplexing ratio (the ratio of data bit width to the number of data I / Os), reduce the number of I / Os required to be used by the main control FPGA of the beam control system, save logic resources on the FPGA, and greatly improve the data transmission efficiency.

[0123] Furthermore, in the FPGA interface logic resource multiplexing structure scheme of the present invention, the user can configure the data bit width by himself to realize the transmission function of data with different bit widths, which can better adapt to the characteristics that the internal signals of the phased array antenna beam control system are usually multi-bit width and variable bit width, and can be flexibly used in various scenarios, further saving FPGA interface logic resources.

[0124] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.

[0125] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An FPGA interface logic resource multiplexing structure, characterized in that: The multiplexing structure includes: a sending end module and a receiving end module; The transmitting end module is used to first send a check sequence to the receiving end module to calibrate the receiving end, and then send user data to the receiving end module after the calibration is completed; the calibration sequence and the user data are multi-bit width data and are converted into high-speed serial data output; The receiving end module is used to receive the calibration sequence and the high-speed serial data, perform calibration according to the calibration sequence, and convert the high-speed serial data into low-speed parallel data for output after the calibration is completed.

2. The FPGA interface logic resource multiplexing structure according to claim 1, characterized in that: The receiving end module is further used to output a calibration indication signal to the sending end module after the calibration is completed; After receiving the calibration indication signal, the transmitting end module converts the received multi-bit width user data into high-speed serial data and outputs it to the receiving end module.

3. The FPGA interface logic resource multiplexing structure according to claim 2, characterized in that: The transmitting end module includes: a counter, a signal selector, and a parallel-to-serial converter; The counter is used to start counting the parallel low-speed clock after receiving the calibration indication signal, output a counting signal, and output an enable signal when counting to a set number of cycles; The signal selector is used to input the user data and the check sequence, and select to output the user data or the check sequence to the parallel-to-serial converter according to the counting signal, the enable signal, and the calibration indication signal; The parallel-to-serial converter is used to convert the received parallel data into high-speed serial data output according to the serial high-speed clock and the parallel low-speed clock.

4. The FPGA interface logic resource multiplexing structure according to claim 3, characterized in that: The signal selector outputs the check sequence before the calibration indication signal takes effect; stops outputting the check sequence after the calibration indication signal takes effect, and outputs the user data after the enable signal takes effect.

5. The FPGA interface logic resource multiplexing structure according to claim 4, characterized in that: The signal selector includes a first selector, a second selector, and a third selector connected in sequence; The first selector is used to input the user data and output the user data to the second selector according to the counting signal; The second selector is used to input the user data and the non-check sequence, and select to output the user data or the non-check sequence as an output signal to the third selector according to the enable signal; The third selector is used to input the check sequence and the output signal, and select to output the check sequence or the output signal to the parallel-to-serial converter according to the calibration indication signal.

6. The FPGA interface logic resource multiplexing structure according to claim 1, characterized in that: The receiving end module includes: a bit synchronization module, an input delay module, a serial-to-parallel converter, and a bit sliding module; The bit synchronization module is used to perform edge detection on the calibration sequence, and output a delay indication signal to the input delay module when no edge is detected, output a bit slide signal to the bit slide module after two successful detections, and output the calibration indication signal to the sending end module after calibration is completed; The input delay module is used to input the high-speed serial data, delay the high-speed serial data according to the output delay indication signal, and output the delayed high-speed serial data to the serial-to-parallel converter; The serial-to-parallel converter is used to convert the input high-speed serial data into parallel data, and output the parallel data to the bit sliding module; The bit sliding module operates on a parallel low-speed clock and is used to shift the input parallel data after receiving the bit sliding signal; when the bit sliding signal is not received, the input parallel data is transparently transmitted.

7. The FPGA interface logic resource multiplexing structure according to claim 6, characterized in that: The bit synchronization module includes a finite state machine, which performs edge detection on the calibration sequence and generates the calibration indication signal, the delay indication signal, and the bit slip signal according to the detected state.

8. The FPGA interface logic resource multiplexing structure according to claim 6, characterized in that: The bit slip signal is a pulse signal, and its pulse width is one clock cycle of the working clock.

9. The FPGA interface logic resource multiplexing structure according to claim 8, characterized in that: The bit sliding module includes: an input register, an intermediate state register, and an output register.

10. The FPGA interface logic resource multiplexing structure according to claim 6, characterized in that: The receiving end module also includes: An output delay module, wherein the output delay module comprises a plurality of delay units and is used to delay the parallel data output by the bit sliding module and output it to a corresponding user.

11. The FPGA interface logic resource multiplexing structure according to claim 10, characterized in that: The number of the delay units is determined according to the bit width of the user data.

12. A phased array antenna beamforming system, characterized in that: The system comprises: a main control board, and one or more beam forming systems coupled to the main control board; each beam forming system is coupled to an antenna array element; the main control board and the beam forming system use the FPGA interface logic resource multiplexing structure as described in any one of claims 1 to 11 to realize the control of the antenna array element by the main control board and the data transmission between the main control board and the beam forming system on the antenna array element; The transmitting end module is arranged on the main control board; and the receiving end module is arranged in the beam forming system.

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