Method and device for realizing real-time parallel image rejection calibration for large-scale MIMO (Multiple Input Multiple Output) multi-radio frequency channel, processor and medium thereof

Abstract

The invention relates to a method for realizing real-time parallel image rejection calibration processing for a large-scale MIMO (Multiple Input Multiple Output) multi-radio-frequency channel. The method comprises the following steps: acquiring an initialized central frequency point of a system and a port list needing to be calibrated; providing an external local oscillator signal for the baseband board card to which the port to be calibrated belongs; a corresponding number of threads is developed, and image rejection calibration of sub-threads is carried out; and traversing the multi-thread management container, sequentially waiting for the sub-threads to exit and be blocked, and recording a calibration result. The invention also relates to a device for realizing real-time parallel image rejection calibration processing for the large-scale MIMO multi-radio frequency channel, a processor and a storage medium thereof. By adopting the method and device for realizing real-time parallel image rejection calibration processing for the large-scale MIMO multi-radio-frequency channel, the processor and the computer readable storage medium thereof, the problem of rapid image calibration of the large-scale MIMO multi-radio-frequency channel is solved, and the quality of an output signal is effectively improved. And the system integration degree is high. The image rejection calibration precision is high, the calibration granularity is accurate and controllable, and the captured weight factor is close to the optimal.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to the field of image signal suppression calibration, and specifically refers to a method, device, processor and computer-readable storage medium thereof for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels. Background Art

[0002] Image rejection calibration refers to calibrating the image signal in the output signal of the signal processing unit to ensure that it meets the accuracy and precision requirements of the signal in the current environment. By adjusting the weight factors that affect the signal in the signal system, the phase and amplitude differences between the signal components are reduced. For the requirements of high-quality transmission of target signals, image rejection calibration is an inevitable link. In practical applications, the analog path from the output of the DAC (Digital-to-Analog Converter) to the input of the orthogonal modulator is often the main cause of the imbalanced amplitude and phase of the IQ (Inphase, in-phase signal component, Quadrature, orthogonal signal component) signal components, which further affects the EVM (Error Vector Magnitude) index of the system output signal.

[0003] For image signal suppression calibration, traditional solutions usually require external instruments, external complex algorithms, and human participation to write calibration data into storage space. This method is not only limited in application scenarios and only applicable to single-port scenarios with low synchronization requirements, but also requires an unbearable amount of time and labor costs in the large-scale MIMO multi-RF port scenario. In addition, frequency switching, temperature drift, and device aging will affect the calibration effect, and writing fixed calibration values ​​cannot guarantee the timeliness of image calibration. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a method, device, processor and computer-readable storage medium thereof for realizing real-time parallel image suppression calibration processing for large-scale MIMO multi-RF channels, which are high in timeliness, simple in operation and have a wide range of applications.

[0005] In order to achieve the above-mentioned object, the method, device, processor and computer-readable storage medium thereof for implementing real-time parallel image suppression calibration processing for massive MIMO multi-radio channels of the present invention are as follows:

[0006] The method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels is mainly characterized in that the method comprises the following steps:

[0007] (1) Obtain the center frequency point of system initialization and the port list that needs to be calibrated;

[0008] (2) Configure a built-in signal generator to provide an external local oscillator signal to the baseband card of the port to be calibrated through a power divider module;

[0009] (3) Based on the obtained port list, a corresponding number of multi-threads are opened, mirror suppression calibration of the sub-threads is performed, and the sub-threads are placed in a thread container for unified management;

[0010] (4) Traverse the multi-thread management container, wait for the child threads to exit and block in turn, and after all the child threads exit, record the calibration results and end the system image suppression calibration process.

[0011] Preferably, the image suppression calibration of the sub-thread in step (3) specifically includes the following steps:

[0012] (3.1) Switch the RF port corresponding to the child thread to the ORX channel;

[0013] (3.2) Based on the center frequency currently configured in the system, configure the local oscillator frequency of ORX;

[0014] (3.3) Turn on the amplifiers on the RF transmission path and ORX channel, and flexibly configure the attenuator value as needed;

[0015] (3.4) Based on the sampling rate of the system and the bandwidth of the required signal, the I-channel data and Q-channel data of the single-tone signal are generated by the host computer and sent to the register address of the FPGA;

[0016] (3.5) The weight factor is adjusted by the algorithm to find the optimal weight factor K value and θ value so that the power amplitude of the image signal in the target signal is minimized;

[0017] (3.6) End the port mirror suppression calibration process, exit the child thread and block, and return the calibration value.

[0018] Preferably, the step (3.5) specifically comprises the following steps:

[0019] (3.5.1) Set the minimum image signal power P min is 0, and its corresponding weight factor K min and θ min is 0;

[0020] (3.5.2) Perform the first loop body loop, fix the K value with a step value of 0.1, traverse the θ value within the empirical value range, and fix the θ after traversal min , traverse the K value with 0.01;

[0021] (3.5.3) Perform the second cycle of the body cycle, and then K min and θ min As a benchmark, the range of 0.1 and 1 is expanded to the left and right for expansion traversal, and the step accuracy is optimized to 0.005 and 0.05;

[0022] (3.5.4) Perform the third cycle of the body cycle, and then K min and θ min As a benchmark, the range of 0.01 and 0.1 is expanded left and right for expansion traversal, and the step accuracy is optimized to 0.001 and 0.01;

[0023] (3.5.5) Compare P after three traversals min and the set threshold value. If it meets the requirements, the calibration is completed; otherwise, repeat steps (3.5.1) to (3.5.4).

[0024] Preferably, the step (3.5.2) specifically includes the following steps:

[0025] (3.5.2.1) Calculate the values ​​of A and B based on the current weight factor K and θ, and send A and B to the specified register address of the FPGA;

[0026] (3.5.2.2) The I and Q data of the current channel output are collected in real time through FPGA, and the power P of the image signal is calculated through Fourier transform. cur ;

[0027] (3.5.2.3) Determine P cur and P min The size of P cur Less than P min , then P min Set to P cur Update K min and θ min .

[0028] Preferably, the values ​​of A and B are calculated in the step (3.5.2.1) as follows:

[0029] Calculate the values ​​of A and B according to the following formula:

[0030]

[0031] Among them, K and θ are the current weight factors.

[0032] The device for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels is characterized in that the device comprises:

[0033] a processor configured to execute computer executable instructions;

[0034] A memory stores one or more computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels are implemented.

[0035] The processor for implementing real-time parallel image suppression calibration processing for massive MIMO multi-radio channels is characterized in that the processor is configured to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the various steps of the method for implementing real-time parallel image suppression calibration processing for massive MIMO multi-radio channels are implemented.

[0036] The computer-readable storage medium is characterized in that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels.

[0037] The method, device, processor and computer-readable storage medium for realizing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels of the present invention are adopted, which can solve the problem of fast image calibration of large-scale MIMO multi-radio channels, so that the I and Q signal components in the target output signal meet the theoretical orthogonal characteristics as much as possible, and effectively improve the quality of the output signal. The system has a high degree of integration, and does not require the participation of external instruments and personnel. It can automatically perform fast image suppression calibration operations according to the center frequency of the system by relying on the built-in signal generator, host computer and FPGA module. The image suppression calibration has high accuracy, the calibration granularity is accurate and controllable, and the captured weight factor is close to the optimal. The present invention can be applied to scenarios with high timeliness requirements, especially large-scale MIMO multi-radio channel scenarios. According to the number of channels that need to be calibrated, a corresponding number of calibration sub-threads are opened to realize fast image suppression calibration in parallel. The calibration time depends only on the single RF channel that takes the longest time. Compared with the traditional calibration scheme, the calibration time is greatly compressed under the premise of meeting the threshold of the image suppression ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the image suppression result of a single channel at 4.5 GHz in the method for implementing real-time parallel image suppression calibration processing for massive MIMO multi-radio channels of the present invention.

[0039] Figure 2 It is a schematic diagram of the image suppression result of a single channel at 5.2 GHz in the method for implementing real-time parallel image suppression calibration processing for massive MIMO multi-radio channels of the present invention.

[0040] Figure 3 A schematic diagram of a host computer opening up multiple threads according to the number of MIMO multi-radio channels for the method of realizing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels of the present invention.

[0041] Figure 4 A schematic diagram of a calibration process that needs to be executed by a sub-thread of the method for implementing real-time parallel image suppression calibration processing for massive MIMO multi-radio channels of the present invention.

[0042] Figure 5 The present invention is a schematic diagram of a host computer weight factor adjustment module of a method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels. DETAILED DESCRIPTION

[0043] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0044] The method of the present invention for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels includes the following steps:

[0045] (1) Obtain the center frequency point of system initialization and the port list that needs to be calibrated;

[0046] (2) Configure a built-in signal generator to provide an external local oscillator signal to the baseband card of the port to be calibrated through a power divider module;

[0047] (3) Based on the obtained port list, a corresponding number of multi-threads are opened, mirror suppression calibration of the sub-threads is performed, and the sub-threads are placed in a thread container for unified management;

[0048] (4) Traverse the multi-thread management container, wait for the child threads to exit and block in turn, and after all the child threads exit, record the calibration results and end the system image suppression calibration process.

[0049] As a preferred embodiment of the present invention, the image suppression calibration of the sub-thread in step (3) specifically includes the following steps:

[0050] (3.1) Switch the RF port corresponding to the child thread to the ORX channel;

[0051] (3.2) Based on the center frequency currently configured in the system, configure the local oscillator frequency of ORX;

[0052] (3.3) Turn on the amplifiers on the RF transmission path and ORX channel, and flexibly configure the attenuator value as needed;

[0053] (3.4) Based on the sampling rate of the system and the bandwidth of the required signal, the I-channel data and Q-channel data of the single-tone signal are generated by the host computer and sent to the register address of the FPGA;

[0054] (3.5) The weight factor is adjusted by the algorithm to find the optimal weight factor K value and θ value so that the power amplitude of the image signal in the target signal is minimized;

[0055] (3.6) End the port mirror suppression calibration process, exit the child thread and block, and return the calibration value.

[0056] As a preferred embodiment of the present invention, the step (3.5) specifically includes the following steps:

[0057] (3.5.1) Set the minimum image signal power P min is 0, and its corresponding weight factor K min and θ min is 0;

[0058] (3.5.2) Perform the first loop body loop, fix the K value with a step value of 0.1, traverse the θ value within the empirical value range, and fix the θ after traversal min , traverse the K value with 0.01;

[0059] (3.5.3) Perform the second cycle of the body cycle, and then K min and θ min As a benchmark, the range of 0.1 and 1 is expanded to the left and right for expansion traversal, and the step accuracy is optimized to 0.005 and 0.05;

[0060] (3.5.4) Perform the third cycle of the body cycle, and then K min and θ min As a benchmark, the range of 0.01 and 0.1 is expanded left and right for expansion traversal, and the step accuracy is optimized to 0.001 and 0.01;

[0061] (3.5.5) Compare P after three traversals min and the set threshold value. If it meets the requirements, the calibration is completed; otherwise, repeat steps (3.5.1) to (3.5.4).

[0062] As a preferred embodiment of the present invention, the step (3.5.2) specifically includes the following steps:

[0063] (3.5.2.1) Calculate the values ​​of A and B based on the current weight factor K and θ, and send A and B to the specified register address of the FPGA;

[0064] (3.5.2.2) The I and Q data of the current channel output are collected in real time through FPGA, and the power P of the image signal is calculated through Fourier transform. cur ;

[0065] (3.5.2.3) Determine P cur and P min The size of P cur Less than P min , then P min Set to P cur Update K min and θ min .

[0066] As a preferred embodiment of the present invention, the values ​​of A and B are calculated in step (3.5.2.1), specifically:

[0067] Calculate the values ​​of A and B according to the following formula:

[0068]

[0069] Among them, K and θ are the current weight factors.

[0070] The device for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels of the present invention, wherein the device comprises:

[0071] a processor configured to execute computer executable instructions;

[0072] A memory stores one or more computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels are implemented.

[0073] The processor of the present invention is used to implement real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels, wherein the processor is configured to execute computer-executable instructions. When the computer-executable instructions are executed by the processor, the various steps of the method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels are implemented.

[0074] The computer-readable storage medium of the present invention stores a computer program thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels.

[0075] In a specific embodiment of the present invention, a solution for real-time parallel image suppression calibration of multiple radio frequency channels integrated in a large-scale MIMO system is provided. This calibration is built into the initialization link of the system and does not require human participation. Only a built-in signal generator, a host computer and an FPGA (Field Programmable Gate Array) module are required to realize fast image suppression calibration of large-scale MIMO multiple radio frequency channels, thereby effectively improving the integration, reliability and timeliness of the system.

[0076] like Figure 3 The host computer opens a multi-threaded schematic diagram. According to the number of channels to be calibrated in the large-scale MIMO system, the host computer opens the corresponding number of threads, and implements multi-port and fast mirror calibration in parallel to effectively suppress the amplitude of the mirror signal and improve the quality of the output target signal. Based on any central frequency point to be calibrated in the large-scale MIMO system, the built-in signal generator provides an external intrinsic signal to the RF module that needs mirror suppression calibration. The I-channel data and Q-channel data of the current module channel are collected in real time through the FPGA module, and the power of the mirror signal is calculated through fast Fourier transform.

[0077] like Figure 5 It is a schematic diagram of the weight factor adjustment module. According to the power of the real-time feedback mirror signal, the two factors affecting the mirror signal are adjusted through the internal algorithm of the host computer to reduce the amplitude of the mirror signal in the target output signal, forming a feedback mechanism so that the mirror signal component in the output signal is buried in the background noise, thereby reducing the difference in amplitude and phase between the signal components in the output signal.

[0078] In a second aspect, the present invention provides an integrated solution based on image suppression calibration, including a built-in signal generator, an FPGA data acquisition module, and a host computer;

[0079] The built-in signal generator is used to generate a double frequency signal according to the center frequency of the system, thereby providing an external local oscillator signal source for the radio frequency transmission channel that needs to be calibrated;

[0080] The FPGA data acquisition module is used to collect I-channel data and Q-channel data of the calibration transmission channel in real time, and calculate the amplitude of the image signal through Fourier transform, system sampling rate and the difference between the image signal and the local oscillator signal;

[0081] The host computer is used to implement all the operation steps of large-scale MIMO multi-RF channel image suppression calibration, including switching RF channels, controlling the switches of amplifiers and attenuators on the RF path, controlling the read and write operations of the FPGA chip, calculating the image signal power using a fast Fourier transform algorithm, obtaining the optimal weight factor using an algorithm, and performing multi-channel fast image suppression calibration according to the number of RF channels that need to be calibrated.

[0082] The present invention provides an image suppression calibration method integrated in a large-scale MIMO system, generates an external local oscillator signal and a single-tone signal required for calibration based on any center frequency point of the system, collects I-channel data and Q-channel data of the calibration channel in real time according to the FPGA module, calculates the amplitude of the image signal in the target signal, and captures two optimal weight factors through the host computer algorithm, so that the image signal is buried in the background noise as much as possible, thereby achieving the purpose of optimizing the amplitude and phase difference of each signal component in the target output signal, and improving the quality of the output signal. In the whole image suppression process, there is no need to use external instruments and meters, and human participation. The host software will automatically execute the operation process in the system initialization link, thereby improving the integration and reliability of the system.

[0083] For communication systems, the essence of the signal can be split into IQ data. When the amplitude or phase of the I-channel data and the Q-channel data are unbalanced, the EVM index of the system will deteriorate. For example, the DAC calibration method is often used in the architecture of the base station, that is, the phase and amplitude of the output DAC signal are calibrated so that the I-channel data and the Q-channel data meet the orthogonal characteristics as much as possible. This method usually requires an external spectrum analyzer to observe the spectrum of the mirror signal in the transmitted signal at a preset frequency, and adjust the DAC control word corresponding to the current frequency to achieve the effect of suppressing the mirror signal. In this process, external instruments, algorithm software, and personnel operations are also required. The calibration steps are cumbersome and time-sensitive, and cannot meet the requirements of large-scale MIMO multi-RF channel fast image suppression calibration.

[0084] To solve the above technical problems, an example of the present invention provides a multi-RF channel fast image suppression calibration integrated in a large-scale MIMO system. The scheme can be calibrated based on any center frequency point configured in the system. The host computer automatically traverses the enabled RF ports in the system and opens up the number of threads according to the number of ports. In this embodiment, 80 RF channels need to be calibrated at the same time, and the overall system image suppression calibration time is compressed to minutes.

[0085] In this embodiment, the following operation steps are implemented by the host computer:

[0086] Step 1: See Figure 3 , the host computer obtains the center frequency point of system initialization and the list of ports that need to be calibrated.

[0087] Step 2: Configure the built-in signal generator with a frequency twice the system center frequency and a power of 0dBm. Provide an external local oscillator signal to the baseband board of the port to be calibrated through the power divider module.

[0088] Step 3: The host computer opens a corresponding number of multi-threads based on the obtained port list, performs image suppression calibration, and puts the sub-threads into the thread container for unified management. It should be noted that each port calibration process corresponds to a separate sub-thread.

[0089] Step 4: Traverse the multi-thread management container, wait for the child threads to exit and block in turn, and after all the child threads exit, record the calibration results and end the system image suppression calibration link.

[0090] Further, based on the above embodiment, in the above step 3, a subthread is opened to perform port mirror suppression calibration, see Figure 4 ,The calibration process of the sub-thread includes the following steps:

[0091] Step 1: Switch the RF port corresponding to the child thread to the ORX (Observed Receiver) channel.

[0092] Step 2: Based on the center frequency of the current system configuration, configure the local oscillator frequency of ORX. The local oscillator frequency of ORX is not equal to the center frequency of the current system, but a certain frequency offset is added to the center frequency of the system. The frequency offset can be positive or negative.

[0093] It should be noted that, assuming the center frequency of the system is F c The absolute value of the superimposed frequency deviation is 17 MHz. The purpose of setting this frequency deviation value is to avoid being equal to the common single-tone signal frequency.

[0094] If the high frequency solution is adopted, the center frequency of ORX is

[0095] F PRX =F c +17MHz,

[0096] If it is a low-frequency solution, the center frequency of ORX is

[0097] F ORX =F c -17MHz,

[0098] That is, on the spectrum of ORX, the local oscillator signal of ORX appears at 17MHz and -17MHz respectively. ORX =F c +17MHz is greater than the maximum frequency supported by the system, then the low frequency solution is adopted, otherwise F ORX =F c If -17MHz is less than the minimum frequency supported by the system, a high-frequency solution is used.

[0099] Step 3: Turn on the amplifiers on the RF transmit path and the ORX channel and flexibly configure the attenuator value as needed to maximize the power of the transmit signal and avoid saturation or self-excitation.

[0100] Step 4: Based on the sampling rate of the system and the bandwidth of the required signal, the I-channel data and Q-channel data of the single-tone signal are generated by the host computer and sent to the register address of the FPGA.

[0101] The frequency of the single tone signal must not be equal to the absolute difference between the ORX frequency and the system center frequency. In this embodiment, the frequency of the single tone signal is set to 10 MHz and the power is -4 dBm, which corresponds to F in the spectrum of ORX. main =F ORX +10MHz, according to |F main -F ORx |=|F ORx -F mirror |It can be seen that F mirror =F mirror -10MHz. If a high frequency solution is used, the image signal will appear at 7MHz in the ORX spectrum.

[0102] Step 5: Find the optimal weight factor K value and θ value through the algorithm inside the host computer, so that the power amplitude of the image signal in the target signal is minimized, which is the key to the calibration of the image suppression signal in this embodiment. Send the optimal weight factor K value and θ value to the register address of FPFA. It should be noted that the K value and θ value have a minimum step accuracy of 0.01°, and its adjustment range is [-10°, 10°]. The minimum step accuracy of K value is 0.001dB, and its adjustment range is [-1, 1]. The weight factor θ value has a higher priority.

[0103] Step 6: End the port mirror suppression calibration process, exit the child thread and block, and return the calibration value.

[0104] Further, based on the above sub-thread calibration process, the weight factor is adjusted by an algorithm in the above step 5, including the following steps:

[0105] Step (1): Set the minimum image signal power to P min =0, and its corresponding weight factor is K min =0 and θ min =0.

[0106] Step (2): Figure 3 As shown, the first loop body loop is performed. First, the K value is fixed with a step value of 0.1, and the θ value is traversed within the empirical value range. The θ after traversal is fixed. min , traverse the K value by 0.01, and execute the following steps for each step:

[0107] Step a: Calculate according to the current weight factor K value θ

[0108]

[0109] Send A and B to the specified register address of FPGA.

[0110] Step b: The I-channel data and Q-channel data output by the current channel are collected in real time through the FPGA in the system, and the power P of the image signal is calculated through Fourier transform. cur .

[0111] Step c: If P cur <P min , then P min =P cur , update K min and θ min .

[0112] Step (3): Perform a second cycle of the systemic cycle, using K min and θ min As a benchmark, the range of 0.1 and 1 is expanded to the left and right for expansion traversal, and the step accuracy is optimized to 0.005 and 0.05.

[0113] Step (4): Perform the third cycle of the systemic cycle, with K min and θ min As a benchmark, the range of 0.01 and 0.1 is expanded left and right for expansion traversal, and the step accuracy is optimized to 0.001 and 0.01.

[0114] Step (5): After three traversals, P min , and compare it with the set threshold value. If it meets the requirements, the calibration is ended. Otherwise, repeat steps (1) to (4).

[0115] Due to the limitation of the number of external spectrum analyzers, different RF channels in the MIMO system are randomly selected to demonstrate the effect of image rejection calibration. Figure 1 , a schematic diagram of the image suppression calibration results of a single RF channel at 4.5GHz, this figure is the result of the image suppression calibration, and the image suppression result is -67.4dBFc. Figure 2 , a schematic diagram of a single RF channel 5.2GHz image suppression calibration. The figure is the result of the image suppression calibration, and the image suppression result is -72.41dBFc.

[0116] The present invention completes the image suppression calibration of 80 radio frequency ports of the large-scale MIMO system as a whole, and the calibration time is compressed to minutes. Compared with the traditional calibration method, it effectively realizes the parallel rapid image suppression calibration of multiple radio frequency channels.

[0117] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0118] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0119] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0120] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0121] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0122] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0123] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0124] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0125] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0126] The method, device, processor and computer-readable storage medium for realizing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels of the present invention are adopted, which can solve the problem of fast image calibration of large-scale MIMO multi-radio channels, so that the I and Q signal components in the target output signal meet the theoretical orthogonal characteristics as much as possible, and effectively improve the quality of the output signal. The system has a high degree of integration, and does not require the participation of external instruments and personnel. It can automatically perform fast image suppression calibration operations according to the center frequency of the system by relying on the built-in signal generator, host computer and FPGA module. The image suppression calibration has high accuracy, the calibration granularity is accurate and controllable, and the captured weight factor is close to the optimal. The present invention can be applied to scenarios with high timeliness requirements, especially large-scale MIMO multi-radio channel scenarios. According to the number of channels that need to be calibrated, a corresponding number of calibration sub-threads are opened to realize fast image suppression calibration in parallel. The calibration time depends only on the single RF channel that takes the longest time. Compared with the traditional calibration scheme, the calibration time is greatly compressed under the premise of meeting the threshold of the image suppression ratio.

[0127] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for implementing real-time parallel image rejection calibration processing for massive MIMO multi-radio channels, characterized in that: The method comprises the following steps: (1) Obtain the center frequency point of system initialization and the list of ports that need to be calibrated; (2) Configure a built-in signal generator to provide an external local oscillator signal to the baseband card of the port to be calibrated through a power divider module; (3) Based on the obtained port list, a corresponding number of multi-threads are opened, mirror suppression calibration of the sub-threads is performed, and the sub-threads are placed in a thread container for unified management; (4) Traverse the multi-thread management container, wait for the child threads to exit and block in turn, and after all the child threads exit, record the calibration results and end the system image suppression calibration process.

2. The method for implementing real-time parallel image rejection calibration processing for massive MIMO multi-radio channels according to claim 1, characterized in that: The step (3) of performing image suppression calibration of the sub-thread specifically includes the following steps: (3.1) Switch the RF port corresponding to the child thread to the ORX channel; (3.2) Based on the center frequency currently configured in the system, configure the local oscillator frequency of ORX; (3.3) Turn on the amplifiers on the RF transmission path and ORX channel, and flexibly configure the attenuator value as needed; (3.4) Based on the sampling rate of the system and the bandwidth of the required signal, the I-channel data and Q-channel data of the single-tone signal are generated by the host computer and sent to the register address of the FPGA; (3.5) The weight factor is adjusted by the algorithm to find the optimal weight factor K value and θ value so that the power amplitude of the image signal in the target signal is minimized; (3.6) End the port mirror suppression calibration process, exit the child thread and block, and return the calibration value.

3. The method for implementing real-time parallel image rejection calibration processing for massive MIMO multi-radio channels according to claim 2, characterized in that: The step (3.5) specifically comprises the following steps: (3.5.1) Set the minimum image signal power P min is 0, and its corresponding weight factor K min and θ min is 0; (3.5.2) Perform the first loop body loop, fix the K value with a step value of 0.1, traverse the θ value within the empirical value range, and fix the θ after traversal min , traverse the K value with 0.01; (3.5.3) Perform the second cycle of the body cycle, and then K min and θ min As a benchmark, the range of 0.1 and 1 is expanded to the left and right for expansion traversal, and the step accuracy is optimized to 0.005 and 0.05; (3.5.4) Perform the third cycle of the body cycle, and then K min and θ min As a benchmark, the range of 0.01 and 0.1 is expanded left and right for expansion traversal, and the step accuracy is optimized to 0.001 and 0.01; (3.5.5) Compare P after three traversals min and the set threshold value. If it meets the requirements, the calibration is completed; otherwise, repeat steps (3.5.1) to (3.5.4).

4. The method for implementing real-time parallel image rejection calibration processing for massive MIMO multi-radio channels according to claim 3, characterized in that: The step (3.5.2) specifically includes the following steps: (3.5.2.1) Calculate the values ​​of A and B based on the current weight factor K and θ, and send A and B to the specified register address of the FPGA; (3.5.2.2) The I and Q data of the current channel output are collected in real time through FPGA, and the power P of the image signal is calculated through Fourier transform. cur ; (3.5.2.3) Determine P cur and P min The size of P cur Less than P min , then P min Set to P cur Update K min and θ min .

5. The method for implementing real-time parallel image rejection calibration processing for massive MIMO multi-radio channels according to claim 1, characterized in that: The values ​​of A and B are calculated in the step (3.5.2.1) as follows: Calculate the values ​​of A and B according to the following formula: Among them, K and θ are the current weight factors.

6. A device for implementing real-time parallel image rejection calibration processing for large-scale MIMO multi-radio channels, characterized in that: The device comprises: a processor configured to execute computer-executable instructions; A memory storing one or more computer executable instructions, wherein when the computer executable instructions are executed by the processor, the steps of the method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels as described in any one of claims 1 to 5 are implemented.

7. A processor for implementing real-time parallel image rejection calibration processing for massive MIMO multi-radio channels, characterized in that: The processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the steps of the method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels as described in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing real-time parallel image suppression calibration processing for large-scale MIMO multi-radio channels as described in any one of claims 1 to 5.

Images