Semiconductor device and preparation method thereof, memory and electronic equipment

Abstract

The invention relates to a semiconductor device and a preparation method thereof, a memory and electronic equipment. The semiconductor device comprises isolation structures and target columns which are located on a substrate and are sequentially and alternately arranged in the first direction; the target column comprises a well isolation layer, a bit line structure and an active column which are sequentially stacked in the thickness direction of the substrate; the bottom surface of the isolation structure is lower than the bottom surface of the well isolation layer; the doping type of the well isolation layer is opposite to that of the substrate under the well isolation layer; the bit line structure comprises a middle protruding part connected with the bottom surface of the active column, and a straight part located between the bottom surface of the middle protruding part and the well isolation layer. According to the invention, the impedance of the bit line structure can be reduced and an effective isolation structure can be formed between different bit line structures.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor device and a manufacturing method thereof, a memory and an electronic device. Background Art

[0002] With the rapid development of semiconductor technology, the market has higher and higher requirements for the integration, performance and reliability of integrated circuits. The use of vertical channel transistors can reduce the cross-sectional area of ​​transistors while ensuring that the performance of semiconductor devices is not reduced, thereby improving the integration of integrated circuits.

[0003] However, the conventional bit line structure connected to the vertical channel transistor has a high resistivity, which poses a challenge to further optimizing the performance of semiconductor devices. Moreover, as the feature size of semiconductor devices decreases, the spacing between different bit line structures becomes smaller and smaller, resulting in an increase in parasitic capacitance between adjacent bit lines and an increased risk of leakage current. Summary of the invention

[0004] Based on this, the present disclosure provides a semiconductor device and a preparation method thereof, a memory and an electronic device, which can at least reduce the impedance of the bit line structure and form an effective isolation structure between different bit line structures, avoid the generation of parasitic capacitance and leakage current between adjacent buried bit line structures, and improve the performance and reliability of the semiconductor device.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a semiconductor device, comprising an isolation structure and a target column arranged alternately in sequence along a first direction on a substrate; the target column comprises a well isolation layer, a bit line structure and an active column stacked in sequence along the thickness direction of the substrate; the bottom surface of the isolation structure is lower than the bottom surface of the well isolation layer; the doping type of the well isolation layer is opposite to the doping type of the substrate directly thereunder; the bit line structure comprises a middle protrusion connected to the bottom surface of the active column, and a straight portion between the bottom surface of the middle protrusion and the well isolation layer.

[0006] In the semiconductor device of the above embodiment, an isolation structure and a target column are alternately arranged in sequence along a first direction formed on a substrate; the target column includes a well isolation layer, a bit line structure and an active column stacked in sequence along the thickness direction of the substrate; the bottom surface of the isolation structure is lower than the bottom surface of the well isolation layer, so that the target columns adjacent to each other along the first direction are effectively isolated via the isolation structure; the doping type of the well isolation layer is opposite to the doping type of the substrate directly below it, so that the well isolation layer and the substrate directly below it form a PN junction; the bit line structure includes a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer, so that the bit line structure is electrically connected to the substrate via the aforementioned PN junction, effectively reducing the occurrence of leakage; because the bit line structure is in an inverted T shape, and the bit line structures adjacent to each other along the first direction are effectively isolated via the isolation structure, it is beneficial to reduce the spacing between the bit line structures adjacent to each other along the first direction, and reduce the spacing between the active columns adjacent to each other along the first direction, thereby reducing the cross-sectional area of ​​the transistor prepared on the active column.

[0007] In some embodiments, the orthographic projection of the middle protrusion on the top surface of the substrate is within the orthographic projection of the active column directly above the middle protrusion on the top surface of the substrate, thereby increasing the contact area between the connecting corner between the active column and the middle protrusion and the isolation structure, and increasing the thickness of the isolation structure at the corner, thereby effectively avoiding leakage current or tip discharge at the contact surface.

[0008] In some embodiments, the orthographic projection of the active pillar on the top surface of the substrate and the bit line structure directly below the active pillar are within the orthographic projection of the top surface of the substrate, thereby relatively increasing the longitudinal cross-sectional area of ​​the bit line structure and reducing the impedance of the bit line structure while maintaining the volume of the semiconductor device without increasing it.

[0009] In some embodiments, the bit line structure further includes a metal conductive layer, which is located on the outer sidewall surfaces of the middle protruding portion opposite to each other along the first direction and a portion of the top surface of the straight portion to reduce the impedance of the bit line structure.

[0010] In some embodiments, the active pillar is provided with a first doping region, a channel region, and a second doping region arranged in sequence along the thickness direction of the substrate, the first doping region is adjacent to the bit line structure directly below it, and the top surface of the isolation structure is not lower than the top surface of the second doping region; the doping type of the first doping region is the same as the doping type of the well isolation layer directly below it, and the doping type of the first doping region is the same as the doping type of the second doping region. This embodiment facilitates the subsequent direct preparation of a gate surrounding the channel region to prepare a vertical gate-all-around transistor, reduces the complexity of the vertical gate-all-around transistor preparation process, and improves the performance and reliability of the vertical gate-all-around transistor.

[0011] In some embodiments, the well isolation layer forms a PN junction with the substrate directly thereunder; the first doped region is used to form a source contact region, and the second doped region is used to form a drain contact region; or, the first doped region is used to form a drain contact region, and the second doped region is used to form a source contact region.

[0012] In some embodiments, the bit line structure extends along a second direction; the second direction intersects with the first direction and both are perpendicular to the thickness direction of the substrate; active pillars adjacent along the second direction share the bit line structure directly below the active pillar to reduce the complexity of the bit line structure preparation process in the stacked structure.

[0013] According to some embodiments, another aspect of the present disclosure provides a memory, including the semiconductor device described in the aforementioned embodiments. Since the bit line structure is in an inverted T shape and the bit line structures adjacent to each other along the first direction are effectively isolated by the isolation structure, it is beneficial to reduce the spacing between the bit line structures adjacent to each other along the first direction, and reduce the spacing between the active pillars adjacent to each other along the first direction, thereby reducing the cross-sectional area of ​​the transistor prepared on the active pillar.

[0014] According to some embodiments, another aspect of the present disclosure provides an electronic device, comprising the memory in the aforementioned embodiments, so as to improve the performance and reliability of the electronic device while ensuring that the volume of the electronic device is not increased.

[0015] According to some embodiments, another aspect of the present disclosure provides a method for preparing a semiconductor device, comprising:

[0016] providing a substrate;

[0017] A first isolation layer and a target column are formed on a substrate and are arranged alternately in sequence along a first direction; the target column comprises a well isolation layer, a bit line structure and an active column which are stacked in sequence along the thickness direction of the substrate; the bit line structure comprises a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer; the doping type of the well isolation layer is opposite to the doping type of the substrate directly below it; the bottom surface of the first isolation layer is lower than the bottom surface of the well isolation layer and the top surface is not higher than the top surface of the straight portion;

[0018] A second isolation layer is formed at least between the bit line structures adjacent to each other along the first direction. The first isolation layer and the second isolation layer are used to form an isolation structure together.

[0019] In the method for preparing the semiconductor device of the above embodiment, an isolation structure and an active column arranged alternately in sequence along a first direction are formed on a substrate; a bit line structure is formed between the active column and the substrate directly below it, and a well isolation layer is located between the bit line structure and the substrate; the bottom surface of the isolation structure is lower than the bottom surface of the well isolation layer, so that the bit line structures adjacent to each other along the first direction are effectively isolated via the isolation structure; the doping type of the well isolation layer is opposite to the doping type of the substrate directly below it, so that the well isolation layer and the substrate directly below it form a PN junction; the bit line structure includes a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer, so that the bit line structure is electrically connected to the substrate via the aforementioned PN junction, effectively reducing the occurrence of leakage; because the bit line structure is in an inverted T shape, and the bit line structures adjacent to each other along the first direction are effectively isolated via the isolation structure, it is beneficial to reduce the spacing between the bit line structures adjacent to each other along the first direction, and reduce the spacing between the active columns adjacent to each other along the first direction, so that the cross-sectional area of ​​the transistor prepared on the active column can be reduced.

[0020] In some embodiments, forming a first isolation layer and a target column alternately arranged in sequence along a first direction on a substrate includes:

[0021] forming a doped layer on the substrate;

[0022] forming active pillars arranged at intervals along a first direction on the top surface of the doped layer;

[0023] forming a dielectric layer covering the exposed surface of the active pillar and the exposed top surface of the substrate;

[0024] Etching the doped layer and the substrate based on the dielectric layer to obtain a doped portion directly below the active pillar and an isolation trench between the doped portions adjacent to each other along the first direction, and the dielectric layer retained on the sidewall of the active pillar constitutes a protective layer;

[0025] forming a first isolation layer at the bottom of the isolation trench, the top surface of which is lower than the top surface of the doped portion;

[0026] Etching portions of the doped portion on opposite sides along the first direction through the isolation trench to obtain conductive strips spaced apart along the first direction;

[0027] A bit line structure and a well isolation layer located between the bit line structure and the substrate are obtained based on the conductive strip. The bit line structure includes a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer. The well isolation layer, the bit line structure and the active column stacked in sequence along the thickness direction of the substrate are used to jointly constitute a target column.

[0028] In some embodiments, a bit line structure and a well isolation layer located between the bit line structure and a substrate are obtained based on a conductive strip, including:

[0029] forming a metal layer between the conductive strips adjacent to each other along the first direction, wherein the top surface of the metal layer is not lower than the top surface of the conductive strip;

[0030] Using the top surface of the first isolation layer as an etching stop layer, etching the portion of the metal layer between the conductive strips adjacent to each other along the first direction, and the remaining metal layer forming a seed layer;

[0031] An annealing process is performed on the seed layer, and the conductive strip is silicided to obtain a bit line structure including a middle protruding portion and a flat portion.

[0032] In some embodiments, the bit line structure further includes a metal conductive layer; a silicided conductive strip, and:

[0033] The metal conductive layer is retained on the outer surface of the silicide conductive part.

[0034] In some embodiments, the top surface of the active pillar is covered with a patterned mask layer; the protection layer also covers the outer surface of the patterned mask layer; and a metal layer is formed between conductive strips adjacent to each other along a first direction, comprising:

[0035] forming a metal material layer, the metal material layer being located between the protective layers adjacent to each other along the first direction, between the conductive strips adjacent to each other along the first direction, on the top surface of the protective layer, and on the top surface of the patterned mask layer;

[0036] The metal material layer located on the top surface of the patterned mask layer, the top surface of the protective layer, and the portion between the protective layers adjacent to each other along the first direction are etched and removed, and the remaining metal material layer is used to form a metal layer.

[0037] In some embodiments, forming a seed layer includes: using the top surface of the first isolation layer as an etching stop layer, using an anisotropic etching process to remove the portion of the metal layer located between adjacent protective layers along a first direction, and retaining the metal layer on the opposite side walls of the conductive strip along the first direction to form a seed layer.

[0038] In some embodiments, a first doping region, a channel region, and a second doping region are sequentially arranged along the thickness direction of the substrate on the active pillar, the first doping region is connected to the bit line structure directly below it, and the top surface of the isolation structure is not lower than the top surface of the second doping region; after forming the bit line structure, a second isolation layer is formed, including:

[0039] After or before removing the protection layer, forming a second isolation material layer, the second isolation material layer is located between the active pillars adjacent to each other along the first direction and covers the top surface of the patterned mask layer;

[0040] The portion of the second isolation material layer located on the top surface of the patterned mask layer and the patterned mask layer are etched and removed, and the remaining second isolation material layer is used to form a second isolation layer.

[0041] In some embodiments, an etching selectivity ratio between the first isolation layer and the dielectric layer is greater than 1; and / or an etching selectivity ratio between the substrate and the dielectric layer is greater than 1.

[0042] In some embodiments, forming a first isolation layer includes: forming a first isolation material layer, the first isolation material layer is located on the top surface of the patterned mask layer, between active pillars adjacent along the first direction, and between doped portions adjacent along the first direction; etching the first isolation material layer, and the first isolation material layer retained at the bottom of the isolation trench constitutes the first isolation layer.

[0043] In some embodiments, forming the conductive strip includes: using a wet etching process through the isolation trench to remove portions of the doped portion located above the first isolation layer and on two opposite sides along the first direction to obtain the conductive strip.

[0044] In some embodiments, forming the dielectric layer includes: forming the dielectric layer using an atomic layer deposition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present disclosure;

[0047] Figure 2-Figure 13 Schematic cross-sectional views of structures obtained in different steps in different embodiments of the present disclosure.

[0048] Description of reference numerals:

[0049] 100, substrate; 201, doping layer; 202, doping part; 203, conductive strip; 200, well isolation layer; 10, isolation structure; 110, active pillar; 1111, first semiconductor layer; 1121, second semiconductor layer; 1131, third semiconductor layer; 111, first doping region; 112, channel region; 113, second doping region; 12 / 12', bit line structure; 121, metal conductive layer; 122, silicide conductive part; 1221, middle protrusion; 1222, straight part; 1021, dielectric layer; 130, isolation groove; 102, protective layer; 101, first isolation layer; 103, second isolation layer; 141, metal layer; 140, seed layer; 1411, metal material layer; 1011, first isolation material layer. DETAILED DESCRIPTION

[0050] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0052] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the case of using "including", "having", and "comprising" described herein, another component may be added unless a clear limiting term such as "only", "consisting of", etc. is used. Unless mentioned to the contrary, a term in the singular form may include a plural form and is not to be understood as having one number.

[0053] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0054] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0055] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0056] Please note that the mutual insulation between the two in the embodiments of the present disclosure includes but is not limited to at least one of the presence of insulating material, insulating air or a gap between the two.

[0057] In some embodiments, please refer to Figure 1, provides a method for preparing a semiconductor device, comprising the following steps:

[0058] S20: providing a substrate;

[0059] S40: forming a first isolation layer and a target column arranged alternately in sequence along a first direction on the substrate; the target column comprises a well isolation layer, a bit line structure and an active column stacked in sequence along the thickness direction of the substrate; the bit line structure comprises a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer; the doping type of the well isolation layer is opposite to the doping type of the substrate directly below it; the bottom surface of the first isolation layer is lower than the bottom surface of the well isolation layer and the top surface is not higher than the top surface of the straight portion;

[0060] S60: forming a second isolation layer at least between the bit line structures adjacent to each other along the first direction, wherein the first isolation layer and the second isolation layer are used to jointly constitute an isolation structure.

[0061] Please continue to refer to Figure 1 , by forming an isolation structure and an active column arranged alternately in sequence along a first direction on a substrate; a bit line structure is formed between the active column and the substrate directly below it, and a well isolation layer is located between the bit line structure and the substrate; the bottom surface of the isolation structure is lower than the bottom surface of the well isolation layer, so that the bit line structures adjacent to each other along the first direction are effectively isolated via the isolation structure; the doping type of the well isolation layer is opposite to the doping type of the substrate directly below it, so that the well isolation layer and the substrate directly below it form a PN junction; the bit line structure includes a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer, so that the bit line structure is electrically connected to the substrate via the aforementioned PN junction, effectively reducing the occurrence of leakage; because the bit line structure is in an inverted T shape, and the bit line structures adjacent to each other along the first direction are effectively isolated via the isolation structure, it is beneficial to reduce the spacing between the bit line structures adjacent to each other along the first direction, and reduce the spacing between the active columns adjacent to each other along the first direction, so that the cross-sectional area of ​​the transistor prepared on the active column can be reduced.

[0062] In some embodiments, please refer to Figure 1 Step S20 and Figure 2-Figure 3The substrate 100 provided in step S20 may be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0063] In some embodiments, please refer to Figure 2-Figure 13 In step S40, a first isolation layer 101 and target pillars (not shown) arranged alternately in sequence along a first direction are formed on the substrate 100, including the following steps:

[0064] S41: forming a doping layer 201 on the substrate 100;

[0065] S42: forming active pillars 110 arranged at intervals along a first direction on the top surface of the doping layer 201;

[0066] S43: forming a dielectric layer 1021 covering the exposed surface of the active pillar 110 and the exposed top surface of the substrate 100;

[0067] S44: etching the doped layer 201 and the substrate 100 based on the dielectric layer 1021 to obtain the doped portion 202 directly below the active pillar 110 and the isolation trench 130 between the doped portions 202 adjacent to each other along the first direction, and the dielectric layer 1021 retained on the sidewall of the active pillar 110 is used to form the protection layer 102;

[0068] S45: forming a first isolation layer 101 having a top surface lower than a top surface of the doped portion 202 at the bottom of the isolation trench 130 ;

[0069] S46: etching portions of the doped portion 202 on opposite sides along the first direction through the isolation trench 130 to obtain conductive strips 203 spaced apart along the first direction;

[0070] S47: Based on the conductive strip 203, a bit line structure 12 and a well isolation layer 200 located between the bit line structure 12 and the substrate 100 are obtained, the bit line structure 12 includes a middle protrusion 1221 connected to the bottom surface of the active column 110, and a straight portion 1222 located between the bottom surface of the middle protrusion 1221 and the well isolation layer 200; the well isolation layer 200, the bit line structure 12 and the active column 110 stacked in sequence along the thickness direction of the substrate 100 are used to jointly constitute a target column.

[0071] As an example, please refer to Figure 1 Step S20 and Figure 2 In step S42, a first semiconductor layer 1111, a second semiconductor layer 1121 and a third semiconductor layer 1131 stacked along the thickness direction (eg, oy direction) of the substrate 100 may be sequentially formed on the top surface of the doped layer 201; wherein, Figure 2 FIG. 1 shows that the first semiconductor layer 1111 is adjacent to the doped layer 201. Please continue to refer to Figure 2 , the first semiconductor layer 1111 has the same conductivity type as the third semiconductor layer 1131, and has an opposite conductivity type to the second semiconductor layer 1121. The first semiconductor layer 1111 has the same conductivity type as the doping layer 201, and the doping layer 201 has an opposite conductivity type to the substrate 100 directly below it, so as to form a PN junction conductive channel. The first conductivity type ions can be set to be P-type ions, and the second conductivity type ions can be set to be N-type ions, or the first conductivity type ions can be set to be N-type ions, and the second conductivity type ions can be P-type ions. The doping layer 201, the first semiconductor layer 1111, the second semiconductor layer 1121 and the third semiconductor layer 1131 can be formed by an ion implantation doping process, and then an annealing process is used to repair the lattice. P-type ions can include but are not limited to at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions and indium (In) ions. N-type ions can include but are not limited to at least one of phosphorus (P) ions, arsenic (As) ions and antimony (Sb) ions. The concentration of N-type or P-type impurities can be less than or equal to 10 18 cm -3 , such as at about 10 17 cm -3 With about 10 18 cm -3 in the range between.

[0072] Please continue to refer to Figure 2 , by forming a patterned mask layer PR on the top surface of the third semiconductor layer 1131, the patterned mask layer PR has an opening pattern for defining the shape and position of the active pillar, etching the third semiconductor layer 1131, the second semiconductor layer 1121 and the first semiconductor layer 1111 based on the patterned mask layer PR, and obtaining a plurality of active pillars 110 located on the top surface of the doped layer 201, and the plurality of active pillars 110 are arranged at intervals along the first direction (for example, the ox direction). The patterned mask layer PR may include a hard mask layer (such as amorphous carbon, silicon dielectric, etc.), an anti-reflective layer and a photoresist layer sequentially stacked on the top surface of the third semiconductor layer 1131, and the patterned mask layer PR is formed through a series of steps such as exposure and development. Among them, based on Figure 2 The structure shown in FIG. is patterned to obtain Figure 3As shown, a plurality of active pillars 110 are arranged at intervals along a first direction (e.g., ox direction); the remaining first semiconductor layer 1111 is used to form the first doping region 111 of the active pillar 110, the remaining second semiconductor layer 1121 is used to form the channel region 112 of the active pillar 110, and the remaining third semiconductor layer 1131 is used to form the second doping region 113 of the active pillar 110. The materials of the first semiconductor layer 1111 and the third semiconductor layer 1131 may be silicon, and the material of the second semiconductor layer 1121 may be silicon germanium.

[0073] It should be noted that the first direction may be parallel to the ox direction shown in the figure, and the thickness direction of the substrate may be parallel to the oy direction shown in the figure.

[0074] In some embodiments, please refer to step S43 and Figure 4In step S43, a deposition process may be used to form a dielectric layer 1021 on the exposed surface of the active pillar 110 and the exposed top surface of the doped layer 201. In this embodiment, without removing the patterned mask layer PR, the dielectric layer 1021 covering the exposed surface of the patterned mask layer PR, the exposed surface of the active pillar 110, and the exposed top surface of the doped layer 201 is formed, so that the active pillar 110 is protected by the patterned mask layer PR to prevent ions in the deposition process from contaminating or damaging the active pillar 110. For example, the active pillar 110 can be protected when a metal layer is deposited and an annealing process is used to form a bit line structure, so that the metal layer can be prevented from contaminating the active pillar 110. The deposition process may include but is not limited to at least one of a chemical vapor deposition process (CVD), a physical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD). For example, in step S43, the dielectric layer 1021 may be formed by an atomic layer deposition process. The atomic layer deposition process is a film formation process that forms a film layer by layer, and each cycle has self-constraint. The dielectric layer 1021 is formed by the atomic layer deposition process, and the film thickness of the dielectric layer 1021 can be accurately controlled, which is conducive to optimizing the film formation process of the dielectric layer 1021, improving the uniformity and density of the formed dielectric layer 1021, and further optimizing the performance of the semiconductor device. In addition, the atomic layer deposition process can be performed at a relatively low temperature of less than or equal to 500° C., which can more easily control the physical properties of the dielectric layer 1021, thereby further improving the reliability and stability of the semiconductor device. The material of the dielectric layer 1021 may include silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide nitride or any combination thereof.

[0075] In some embodiments, please refer to step S44 and Figure 5, the doping layer 201 and the substrate 100 can be etched based on the dielectric layer 1021, the portion of the dielectric layer 1021 located on the top surface of the patterned mask layer PR and the portion located on the top surface of the doping layer 201 are removed, and the exposed doping layer 201 is etched downward along the thickness direction (e.g., oy direction) of the substrate 100 to obtain the doping portion 202 located directly below the active pillar 110 and the isolation trench 130 located between the doping portions 202 adjacent to each other along the ox direction, and the dielectric layer 1021 retained on the sidewalls of the active pillar 110 and the sidewalls of the patterned mask layer PR is used to form the protection layer 102. The etching process may include but is not limited to a dry etching process and / or a wet etching process, and the dry etching process may include but is not limited to any one or more of a reactive ion etching process (RIE), an inductively coupled plasma etching process (ICP), and a high concentration plasma etching process (HDP). In some embodiments, the etching selectivity ratio of the substrate 100 to the dielectric layer 1021 is greater than 1, and the etching selectivity ratio of the doping layer 201 to the dielectric layer 1021 is greater than 1, so that in the process of removing the portion of the dielectric layer 1021 located on the top surface of the patterned mask layer PR, the exposed doping layer 201 and the substrate 100 are etched downward along the oy direction to obtain the doping portions 202 and the isolation trenches 130 arranged alternately in sequence along the first direction. The conductive types of the adjacent doping portions 202 along the first direction are opposite.

[0076] In some embodiments, please refer to step S45 and Figure 6-Figure 7 , forming a first isolation layer 101, comprising:

[0077] Step S451: forming a first isolation material layer 1011, wherein the first isolation material layer 1011 is located on the top surface of the patterned mask layer PR, between the active pillars 110 adjacent to each other along the first direction, and between the doped portions 202 adjacent to each other along the first direction;

[0078] Step S452 : etching the first isolation material layer 1011 , and the first isolation material layer 1011 remaining at the bottom of the isolation trench 130 is used to form the first isolation layer 101 .

[0079] As an example, see Figure 6 In step S81, a deposition process may be used to form the first isolation material layer 1011, and the first isolation material layer 1011 may be planarized, for example, by using a chemical mechanical polishing process or a push-on etching process to process the top surface of the first isolation material layer 1011. The material of the first isolation material layer 1011 may be selected from silicon nitride, silicon oxynitride, silicon carbide, etc. and combinations thereof. The deposition process may include, but is not limited to, CVD, ALD, HDP, SOD, etc. and combinations thereof.

[0080] As an example, please refer to Figure 7In step S451, a dry etching process may be used to etch the first isolation material layer 1011. The first isolation material layer 1011 retained at the bottom of the isolation trench 130 is used to form the first isolation layer 101. The top surface of the first isolation layer 101 is lower than the top surface of the doped portion 202, so as to facilitate the subsequent lateral etching of the portion of the doped portion 202 higher than the first isolation layer 101. The dry etching process may include but is not limited to one or more of RIE, ICP and HDP. In some embodiments, the etching selectivity ratio of the first isolation layer 101 to the protective layer 102 may be set to be greater than 1 to avoid removing the protective layer 102 during the process of etching the first isolation material layer 1011 to form the first isolation layer 101, which may cause damage and contamination to the active pillar 110 in subsequent processes.

[0081] In some embodiments, please refer to Figure 8 In step S46, forming the conductive strip 203 may include:

[0082] Step S461 : using a wet etching process through the isolation trench 130 to remove the portion of the doped portion 202 located above the first isolation layer 101 and on two opposite sides along the first direction, to obtain the conductive strip 203 .

[0083] As an example, please refer to Figure 7-Figure 8 In step S461, a chemical etchant may be injected into the isolation trench 130, and a wet etching chemical may be used to chemically react with the portion of the doping portion 202 located above the first isolation layer 101 and on opposite sides along the first direction, and the product after the reaction may diffuse into the solution to be removed with the solution. The wet etching chemical may include a tetramethylammonium hydroxide (TMAH) aqueous solution or a chemical solution including ammonia (NH3), hydrogen peroxide (H2O2) and water.

[0084] In some embodiments, please refer to Figure 9-12a In step S47, a bit line structure 12 and a well isolation layer 200 located between the bit line structure 12 and the substrate 100 are obtained based on the conductive strip 203, including:

[0085] Step S471: forming a metal layer 141 between the conductive strips 203 adjacent to each other along the first direction, wherein the top surface of the metal layer 141 is flush with or higher than the top surface of the conductive strip 203;

[0086] Step S472: using the top surface of the first isolation layer 101 as an etching stop layer, etching the portion of the metal layer 141 located between the adjacent protection layers 102 along the first direction, and the remaining metal layer 141 is used to form the seed layer 140;

[0087] Step S473 : performing an annealing process on the seed layer 140 and performing a silicide process on the conductive strip 203 , thereby obtaining a bit line structure 12 including a middle protruding portion 1221 and a straight portion 1222 .

[0088] In some embodiments, please refer to Figure 12b , the bit line structure 12' also includes a metal conductive layer 121; the silicide treatment of the conductive strip 203 in step S473 also includes: retaining the metal conductive layer 121 on the outer surface of the silicide conductive portion obtained after the silicide treatment, and the metal conductive layer 121 covers the outer side wall of the middle protruding portion 1221 and the exposed top surface of the straight portion 1222 to reduce the impedance of the bit line structure 12'.

[0089] As an example, please refer to Figure 9-10 In step S471, a metal layer 141 is formed between the conductive strips 203 adjacent to each other along the first direction, comprising:

[0090] Step S4711: forming a metal material layer 1411, wherein the metal material layer 1411 is located between the protection layers 102 adjacent to each other along the first direction, between the conductive strips 203 adjacent to each other along the first direction, on the top surface of the protection layer 102, and on the top surface of the patterned mask layer PR;

[0091] Step S4712 : etching and removing the portion of the metal material layer 1411 located on the top surface of the patterned mask layer PR, the top surface of the protection layer 102 , and the portion between adjacent protection layers 102 along the first direction; the remaining metal material layer 1411 is used to form the metal layer 141 .

[0092] As an example, please refer to Fig. 9 In step S4711, a deposition process may be used to form the metal material layer 1411, and the top surface of the metal material layer 1411 may be planarized. The deposition process may include, but is not limited to, CVD, ALD, HDP, SOD, etc., and combinations thereof. The metal material layer 1411 may include, but is not limited to, titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon, etc., or combinations thereof.

[0093] As an example, please refer to Fig.10 In step S4712, a dry etching process may be used to remove the portion of the metal material layer 1411 located on the top surface of the patterned mask layer PR, the portion of the top surface of the protection layer 102, and the portion between the adjacent protection layers 102 along the first direction, to obtain a metal layer 141 whose top surface is not lower than the bottom surface of the active pillar. The dry etching process may include, but is not limited to, one or more of RIE, ICP, and HDP.

[0094] As an example, please refer to Fig.11 The step S472 of forming the seed layer 140 may include:

[0095] Step S4721: Using the top surface of the first isolation layer 101 as an etching stop layer, an anisotropic etching process is used to remove the portion of the metal layer 141 located between the protective layers 102 adjacent along the first direction, and the metal layer 141 retained on the outer side wall of the conductive strip 203 along the first direction is used to form a seed layer 140.

[0096] As an example, please refer to Fig.12a , 12b and Fig.13 In step S473, the annealing process can be a wet annealing process or a dry annealing process. Annealing is a metal heat treatment process. By slowly heating the metal to a certain temperature, keeping it for a sufficient time, and then cooling it at an appropriate speed, the hardness can be reduced, the machinability can be improved; residual stress can be reduced, the size can be stabilized, and the tendency of deformation and cracking can be reduced; the grains can be refined, the structure can be adjusted, and the structure defects can be eliminated. The temperature of the annealing process can be 800℃-1500℃, for example, the annealing temperature can be 800℃, 900℃, 1000℃, 1100℃, 1200℃, 1300℃, 1400℃ or 1500℃; the annealing gas can include at least one of H2, O2, N2, Ar and He, and the annealing time can be 1.5 hours to 2.5 hours, for example, the annealing time can be 1.5 hours, 2.0 hours or 2.5 hours. Among them, when the annealing gas includes H2 and O2, the annealing process is a wet annealing process. The annealing process can remove some defects and activated dopants caused by ion implantation. After the seed layer 140 is subjected to the annealing process, the metal conductive layer 121 formed on the surface of the silicide conductive portion 122 can effectively reduce the impedance of the bit line structure 12. Since the bit line structure 12 includes a middle protrusion 1221 connected to the bottom surface of the active pillar 110, and a straight portion 1222 located between the bottom surface of the middle protrusion 1221 and the well isolation layer 200, the longitudinal section of the bit line structure 12 parallel to the first direction is an inverted "T" shape, thereby increasing the thickness of the isolation structure formed subsequently at the corner, so as to effectively avoid leakage current or tip discharge at the corner.

[0097] In some embodiments, please refer to Fig.13 The active pillar 110 is provided with a second doping region 113, a channel region 112 and a first doping region 111 arranged in sequence along the thickness direction of the substrate 100, the first doping region 111 is adjacent to the bit line structure 12' directly below it, and the top surface of the isolation structure 10 is flush with the top surface of the second doping region 113; the forming of the second isolation layer 103 in step S60 may include:

[0098] Step S61: after or before removing the protection layer 102, forming a second isolation material layer (not shown), the second isolation material layer is located between the active pillars 110 adjacent to each other along the first direction and covers the top surface of the patterned mask layer PR;

[0099] Step S62 : etching and removing the portion of the second isolation material layer located on the top surface of the patterned mask layer PR and the patterned mask layer PR. The remaining second isolation material layer is used to form the second isolation layer 103 . The first isolation layer 101 and the second isolation layer are used to form the isolation structure 10 together.

[0100] As an example, please refer to Figure 12- Fig.13 , after removing the protective layer 102 and before removing the patterned mask layer PR, a deposition process can be used to form a second isolation material layer, the second isolation material layer is located between the active pillars 110 adjacent to each other along the first direction, between the patterned mask layers PR adjacent to each other along the first direction, and covers the top surface of the patterned mask layer PR; then, a dry etching process can be used to etch the second isolation material layer to form a second isolation layer 103, so as to facilitate the subsequent formation of a gate between the channel regions 112 adjacent to each other along the first direction. In some other embodiments, after removing the protective layer 102, a deposition process can be used to form a second isolation material layer, and then a second isolation layer 103 can be formed to meet the actual needs of various different application scenarios.

[0101] In some embodiments, please refer to Fig.13 , a gate (not shown) can be formed between the channel regions 112 adjacent to each other along the first direction, thereby forming a vertical channel transistor. Since the second doped region 113 of the vertical channel transistor is located at the top of the transistor, it does not need to be directly led out from the surface of the transistor, making it easier to form an insulating structure between transistors in the array, thereby reducing the power consumption of the semiconductor device. On the premise of ensuring the storage capacity of the semiconductor device, the volume of the semiconductor unit can be reduced, and the response speed and storage density of the semiconductor device can be improved.

[0102] In some embodiments, please refer to Fig.13 , a gate may be provided around the active pillar 110 to form a vertical gate all around transistor (VGAA transistor), thereby further reducing the size of the semiconductor unit.

[0103] It should be understood that although Figure 1 The steps in the above-mentioned process steps are shown in sequence according to arrows or step sequence indications, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1At least part of the steps in the process described above may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0104] In some embodiments, please refer to Fig.13 , provides a semiconductor device, including an isolation structure 10 and a target column (not shown) arranged alternately in sequence along a first direction on a substrate 100; the target column includes a well isolation layer 200, a bit line structure 12 and an active column 110 stacked in sequence along the thickness direction of the substrate 100; the bottom surface of the isolation structure 10 is lower than the bottom surface of the well isolation layer 200; the doping type of the well isolation layer 200 is opposite to the doping type of the substrate 100 directly below it; the bit line structure 12 includes a middle protrusion 1221 connected to the bottom surface of the active column 110, and a straight portion 1222 located between the bottom surface of the middle protrusion 1221 and the well isolation layer 200.

[0105] As an example, please refer to Fig.13 , by forming an isolation structure 10 and a target column alternately arranged in sequence along a first direction on a substrate 100; the target column includes a well isolation layer 200, a bit line structure 12 and an active column 110 stacked in sequence along the thickness direction of the substrate 100; the bottom surface of the isolation structure 10 is lower than the bottom surface of the well isolation layer 200, so that the target columns adjacent to each other in the first direction are effectively isolated via the isolation structure 10; the doping type of the well isolation layer 200 is opposite to the doping type of the substrate 100 directly below it, so that the well isolation layer 200 and the substrate 100 directly below it form a PN junction; the bit line structure 12 includes a bottom surface of the active column 110, and a bottom surface of the well isolation layer 200 is opposite to the doping type of the substrate 100 directly below it, so that the well isolation layer 200 and the substrate 100 directly below it form a PN junction; The middle protrusion 1221 connected to the surface, and the straight portion 1222 located between the bottom surface of the middle protrusion 1221 and the well isolation layer 200, facilitate the electrical connection of the bit line structure 12 with the substrate 100 via the aforementioned PN junction, and effectively reduce the occurrence of leakage; since the bit line structure 12 is in an inverted T shape, and the bit line structures 12 adjacent to each other along the first direction are effectively isolated by the isolation structure 10, it is beneficial to reduce the spacing between the bit line structures 12 adjacent to each other along the first direction, and reduce the spacing between the active pillars 110 adjacent to each other along the first direction, thereby reducing the cross-sectional area of ​​the transistor prepared on the active pillar 110.

[0106] As an example, please refer to Fig.13The orthographic projection of the middle protrusion 1221 on the top surface of the substrate 100, and the active column 110 located directly above the middle protrusion 1221 are within the orthographic projection of the top surface of the substrate 100, thereby increasing the contact area between the connection corner between the active column 110 and the middle protrusion 1221 and the isolation structure 10, and increasing the thickness of the isolation structure 10 at the corner, thereby effectively avoiding leakage current or tip discharge at the contact surface.

[0107] As an example, please refer to Fig.13 The active pillar 110 is projected onto the top surface of the substrate 100, and the bit line structure 12 located directly below the active pillar 110 is within the projection of the top surface of the substrate 100, thereby relatively increasing the longitudinal cross-sectional area of ​​the bit line structure 12 and reducing the impedance of the bit line structure 12 while keeping the volume of the semiconductor device unchanged.

[0108] As an example, please refer to Fig.13 The bit line structure 12 further includes a metal conductive layer 121 , which is located on the outer side wall surfaces of the middle protruding portion 1221 opposite to each other along the first direction and a portion of the top surface of the straight portion 1222 to reduce the impedance of the bit line structure 12 .

[0109] As an example, please refer to Fig.13 , the active pillar 110 is provided with a first doping region 111, a channel region 112 and a second doping region 113 arranged in sequence along the thickness direction of the substrate 100, the first doping region 111 is adjacent to the bit line structure 12 directly below it, and the top surface of the isolation structure 10 is not lower than the top surface of the second doping region 113; the doping type of the first doping region 111 is the same as the doping type of the well isolation layer 200 directly below it, and the doping type of the first doping region 111 is the same as the doping type of the second doping region 113. This embodiment facilitates the subsequent direct preparation of a gate surrounding the channel region 112 to prepare a vertical gate-all-around transistor, reduces the complexity of the vertical gate-all-around transistor preparation process, and improves the performance and reliability of the vertical gate-all-around transistor.

[0110] As an example, please refer to Fig.13 The well isolation layer 200 forms a PN junction with the substrate 100 directly thereunder; the first doped region 111 is used to form a source contact region, and the second doped region 113 is used to form a drain contact region; or, the first doped region 111 is used to form a drain contact region, and the second doped region 113 is used to form a source contact region, so as to meet the actual application requirements of various different scenarios.

[0111] As an example, please refer to Fig.13, the bit line structure 12 extends along the second direction; the second direction intersects with the first direction, and the first direction and the second direction are both perpendicular to the thickness direction of the substrate 100; the active pillars 110 adjacent along the second direction share the bit line structure 12 directly below the active pillars 110 to reduce the complexity of the preparation process of the bit line structure 12 in the stacked structure.

[0112] In some embodiments, a memory is provided, including the semiconductor device described in the aforementioned embodiments. Since the bit line structure is in an inverted T shape and the bit line structures adjacent along the first direction are effectively isolated by the isolation structure, it is beneficial to reduce the spacing between the bit line structures adjacent along the first direction, and reduce the spacing between the active pillars adjacent along the first direction, thereby reducing the cross-sectional area of ​​the transistor prepared on the active pillar.

[0113] In some embodiments, an electronic device is provided, including the memory in the aforementioned embodiments, so as to improve the performance and reliability of the electronic device while ensuring that the volume of the electronic device does not increase. The electronic device is, for example, but not limited to, suitable types of electronic products such as consumer electronic products, household electronic products, vehicle-mounted electronic products, and financial terminal products. Among them, consumer electronic products are such as mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Household electronic products are such as smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products are such as vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products are such as ATM machines, self-service terminals, etc.

[0114] Please note that for the sake of simplicity of the specification, in the structural schematic diagrams given in the embodiments below, unless the corresponding cross-sectional structural schematic diagrams are given separately, other structural schematic diagrams of different perspectives of structures related to the inventive points of the embodiments of the present disclosure can refer to each other.

[0115] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0116] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0117] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: It includes isolation structures and target pillars which are arranged alternately in sequence along a first direction on a substrate; The target column includes a well isolation layer, a bit line structure and an active column stacked in sequence along the thickness direction of the substrate; The bottom surface of the isolation structure is lower than the bottom surface of the well isolation layer; the doping type of the well isolation layer is opposite to the doping type of the substrate directly below it; The bit line structure includes a middle protruding portion connected to the bottom surface of the active pillar, and a straight portion located between the bottom surface of the middle protruding portion and the well isolation layer.

2. The semiconductor device according to claim 1, wherein: The orthographic projection of the middle protrusion on the top surface of the substrate and the active pillar located directly above the middle protrusion are within the orthographic projection of the top surface of the substrate.

3. The semiconductor device according to claim 1, wherein: The orthographic projection of the active pillar on the top surface of the substrate, and the bit line structure located directly below the active pillar are within the orthographic projection of the top surface of the substrate.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The bit line structure further comprises: The metal conductive layer is located on the outer side wall surfaces of the middle protruding portion opposite to each other along the first direction and on a part of the top surface of the straight portion.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The active pillar is provided with a first doping region, a channel region and a second doping region sequentially arranged along the thickness direction of the substrate, the first doping region is adjacent to the bit line structure directly below it, and the top surface of the isolation structure is not lower than the top surface of the second doping region; The doping type of the first doping region is the same as the doping type of the well isolation layer directly thereunder, and the doping type of the first doping region is the same as the doping type of the second doping region.

6. The semiconductor device according to claim 5, characterized in that The well isolation layer forms a PN junction with the substrate directly below it; The first doped region is used to form a source contact region, and the second doped region is used to form a drain contact region; or The first doped region is used to form a drain contact region, and the second doped region is used to form a source contact region.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that: The bit line structure extends along a second direction; the second direction intersects with the first direction and both are perpendicular to the thickness direction of the substrate; The active pillars adjacent to each other along the second direction share a bit line structure directly below the active pillars.

8. A memory, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 7.

9. An electronic device, characterized in that: include: The memory as claimed in claim 8.

10. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; A first isolation layer and a target column are formed on the substrate, which are alternately arranged in sequence along a first direction; the target column comprises a well isolation layer, a bit line structure and an active column which are stacked in sequence along the thickness direction of the substrate; the bit line structure comprises a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer; the doping type of the well isolation layer is opposite to the doping type of the substrate directly below it; the bottom surface of the first isolation layer is lower than the bottom surface of the well isolation layer and the top surface is not higher than the top surface of the straight portion; A second isolation layer is formed at least between the bit line structures adjacent to each other along the first direction, and the first isolation layer and the second isolation layer are used to jointly constitute an isolation structure.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The first isolation layer and the target pillars are formed on the substrate and are alternately arranged in sequence along the first direction, comprising: forming a doping layer on the substrate; forming active pillars arranged at intervals along a first direction on the top surface of the doped layer; forming a dielectric layer covering the exposed surface of the active pillar and the exposed top surface of the substrate; Etching the doped layer and the substrate based on the dielectric layer to obtain a doped portion directly below the active pillar and an isolation trench between the doped portions adjacent to each other along the first direction, and the dielectric layer retained on the sidewall of the active pillar constitutes a protective layer; forming a first isolation layer at the bottom of the isolation trench, the top surface of which is lower than the top surface of the doped portion; Etching portions of the doped portion on opposite sides along the first direction through the isolation trench to obtain conductive strips spaced apart along the first direction; Based on the conductive strip, a bit line structure and a well isolation layer located between the bit line structure and the substrate are obtained, wherein the bit line structure includes a middle protrusion connected to the bottom surface of the active column, and a straight portion located between the bottom surface of the middle protrusion and the well isolation layer; the well isolation layer, the bit line structure and the active column stacked in sequence along the thickness direction of the substrate are used to jointly constitute the target column.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The method of obtaining a bit line structure based on the conductive strip and a well isolation layer between the bit line structure and the substrate comprises: forming a metal layer between the conductive strips adjacent to each other along the first direction, wherein a top surface of the metal layer is not lower than a top surface of the conductive strip; Using the top surface of the first isolation layer as an etching stop layer, etching the portion of the metal layer located between the conductive strips adjacent to each other along the first direction, and the remaining metal layer forming a seed layer; An annealing process is performed on the seed layer, and the conductive strip is silicidized to obtain a bit line structure including the middle protruding portion and the straight portion.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The bit line structure further comprises a metal conductive layer; the silicide treatment of the conductive strip further comprises: The metal conductive layer remains on the outer surface of the silicide conductive part obtained after the silicidation treatment.

14. The method for preparing a semiconductor device according to any one of claims 10 to 13, characterized in that: The top surface of the active pillar is covered with a patterned mask layer; the protection layer also covers the outer surface of the patterned mask layer; the metal layer is formed between the conductive strips adjacent to each other along the first direction, comprising: forming a metal material layer, wherein the metal material layer is located between the protective layers adjacent to each other along the first direction, between the conductive strips adjacent to each other along the first direction, on the top surface of the protective layer, and on the top surface of the patterned mask layer; The portion of the metal material layer located on the top surface of the patterned mask layer, the top surface of the protective layer, and the portion between the protective layers adjacent to each other along the first direction are etched and removed, and the remaining metal material layer is used to form the metal layer.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: Forming the seed layer comprises: The top surface of the first isolation layer is used as an etching stop layer, and an anisotropic etching process is used to remove the portion of the metal layer located between the adjacent protective layers along the first direction, and the metal layer retained on the opposite side walls of the conductive strip along the first direction is used to form the seed layer.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: The active pillar is provided with a first doping region, a channel region and a second doping region sequentially arranged along the thickness direction of the substrate, the first doping region is connected to the bit line structure directly below it, and the top surface of the isolation structure is not lower than the top surface of the second doping region; After forming the bit line structure, forming the second isolation layer includes: After or before removing the protection layer, forming a second isolation material layer, wherein the second isolation material layer is located between the active pillars adjacent to each other along the first direction and covers the top surface of the patterned mask layer; The portion of the second isolation material layer located on the top surface of the patterned mask layer and the patterned mask layer are etched and removed, and the remaining second isolation material layer is used to form the second isolation layer.

17. The method for preparing a semiconductor device according to any one of claims 11 to 13, characterized in that: The etching selectivity ratio between the first isolation layer and the dielectric layer is greater than 1; and / or The etching selectivity ratio between the substrate and the dielectric layer is greater than 1.

18. The method for preparing a semiconductor device according to claim 14, characterized in that: Forming the first isolation layer includes: forming a first isolation material layer, wherein the first isolation material layer is located on a top surface of the patterned mask layer, between the active pillars adjacent to each other along the first direction, and between the doped portions adjacent to each other along the first direction; The first isolation material layer is etched, and the first isolation material layer remaining at the bottom of the isolation trench constitutes the first isolation layer.

19. The method for preparing a semiconductor device according to any one of claims 10 to 13, characterized in that: Forming the conductive strips includes: The conductive strips are obtained by removing the portions of the doped portion located above the first isolation layer and on two opposite sides along the first direction through the isolation trenches using a wet etching process.

20. The method for preparing a semiconductor device according to any one of claims 11 to 13, characterized in that: Forming the dielectric layer includes: The dielectric layer is formed by an atomic layer deposition process.

Images