Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a conductive layer, a laminated structure and a channel structure. The laminated structure is located on one side of the conductive layer and comprises gate layers and dielectric layers which are alternately stacked. The channel structure penetrates through the laminated structure in the stacking direction and extends into the conductive layer, the channel structure comprises a first part and a second part which are connected with each other in the stacking direction, the first part penetrates through the laminated structure in the stacking direction and comprises a first channel layer and a functional layer from inside to outside, and the second part extends into the conductive layer in the stacking direction and comprises a second channel layer and a functional layer from inside to outside. And the first channel layer and the second channel layer are arranged from inside to outside.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] In order to achieve higher storage density, the number of stacked layers in semiconductor devices will increase significantly, for example, from 32 layers to 64 layers, then to 96 layers or even 128 layers, etc. However, as the number of stacked layers in semiconductor devices increases, their stability will decrease accordingly.

[0003] Therefore, how to improve the stability of semiconductor devices while improving the storage density of semiconductor devices is a problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and a storage system that can at least partially solve the above-mentioned problems or other problems existing in the related art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a conductive layer; a stacked structure located on one side of the conductive layer, the stacked structure including alternately stacked gate layers and dielectric layers; and a channel structure that penetrates the stacked structure along a stacking direction and extends into the conductive layer, the channel structure including a first part and a second part connected to each other along the stacking direction, wherein the first part penetrates the stacked structure along the stacking direction and includes a first channel layer and a functional layer from the inside to the outside; and the second part extends into the conductive layer along the stacking direction and includes the first channel layer and the second channel layer from the inside to the outside.

[0006] In one embodiment of the present application, the second channel layer and the conductive layer have the same thickness in the stacking direction.

[0007] In one embodiment of the present application, in a direction perpendicular to the stacking direction, a thickness of the second channel layer is greater than a thickness of the first channel layer.

[0008] In one embodiment of the present application, the semiconductor material layer included in the first channel layer and the semiconductor material layer included in the second channel layer both contain the same type of doping elements; or the semiconductor material layer included in the first channel layer, the semiconductor material layer included in the second channel layer and the semiconductor material layer included in the conductive layer all contain the same type of doping elements.

[0009] In one embodiment of the present application, a doping concentration of a doping element of the second channel layer is greater than a doping concentration of a doping element of the first channel layer.

[0010] In one embodiment of the present application, the semiconductor device also includes a substrate located on the other side of the conductive layer opposite to the one side; and the channel structure also includes a channel filling layer surrounded by the first channel layer, wherein the channel filling layer penetrates the stacked structure and the conductive layer along the stacking direction and extends into the substrate.

[0011] In one embodiment of the present application, the semiconductor device also includes a gate line gap structure having a spacing with the channel structure in a direction perpendicular to the stacking direction, and the gate line gap structure includes a first section and a second section connected to each other along the stacking direction, wherein the first section penetrates the stacked structure along the stacking direction and includes a gap filling layer and a first sidewall isolation layer arranged between the stacked structure and the gap filling layer; and the second section penetrates at least the conductive layer along the stacking direction and includes the gap filling layer and a second sidewall isolation layer arranged between the conductive layer and the gap filling layer.

[0012] In one embodiment of the present application, the first sidewall spacer and the second sidewall spacer are made of different materials.

[0013] In one embodiment of the present application, the second sidewall isolation layer and the second channel layer include the same material.

[0014] In one embodiment of the present application, in a direction perpendicular to the stacking direction, the thickness of the second channel layer is greater than or equal to the thickness of the functional layer.

[0015] In one embodiment of the present application, the second portion penetrates the conductive layer along the stacking direction.

[0016] In one embodiment of the present application, different second portions of the channel structures have different thicknesses along the stacking direction.

[0017] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a stacked structure and an initial channel structure on a first side of a substrate, wherein the substrate comprises a conductive layer, the stacked structure comprises alternately stacked gate layers and dielectric layers, and the initial channel structure penetrates the stacked structure along a stacking direction and at least extends into the conductive layer; from a second side opposite to the first side, removing a portion of the substrate to expose the conductive layer, and removing at least a portion of the initial functional layer of the initial channel structure located in the conductive layer to expose the initial first channel layer of the initial channel structure; forming an initial second channel layer, wherein the initial second channel layer at least covers the exposed initial first channel layer; and removing a portion of the initial first channel layer and a portion of the initial second channel layer to form a first channel layer and a second channel layer.

[0018] In one embodiment of the present application, after removing part of the initial first channel layer and part of the initial second channel layer, the method further includes: planarizing the conductive layer and the initial first channel layer and the initial second channel layer remaining after the removal.

[0019] In one embodiment of the present application, the initial channel structure also includes an initial channel filling layer surrounded by the initial first channel layer. After removing part of the initial first channel layer and part of the initial second channel layer, the method also includes: removing part of the initial channel filling layer, wherein the removed part of the initial channel filling layer corresponds to the removed part of the initial first channel layer.

[0020] In one embodiment of the present application, after removing part of the initial first channel layer and part of the initial second channel layer, the method further comprises: using the same type of doping elements to dope the initial first channel layer and the initial second channel layer remaining after the removal process.

[0021] In one embodiment of the present application, the substrate includes a conductive layer, and the method further includes: doping the conductive layer with the same type of doping elements.

[0022] In one embodiment of the present application, the stacked structure also includes an initial gate line gap structure having a spacing with the channel structure in a direction perpendicular to the stacking direction, and the initial gate line gap structure penetrates the stacked structure along the stacking direction and extends to the substrate. The method also includes: in a process of removing a portion of the substrate and a portion of the initial functional layer of the initial channel structure extending into the substrate, removing a portion of the initial first sidewall isolation layer of the initial gate line gap structure extending into the substrate to expose the gap filling layer of the initial gate line gap structure; using the initial second channel layer to cover the exposed gap filling layer; and removing a portion of the initial second channel layer covering the gap filling layer to form a second sidewall isolation layer, wherein the second sidewall isolation layer is located between the conductive layer and the gap filling layer.

[0023] In one embodiment of the present application, a plurality of first openings are formed in the conductive layer by removing at least a portion of the initial functional layer of the initial channel structure located in the conductive layer, and before forming an initial second channel layer, wherein the initial second channel layer at least covers the exposed initial first channel layer, the method further includes: expanding the size of the first opening along a direction perpendicular to the stacking direction to form a second opening; wherein the initial second channel layer at least fills the second opening.

[0024] Another aspect of the present application provides a storage system, which includes a controller and the semiconductor device provided in one aspect of the present application, and the controller is used to store data in the semiconductor device.

[0025] Another aspect of the present application provides an electronic device, including the storage system provided by another aspect of the present application.

[0026] According to a semiconductor device, a method for preparing a semiconductor device, a storage system and an electronic device provided by at least one embodiment of the present application, the channel structure may include a first channel layer that penetrates the stacked structure along the stacking direction and extends into the conductive layer, and a second channel layer located between the first channel layer and the conductive layer. The second channel layer can enhance the effective connection between the first channel layer and the conductive layer, improve the stability and conductivity of the channel structure, and thereby improve the stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0028] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of the present application;

[0029] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of the present application;

[0030] Figure 3-Figure 6 Each of them is a schematic diagram of an intermediate in the process of preparing a semiconductor device;

[0031] Figure 7 is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present application;

[0032] Figure 8 is a schematic cross-sectional view of a structure formed after a stacked structure and an initial channel structure are formed on a substrate according to a preparation method in one embodiment of the present application;

[0033] Fig. 9 is a cross-sectional schematic diagram of a structure formed after removing a portion of the substrate according to a preparation method in one embodiment of the present application;

[0034] Fig.10 is a schematic cross-sectional view of a structure formed after removing a portion of an initial functional layer of an initial channel structure extending into a substrate according to a preparation method in one embodiment of the present application;

[0035] Fig.11 is a schematic cross-sectional view of a structure formed after forming an initial second channel layer according to a preparation method in one embodiment of the present application;

[0036] Fig.12 is a schematic cross-sectional view of a structure formed after forming a second channel layer according to a preparation method in one embodiment of the present application;

[0037] Fig.13 is a schematic cross-sectional view of a structure formed after removing a portion of an initial trench filling layer according to a preparation method in one embodiment of the present application; and

[0038] Fig.14 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first channel layer discussed in this application may also be referred to as the second channel layer, and vice versa.

[0041] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0042] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0043] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0044] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0045] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0046] Figure 1is a schematic cross-sectional view of a semiconductor device 1000 according to an embodiment of the present application. Figure 2 is a schematic cross-sectional view of a semiconductor device 1000 according to an embodiment of the present application.

[0047] like Figure 1 and Figure 2 As shown, the semiconductor device 1000 may include: a conductive layer 110, a stacked structure 200, and a channel structure 300. The stacked structure 200 is located on one side of the conductive layer 110, for example, disposed on the conductive layer 110, and includes a gate layer 220 and a dielectric layer 210 that are alternately stacked. The channel structure 300 penetrates the stacked structure 200 along the stacking direction (z direction) of the stacked structure 200 and extends into the conductive layer 110. The channel structure 300 includes a first portion 301 and a second portion 302 connected to each other along the z direction. The first portion 301 penetrates the stacked structure 200 along the z direction and may include a first channel layer 330 and a functional layer 320 from the inside to the outside. The second portion 302 extends into the conductive layer 110 along the z direction and may include a first channel layer 330 and a second channel layer 350 from the inside to the outside.

[0048] It should be noted that Figure 1 and Figure 2 To facilitate observation of the relationship between the conductive layer 110 and the channel structure 300, the complete structure of the stacked structure 200 is not shown. For example, multiple gate layers 220 and multiple dielectric layers 210 alternately stacked along the z direction are omitted, and only the gate layers 220 and dielectric layers 210 near the conductive layer 110 are shown.

[0049] In other words, the channel structure 300 may include a first channel layer 330 that penetrates the stacked structure 200 along the z direction and extends into the conductive layer 110, and a second channel layer 350 located between the first channel layer 330 and the conductive layer 110. The second channel layer 350 can enhance the effective connection between the first channel layer 330 and the conductive layer 110, thereby improving the stability and conductivity of the channel structure 300, and thereby improving the stability of the semiconductor device 1000.

[0050] Specifically, a semiconductor device may generally include a common source connected to a channel layer, and the common source is used to form a circuit loop for conducting a memory cell in the semiconductor device. However, as the number of stacked layers of the stacked structure in the semiconductor device increases, the stability of the common source decreases, and the difficulty of the manufacturing process increases. In order to at least partially solve the above problems, according to a semiconductor device provided in at least one embodiment of the present application, the common source may be arranged on the back side of the stacked structure to form a backside source.

[0051] As will be combined below Figures 3 to 6An implementation method for preparing a semiconductor device is described. As the number of stacked layers increases, the depth of the channel hole accommodating the channel layer gradually increases. In the process of forming a conductive layer (which can be understood as a back source) connected to the channel layer on the back side, the difficulty of the required processes such as thinning and opening holes is gradually increasing, and it is easy to damage or destroy the intermediate of the semiconductor device during the implementation of the above-mentioned back process. In addition, the pre-formed channel layer may also be contaminated during the formation of the conductive layer. Therefore, a low-cost, easy-to-operate process for forming a channel layer and a conductive layer connected to the channel layer and a corresponding device structure are needed to enhance the effective connection between the channel layer and the conductive layer while having a relatively large process operable window, simpler process steps and lower cost.

[0052] Figure 3-Figure 6 Each is a schematic diagram of an intermediate in the process of preparing a semiconductor device.

[0053] Figure 3 A schematic structural diagram of an intermediate body 101 formed by forming a stacked structure 20 and a channel structure 30 on a substrate (not shown), flipping the intermediate body 101 by 180°, and then removing the intermediate body 101 from the substrate.

[0054] like Figure 3 As shown, the channel structure 30 penetrates the stacked structure 20 along the z direction and extends into the substrate. After the substrate is removed, the bottom of the channel structure 30 is exposed.

[0055] The stacked structure 20 includes gate layers 22 and dielectric layers 21 alternately stacked along the z direction. The dielectric layer 21 may include at least one dielectric material layer. The gate layer 22 may include a conductive material layer, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide.

[0056] The channel structure 30 may include, from the inside to the outside, a channel filling layer 34, a channel layer 33 and a functional layer 32. The channel filling layer 34, the channel layer 33 and the functional layer 32 all penetrate the stacked structure 20 along the z direction and extend into the substrate.

[0057] The channel filling layer 34 may also include an insulating gap. By controlling the channel filling process, a plurality of insulating gaps are formed in the channel filling layer 34, and structural stress can be alleviated. The functional layer 32 is a composite layer structure, which may include a blocking layer, a charge trapping layer, and a tunneling layer. The blocking layer may include one or more layers, and the one or more layers may include one or more materials. The material for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The charge trapping layer may include one or more layers, and the one or more layers may include one or more materials. The material for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. The tunneling layer may include one or more layers, and the one or more layers may include one or more materials. The material for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc.

[0058] Figure 4 A schematic structural diagram of the intermediate body 102 formed by removing a portion of the functional layer 32 and exposing at least the bottom of the channel layer 33 .

[0059] like Figure 3 and Figure 4 As shown, a portion of the substrate and a portion of the functional layer 32 and a portion of the channel layer 33 corresponding to the removed portion of the substrate can be removed by, for example, a dry etching process or a combination of dry and wet etching processes to form a retained channel layer 33' and a portion of the functional layer 32 corresponding to the retained channel layer 33'.

[0060] Afterwards, a portion of the functional layer 32 may be further removed by, for example, a dry etching process or a combination of a dry etching process and a wet etching process to form a retained functional layer 32′ and a gap 01 ( Figure 4 The portion of the functional layer removed in the above two steps includes the bottom of the functional layer 32 and a portion of the sidewall adjacent to the bottom. After removing the portion of the functional layer 32, a portion of the sidewall of the retained channel layer 33' can be exposed ( Figure 4 The part enclosed by the dotted circle in the middle).

[0061] In the above-mentioned process of removing part of the substrate and part of the functional layer 32 and part of the channel layer 33 corresponding to the removed part of the substrate, part of the channel layer 33 is removed, which can be understood as the channel layer 33 is opened, thereby exposing the retained channel layer 33' toward the inner wall of the channel filling layer 34, resulting in the retained channel layer 33' possibly being contaminated in subsequent processes, for example, by the gas used in the dry etching process or the etchant used in the wet etching process.

[0062] Figure 5FIG. 1 is a schematic structural diagram of an intermediate body 103 formed after forming a gap filling layer 35 .

[0063] like Figure 4 and Figure 5 As shown, the gap filling layer 35 can be filled in the gap 01 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or any combination thereof.

[0064] As an option, an ALD thin film deposition process may be used to fill the gap 01 with a gap filling layer 35. The material of the gap filling layer 35 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-K dielectric material such as aluminum oxide or hafnium oxide.

[0065] However, if Figure 4 As shown, the process window (gap 01 ) for filling the gap filling layer 35 is too small, which increases the difficulty of forming the gap filling layer 35 by filling the gap 01 in actual operation.

[0066] Figure 6 It is a schematic structural diagram of the intermediate body 104 formed after the conductive covering layer 11 is formed.

[0067] like Figure 5 and Figure 6 As shown, a conductive capping layer 11 may be formed on the back of the intermediate body 104 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The conductive capping layer 11 is connected to the reserved channel layer 33 ′ and is the back source of the semiconductor device.

[0068] refer to Figure 3 , Figure 5 and Figure 6 It is not difficult to find that the retained channel layer 33' connected to the conductive covering layer 11 is only a small part of the channel layer 33 extending into the substrate along the z direction. Therefore, the area of ​​the effective contact surface between the conductive covering layer 11 and the retained channel layer 33' is too small, which has an adverse effect on the stability and conductivity of the channel structure.

[0069] Reference again Figure 1 and Figure 2In order to at least partially solve the above problems, the present application provides a semiconductor device 1000. The second channel layer 350 is located between the first channel layer 330 and the conductive layer 110. The second channel layer 350 can enhance the effective connection between the first channel layer 330 and the conductive layer 110, improve the stability and conductivity of the channel structure 300, and thus improve the stability of the semiconductor device 1000.

[0070] In addition, in the subsequent method for forming the semiconductor device 1000, the process of forming the second channel layer and the conductive layer does not require opening the channel layer, thereby reducing the possibility of the channel layer being contaminated in the subsequent process, thereby enhancing the conductive performance of the channel structure. In addition, the second channel layer can be formed by pre-forming an initial second channel layer on the surface of the conductive layer and removing most of the initial second channel layer, thereby having a larger formation process window, simplifying the difficulty of the operation process, and improving the stability and conductivity of the channel structure.

[0071] In one embodiment of the present application, the plurality of channel structures 300 may have different extension lengths in the z direction. In other words, the second portions 302 of different channel structures 300 may have different thicknesses along the z direction, for example, the plurality of second portions 302 may only extend into the conductive layer 110 along the z direction; or the plurality of second portions 302 may penetrate the conductive layer 110 along the z direction; or some of the plurality of second portions 302 only extend into the conductive layer 110, while others penetrate the conductive layer 110. Therefore, the semiconductor device 1000 provided in the present application does not limit the consistency of the extension length of the channel hole accommodating the channel structure 300 in the z direction, thereby improving the process margin of forming the channel hole using the deep hole etching process during the preparation process, and reducing the preparation cost and process difficulty.

[0072] Accordingly, the plurality of first channel layers 330 have different extension lengths in the z direction, for example, a portion of the plurality of first channel layers 330 may only extend into the conductive layer 110, and another portion of the plurality of first channel layers 330 may penetrate the conductive layer 110. In order to improve the stability of the connection between the conductive layer 110 and the plurality of first channel layers 330 having different extension lengths in the z direction, the second channel layer 350 and the conductive layer 110 may have the same thickness in the z direction, so that the second channel layer 350 and the conductive layer 110 form full contact with each other, have the largest possible effective contact area, and thus improve the stability of the connection between the conductive layer 110 and the plurality of first channel layers 330.

[0073] In addition, in one embodiment of the present application, in a direction perpendicular to the z direction, such as the x direction or the y direction, the thickness D1 of the second channel layer 350 may be greater than the thickness D2 of the first channel layer 330. The thickness D1 of the second channel layer 350 is relatively large, so the opening for accommodating the second channel layer 350 is also relatively large. During the preparation process, the process of forming the initial second channel layer on the back side of the semiconductor device intermediate and in the opening can reduce the difficulty of forming the initial second channel layer by filling the opening in actual operation because the opening is relatively large, and improve the density of the second channel layer 350 formed based on the initial second channel layer, so that the stability and conductivity of the connection between the conductive layer 110 and the plurality of first channel layers 330 are improved.

[0074] In one embodiment of the present application, the first channel layer 330 includes a semiconductor material layer, and the second channel layer 350 also includes a semiconductor material layer. The semiconductor material layer included in the first channel layer 330 and the semiconductor material layer included in the second channel layer 350 may be the same or different, and the present application does not limit this. The semiconductor material layer included in the first channel layer 330 and the semiconductor material layer included in the second channel layer 350 can be prepared by selecting any suitable semiconductor material, and the semiconductor material includes but is not limited to crystalline silicon or silicide. In the case where the semiconductor material layer included in the first channel layer 330 and the semiconductor material layer included in the second channel layer 350 are the same, for example, a polycrystalline silicon material layer can be used.

[0075] In addition, the conductive layer 110 may also include a semiconductor material layer, and the semiconductor material layer included in the conductive layer 110, the semiconductor material layer included in the first channel layer 330, and the semiconductor material layer included in the second channel layer 350 may be the same or different, and this application does not limit this. The semiconductor material forming the semiconductor material layer included in the conductive layer 110 includes, but is not limited to, crystalline silicon or silicide.

[0076] In addition, the semiconductor material layer included in the first channel layer 330 and the semiconductor material layer included in the second channel layer 350 both contain the same type of doping elements; or the semiconductor material layer included in the first channel layer 330, the semiconductor material layer included in the second channel layer 350 and the semiconductor material layer included in the conductive layer 110 all contain the same type of doping elements.

[0077] Specifically, the doping elements may include two types (understandable conductivity types), the first type may be P-type, and the second type may be N-type. As an option, the semiconductor material layer included in the first channel layer 330 and the semiconductor material layer included in the second channel layer 350 may be doped with any suitable, for example, N-type dopant (e.g., phosphorus (P), arsenic (Ar) or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As another option, the semiconductor material layer included in the first channel layer 330 and the semiconductor material layer included in the second channel layer 350 may be doped with any suitable, for example, P-type dopant (e.g., boron (B), gallium (Ga) or indium (In)) to absorb free electrons and increase the conductivity of the intrinsic semiconductor.

[0078] In addition, as an option, the semiconductor material layer included in the first channel layer 330, the semiconductor material layer included in the second channel layer 350, and the semiconductor material layer included in the conductive layer 110 may be doped with any suitable, for example, N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As another option, the semiconductor material layer included in the first channel layer 330, the semiconductor material layer included in the second channel layer 350, and the semiconductor material layer included in the conductive layer 110 may be doped with any suitable, for example, P-type dopant (e.g., boron (B), gallium (Ga), or indium (In)) to absorb free electrons and increase the conductivity of the intrinsic semiconductor.

[0079] On this basis, in some embodiments of the present application, the doping concentration of the doping element of the second channel layer 350 may be greater than the doping concentration of the doping element of the first channel layer 330 .

[0080] Taking a three-dimensional memory as an example, since the channel layer of a semiconductor device is a key channel for carrier migration, the current conduction capability of the channel layer has an important influence on the erase and read performance of the three-dimensional memory. The first channel layer is a non-doped semiconductor material layer or a relatively low-concentration doped semiconductor material layer, which can form a large difference in doping concentration of conductive doping elements with the second channel layer and the conductive layer, respectively, so that the concentration of carriers in the first channel layer can be much smaller than the concentration of carriers in the second channel layer and the conductive layer, which is conducive to the flow of carriers mainly composed of conductive doping elements toward the first channel layer, so that the mobility of carriers in the first channel layer can be maintained at a high level, thereby improving the current conduction capability of the channel layer.

[0081] Reference again Figure 2In some embodiments of the present application, the semiconductor device 1000 further includes a substrate 120 located on the other side of the conductive layer 110 opposite to the one side; the channel structure 300 further includes a channel filling layer 340 surrounded by the first channel layer 330, wherein the channel filling layer 340 penetrates the stacked structure 200 and the conductive layer 110 along the z direction and extends into the substrate 120.

[0082] As mentioned above, in the above Figures 3 to 6 In the process of preparing the semiconductor device shown, in the process of removing part of the substrate and part of the functional layer 32 and part of the channel layer 33 corresponding to the removed part of the substrate, the channel layer 33 is opened, resulting in the inner wall of the retained channel layer 33' toward the channel filling layer 34 being exposed, which may be contaminated in subsequent processes.

[0083] In at least one embodiment of the present application, the initial first channel layer used to form the first channel layer 330 and the initial second channel layer used to form the second channel layer 350 may be removed together, and the pre-formed channel filling layer 340 may not be removed during the removal process and may be retained in the finally formed semiconductor device 1000. Therefore, the channel filling layer 340 can protect the inner wall of the first channel layer 330, reduce the possibility of the first channel layer 330 being contaminated during the preparation of the semiconductor device 1000, and improve the conductivity of the first channel layer 330.

[0084] In addition, refer again Figure 1 In at least one embodiment of the present application, the semiconductor device 1000 further includes a gate line gap structure 400 having a spacing with the channel structure 300 in a direction perpendicular to the z direction (for example, the x direction or the y direction), and the gate line gap structure 400 may include a first section 401 and a second section 402 connected to each other along the z direction, wherein the first section 401 penetrates the stacked structure 200 along the z direction and includes a gap filling layer 430 and a first sidewall isolation layer 420 disposed between the stacked structure 200 and the gap filling layer 430; and the second section 402 penetrates at least the conductive layer 110 along the z direction and includes a gap filling layer 430 and a second sidewall isolation layer 440 disposed between the conductive layer 110 and the gap filling layer 430.

[0085] Optionally, the first sidewall spacer 420 may be spaced apart from the stacked structure 200 by a gap filling layer 430, including but not limited to an insulating dielectric material layer such as a silicon oxide layer, a high dielectric constant dielectric layer, etc. In addition, the gap filling layer 430 may be a semiconductor layer such as a polysilicon layer. Using a semiconductor layer such as a polysilicon layer as the filling body of the gate line gap structure 400 can effectively reduce the deformation of the semiconductor device 1000. Alternatively, the gap filling layer 430 may be an insulating dielectric material layer such as a silicon oxide layer.

[0086] As an option, the first sidewall spacer 420 and the second sidewall spacer 440 may include different materials.

[0087] As another option, the second sidewall spacer 440 and the second channel layer 350 may include the same material. Specifically, the second sidewall spacer 440 and the second channel layer 350 may be formed in the same process during the preparation of the semiconductor device 1000, thereby simplifying the steps of the preparation process and reducing the preparation cost.

[0088] In at least one embodiment of the present application, in a direction perpendicular to the z direction (e.g., the x direction and the y direction), the thickness of the second channel layer 350 is greater than or equal to the thickness of the functional layer 320. As described above, increasing the size of the opening for accommodating the second channel layer 350 can reduce the difficulty of forming the initial second channel layer by filling the opening in actual operation, and improve the density of the second channel layer 350 formed based on the initial second channel layer. Therefore, when the thickness of the second channel layer 350 is greater than or equal to the thickness of the functional layer 320, the size of the opening for accommodating the second channel layer 350 can be ensured to be relatively large, thereby improving the stability and conductivity of the connection formed between the conductive layer 110 and the multi-first channel layer 330 through the second channel layer 3250.

[0089] Therefore, according to the semiconductor device provided by at least one embodiment of the present application, the channel structure may include a first channel layer that penetrates the stacked structure along the stacking direction and extends into the conductive layer, and a second channel layer located between the first channel layer and the conductive layer. The second channel layer can enhance the effective connection between the first channel layer and the conductive layer, improve the stability and conductivity of the channel structure, and thereby improve the stability of the semiconductor device.

[0090] Figure 7 FIG. 2 is a flow chart of a method 2000 for manufacturing a semiconductor device according to an embodiment of the present application. Figure 7 As shown, the present application provides a method 2000 for preparing a semiconductor device, comprising:

[0091] S1, forming a stacked structure and an initial channel structure on a first side of a substrate, wherein the substrate includes a conductive layer, the stacked structure includes alternately stacked gate layers and dielectric layers, and the initial channel structure penetrates the stacked structure along a stacking direction and extends at least into the conductive layer.

[0092] S2, from a second side opposite to the first side, removing a portion of the substrate to expose the conductive layer, and removing at least a portion of the initial functional layer of the initial channel structure located in the conductive layer to expose the initial first channel layer of the initial channel structure.

[0093] S3, forming an initial second channel layer, wherein the initial second channel layer at least covers the exposed initial first channel layer.

[0094] S4, removing a portion of the initial first channel layer and a portion of the initial second channel layer to form a first channel layer and a second channel layer.

[0095] The following will be combined Figures 7 to 13 The specific process of each step of the above-mentioned preparation method 2000 is described in detail.

[0096] Step S1

[0097] Figure 8 It is a schematic cross-sectional view of a structure formed after a stacked structure 200 and an initial channel structure 300 ′ are formed on a substrate 100 according to a preparation method in one embodiment of the present application.

[0098] like Figures 7 and 8 As shown, step S1 forms a stacked structure and an initial channel structure on a first side of the substrate, wherein the substrate includes a conductive layer, the stacked structure includes alternately stacked gate layers and dielectric layers, and the initial channel structure penetrates the stacked structure along the stacking direction and extends at least into the conductive layer, which may for example include: preparing a substrate 100 including a conductive layer 110; alternately stacking gate sacrificial layers (not shown) and dielectric layers 210 on the first side 100-a of the substrate 100 to form a dielectric stacked structure (not shown); forming an initial channel structure 300' that penetrates the dielectric stacked structure along the stacking direction and extends to the substrate 100, the initial channel structure 300' may include an initial functional layer 320' and an initial first channel layer 330' sequentially formed on the inner wall of the channel hole (not shown); and removing the gate sacrificial layer to form a sacrificial gap (not shown), and forming a gate layer 220 in the sacrificial gap to constitute the stacked structure 200.

[0099] Specifically, in some embodiments, as an example, the substrate 100 can be selected according to the actual requirements of the device, and the substrate 100 is a composite structure, for example, it can include a conductive layer 110, a substrate sacrificial layer 130, and a substrate spacer layer 140 located between the conductive layer 110 and the substrate sacrificial layer 130. The substrate 100 has a first side 100-a and a second side 100-b opposite to each other.

[0100] The substrate sacrificial layer 130 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate or a GOI (Germanium-on-Insulator) substrate, etc. In other embodiments, the substrate sacrificial layer 130 may also include other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc. In addition, the substrate sacrificial layer 130 may also be a composite structure, such as a silicon stack or a germanium silicon stack.

[0101] In addition, in the semiconductor device manufacturing method 2000 provided in the present application, the substrate sacrificial layer 130 can be completely removed in subsequent steps, so an ordinary substrate structure can generally be used without making other structures therein, which not only saves costs but also reduces process difficulty.

[0102] After forming the substrate sacrificial layer 130, a substrate spacer layer 140 may be formed on the substrate sacrificial layer 130 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in this application. The substrate spacer layer 140 may be used to space the substrate sacrificial layer 130 from the subsequently formed conductive layer 110. The substrate spacer layer 140 may include but is not limited to an insulating dielectric material layer such as a silicon oxide layer.

[0103] After forming the substrate spacer layer 140, a conductive layer 110 may be formed on the substrate spacer layer 140 by any one of CVD, PVD and ALD or any combination thereof. The conductive layer 110 is used to form a common source connected to the first channel layer, and the common source is a part of the circuit loop for conducting the memory cell in the semiconductor device. Considering the connection function of the conductive layer 110, the thickness of the conductive layer 110 may be appropriately increased, for example, the thickness of the conductive layer 110 in the z direction may be adjusted to between 50 nanometers and 300 nanometers.

[0104] After forming the substrate 100, the dielectric layer 210 and the gate sacrificial layer can be alternately stacked along the z direction through one or more thin film deposition processes to form a dielectric stack structure on the first side 100-a of the substrate 100. The thin film deposition process may include but is not limited to CVD, PVD, ALD or any combination thereof, which is not limited in the present application.

[0105] In other words, the dielectric stack structure may include multiple pairs of dielectric layers 210 and gate sacrificial layers stacked alternately with each other. For example, the dielectric stack structure may include 64 pairs, 128 pairs, or more than 128 pairs of dielectric layers 210 and gate sacrificial layers. In some embodiments, the dielectric layer 210 and the gate sacrificial layer may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the dielectric layer 210 and the gate sacrificial layer may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, and the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched away and replaced with a conductor layer including a conductive material.

[0106] The preparation method of the dielectric stacking structure of a single stacking structure is described above. In fact, with the continuous increase in the storage demand of semiconductor devices, the storage stack gradually increases. In order to break through the limitations of traditional process limits, a double stacking technology or a multi-stack technology can also be used to form a dielectric stacking structure by stacking a plurality of sub-dielectric stacking structures sequentially in the stacking direction of the dielectric stacking structure, wherein each sub-dielectric stacking structure may include a plurality of insulating layers and gate sacrificial layers alternately stacked. The number of layers of each sub-dielectric stacking structure may be the same or different. Since the content and structure involved in the preparation process of the single-stack dielectric stacking structure described above can be fully or partially applied to the dielectric stacking structure formed by a plurality of sub-dielectric stacking structures described here, the content related or similar thereto will not be repeated. However, it can be understood by those skilled in the art that the subsequent preparation process can be carried out on the basis of a multi-dielectric stacking structure or a single dielectric stacking structure.

[0107] After forming the dielectric stack structure, a channel hole may be formed in the dielectric stack structure, and the channel hole may penetrate the dielectric stack structure along the stacking direction (z direction) of the dielectric stack structure and extend into the substrate 100. Optionally, the channel hole may sequentially penetrate the dielectric stack structure and the conductive layer 110 along the z direction and extend into the substrate spacer layer 140 or the substrate sacrificial layer 130.

[0108] The channel hole may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc. The channel hole may have a cylindrical or pillar shape that penetrates the dielectric stack structure and extends to the substrate 100.

[0109] Furthermore, after forming a dielectric stacking structure using double stacking technology or multi-stack technology, the dielectric stacking structure may include N sub-dielectric stacking structures, and accordingly, the channel hole may also include N×M sub-channel holes, wherein each sub-dielectric stacking structure may include M sub-channel holes, where M≥1 and N≥2. Forming channel holes in a dielectric stacking structure using a double stacking technology or a multi-stack technology may include: forming a first sub-dielectric stacking structure on one side of a substrate, and forming M first sub-channel holes that penetrate the first sub-dielectric stacking structure and extend into the substrate; continuing to form subsequent sub-dielectric stacking structures and sub-channel holes until an N-th sub-dielectric stacking structure and M sub-channel holes located in the N-th sub-dielectric stacking structure are formed, and then filling a hole-filling sacrificial layer in the corresponding sub-channel holes in N-1 sub-dielectric stacking structures other than the N-th sub-dielectric stacking structure; and removing the hole-filling sacrificial layer in the N-1 sub-dielectric stacking structure based on the M sub-channel holes of the N-th sub-dielectric stacking structure, so that the upper and lower adjacent sub-channel holes in the N sub-dielectric stacking structures are at least partially aligned with each other to obtain M channel holes.

[0110] After the channel hole is formed, an initial channel structure 300' may be formed in the channel hole, which may specifically include, for example, forming an initial channel structure 300' including an initial functional layer 320' and an initial first channel layer 330' in the channel hole, wherein the initial functional layer 320' may include an initial blocking layer, an initial charge capture layer and an initial tunneling layer sequentially formed in the channel hole.

[0111] In addition, the initial channel structure 300' may further include an initial channel filling layer 340' surrounded by the initial first channel layer 330', and a channel plug (not shown) located in the initial channel filling layer 340'. Thus, after forming the initial first channel layer 330', the initial channel filling layer 340' and the channel plug may be filled in the remaining space of the channel hole.

[0112] In some embodiments, the initial functional layer 320 ′ and the initial first channel layer 330 ′ may be sequentially formed in the channel hole by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0113] Specifically, the initial functional layer 320' may include an initial blocking layer; an initial charge trapping layer formed on the surface of the initial blocking layer; and an initial tunneling layer formed on the surface of the initial charge trapping layer. The initial blocking layer may include one or more layers, and the one or more layers may include one or more materials. The materials for the initial blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The initial charge trapping layer may include one or more layers, and the one or more layers may include one or more materials. The materials for the initial charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. The initial tunneling layer may include one or more layers, and the one or more layers may include one or more materials. The materials for the initial tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc.

[0114] In some embodiments, the initial first channel layer 330' can be used to transport the required charges (electrons or holes). According to an exemplary embodiment of the present application, the initial first channel layer 330' can be formed on the surface of the initial tunneling layer by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0115] In some embodiments, the initial first channel layer 330' may be a semiconductor layer, and the semiconductor may include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon, etc. In addition, similar to the channel hole, the initial first channel layer 330' may also sequentially penetrate the dielectric stack structure along the z direction and extend into the substrate 100.

[0116] As an option, the initial first channel layer 330' may be a non-doped semiconductor material layer; as another option, the initial first channel layer 330' may be a low-doped semiconductor material layer. In other words, the conductive impurity doping type included in the initial first channel layer 330' may be selected to be the same type of doping element included in the subsequently formed second channel layer, or the conductive impurity doping type included in the initial first channel layer 330' may be selected to be the same type of doping element included in the conductive layer 110 and the subsequently formed second channel layer.

[0117] In addition, the doping concentration of the doping element of the initial first channel layer 330 ′ is lower than the doping concentration of the doping element of the subsequently formed second channel layer; optionally, the doping concentration of the doping element of the initial first channel layer 330 ′ is lower than the doping concentration of the doping element of the conductive layer 110 .

[0118] The method 2000 for manufacturing a semiconductor device according to an embodiment of the present application further includes: forming a channel plug at a top portion of the channel hole away from the substrate 100 .

[0119] Specifically, a filling dielectric layer (not shown) may be used to fill the remaining space of the channel hole. The filling dielectric layer may include an oxidized dielectric layer, such as silicon oxide, etc. An initial channel filling layer 340' may be formed by removing a portion of the filling dielectric layer located at the top of the channel hole, and a semiconductor material may be filled in the space formed after removing part of the filling dielectric layer to form a channel plug connected to the initial first channel layer 330'.

[0120] Furthermore, during the filling process, a plurality of insulating gaps may be formed in the filling dielectric layer by controlling the trench filling process to alleviate structural stress.

[0121] In addition, the method 2000 for preparing a semiconductor device according to an embodiment of the present application further includes an initial gate line gap structure 400 ′ having a spacing from the initial channel structure 300 ′ in a direction (x direction or y direction) perpendicular to the z direction.

[0122] In some embodiments, a gate line gap 410 is formed along the z direction to penetrate the dielectric stack structure and the substrate sacrificial layer 130. In some embodiments, the gate gap 410 having a certain distance from the initial channel structure 300' can be formed by, for example, a dry etching process or a combination of dry and wet etching processes.

[0123] In addition, after forming the gate gap 410 , the method 2000 for manufacturing a semiconductor device provided in the present application further includes forming a gate 230 .

[0124] Specifically, the gate gap 410 can be used as a passage for providing an etchant and a chemical precursor, and all gate sacrificial layers in the dielectric stack structure can be removed by a process such as wet etching to form a gate sacrificial gap (not shown). After the gate sacrificial gap is formed, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form a gate layer 220 in the gate sacrificial gap. The gate layer 220 can be made of a conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide.

[0125] Optionally, before forming the gate layer 220, the method 2000 for preparing a semiconductor device according to an embodiment of the present application further comprises forming a dielectric layer (not shown) on the inner wall of the gate sacrificial gap and the inner wall (or inner side wall) of the gate gap 410 by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. As an option, the dielectric layer may be a high dielectric constant dielectric layer. Furthermore, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form an adhesion layer (e.g., a titanium nitride TiN layer, not shown) between the dielectric layer 210 and the gate layer 220 or between the dielectric layer and the gate layer 220.

[0126] After all the gate sacrificial layers in the dielectric stack structure are replaced with the gate layer 220, the dielectric stack structure is formed as follows: Figure 8 The stacked structure 200 is shown.

[0127] After the gate layer 220 is formed, a thin film deposition process such as CVD, PVD, ALD or any combination thereof or a thermal oxidation process may be used to form an initial first sidewall isolation layer 420' on the inner wall of the gate line gap 410. The initial first sidewall isolation layer 420' includes but is not limited to an insulating dielectric material layer such as a silicon oxide layer.

[0128] As an option, an initial first sidewall spacer 420 ′ is formed on the inner wall of the gate line gap 410 ; and a gap filling layer 430 is formed in the remaining space of the gate line gap 410 , thereby forming an initial gate line gap structure 400 ′.

[0129] A thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the gate gap 410 with a conductive material to form a gap filling layer 430. The gap filling layer 430 may be a semiconductor layer such as a polysilicon layer. Using a semiconductor layer such as a polysilicon layer as the filling body of the gate line gap structure 400 can effectively reduce the deformation of the semiconductor device 1000. Alternatively, the gap filling layer 430 may be an insulating dielectric material layer such as a silicon oxide layer.

[0130] Step S2

[0131] Fig. 9 It is a schematic cross-sectional view of a structure formed after a portion of the substrate 100 is removed according to a preparation method in one embodiment of the present application. Fig.10 It is a schematic cross-sectional view of a structure formed after removing the portion of the initial functional layer 320 ′ extending into the substrate 100 of the initial channel structure 300 ′ according to a preparation method in one embodiment of the present application.

[0132] like Figures 8 to 10 As shown, step S2 removes a portion of the substrate from a second side opposite to the first side to expose the conductive layer, and removes at least a portion of the initial functional layer of the initial channel structure located in the conductive layer to expose the initial first channel layer of the initial channel structure. It may, for example, include: removing a portion of the substrate 100 to expose the initial channel structure 300'; continuing to remove a portion of the substrate 100' to expose the conductive layer 110; and removing at least a portion of the initial functional layer 320' located in the conductive layer 110 to expose the initial first channel layer 330'.

[0133] like Figure 8 and Fig. 9 As shown, in one embodiment of the present application, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove a portion of the substrate 100, such as the substrate sacrificial layer 130, to expose the initial channel structure 300'.

[0134] In addition, by removing a portion of the substrate 100 , the initial gate line gap structure 400 ′ can be exposed while the initial channel structure 300 ′ is exposed.

[0135] like Figures 8 to 10 As shown, in one embodiment of the present application, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to continue removing part of the substrate, such as the substrate spacer layer 140, until the conductive layer 110 is exposed.

[0136] After the conductive layer 110 is exposed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the initial functional layer 320', such as the part of the initial functional layer 320' located in the conductive layer 110, to expose the initial first channel layer 330', and form a plurality of first openings 111 in the conductive layer, wherein the plurality of first openings 111 are used to accommodate the second channel layer formed subsequently. In addition, after removing part of the initial functional layer 320', the functional layer 320 can be formed.

[0137] In addition, in order to simplify the difficulty of the operation process and improve the stability and conductivity of the final channel structure, the process window for forming the second functional layer can be expanded. Specifically, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to expand the size of the first opening 111 in a direction perpendicular to the z direction to form a second opening (not shown). The initial second functional layer for forming the second functional layer can be formed on the surface of the conductive layer 110 and in the second opening.

[0138] In addition, in the process of forming the first opening 111, the portion of the initial first sidewall spacer 420' of the initial gate line gap structure 400' located in the substrate 100 is also removed, exposing the gap filling layer 430, and forming the first sidewall spacer 420. The first sidewall spacer 420 is located between the gap filling layer 430 and the stacked structure 200.

[0139] Step S3

[0140] Fig.11 It is a schematic cross-sectional view of a structure formed after forming an initial second channel layer 350 ′ according to a preparation method in one embodiment of the present application.

[0141] like Figure 10 to Figure 11 As shown, step S3 forms an initial second channel layer, wherein the initial second channel layer at least covers the exposed initial first channel layer, and may for example include: using a thin film deposition process such as CVD, PVD, ALD or any combination thereof to form an initial second channel layer 350' on the surface of the conductive layer 110, the first opening 111 and the surface of the exposed initial first channel layer 330'.

[0142] As an option, the same material as that used to prepare the initial first channel layer 330' can be used to prepare the initial second channel layer 350'. The initial second channel layer 350' can be a semiconductor layer, and the semiconductor can include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon.

[0143] In addition, after performing a process of enlarging the size of the first opening 111 in step S2 , an initial second channel layer 350 ′ may be formed on the surface of the conductive layer 110 , the second opening, and the surface of the exposed initial first channel layer 330 ′.

[0144] In addition, in the process of forming the first opening 111 in step S2, the gap filling layer 430 of the initial gate line gap structure 400' is exposed. As an option, an initial second channel layer 350' can be formed on the surface of the conductive layer 110, the first opening 111 (or the second opening), the surface of the exposed initial first channel layer 330', and the surface of the exposed gap filling layer 430.

[0145] Step S4

[0146] Fig.12 It is a schematic cross-sectional view of a structure formed after forming the second channel layer 350 according to a preparation method in one embodiment of the present application. Fig.13 It is a cross-sectional schematic diagram of a structure formed after a portion of the initial trench filling layer 340 ′ is removed according to a preparation method in one embodiment of the present application.

[0147] like Figures 11 to 13 As shown, step S4 removes part of the initial first channel layer 330' and part of the initial second channel layer 350' to form the first channel layer 330 and the second channel layer 350, which may, for example, include: forming by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove part of the initial first channel layer 330' and part of the initial second channel layer 350' to form the first channel layer 330 and the second channel layer 350.

[0148] Optionally, the second channel layer 350 and the first channel layer 330 have the same length in the z direction. In addition, the lengths of the second channel layer 350 and the first channel layer 330 in the z direction are greater than or equal to the thickness of the conductive layer 110 (in the z direction).

[0149] In one embodiment of the present application, in the process of forming the second channel layer 350 by removing a portion of the initial second channel layer 350', a portion of the initial second channel layer 350' covering the gap filling layer 430 may be removed to form a second sidewall spacer 440. The second sidewall spacer 440 is located between the conductive layer 110 and the gap filling layer 430.

[0150] In addition, after removing part of the initial first channel layer 330 ′ and part of the initial second channel layer 350 ′, the same type of doping elements may be used to dope the initial first channel layer and the initial second channel layer remaining after the removal process.

[0151] Specifically, the remaining initial first channel layer and the remaining initial second channel layer can be doped with doping elements by, for example, an ion implantation process or in a laser annealing process, and a first channel layer 330 and a second channel layer 350 containing doping elements of a single conductivity type are formed by introducing an appropriate amount of dopant (impurity source). The doping elements may include two types (understandable conductivity types), the first type may be P-type, and the second type may be N-type. As an option, N-type dopants (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb)) are used to contribute free electrons and increase the conductivity of the intrinsic semiconductor. As another option, P-type dopants (e.g., boron (B), gallium (Ga), or indium (In)) are used to absorb free electrons and increase the conductivity of the intrinsic semiconductor.

[0152] As an option, the conductive layer 110 may contain the same type of doping elements as the first channel layer 330 and the second channel layer 350. In the process of forming the conductive layer 110, any suitable doping process, such as a chemical vapor doping process, may be used to form the conductive layer 110. Chemical vapor doping refers to the process of doping impurity elements into the film through the gas phase during the CVD film deposition process. In other words, when the CVD process is used, the conductive layer 110 containing doping elements of a single conductivity type can be formed by introducing an appropriate amount of dopant (impurity source).

[0153] The doping concentration of the doping element of the conductive layer 110 and the second channel layer 350 is higher than the impurity doping concentration of the first channel layer 330. Therefore, when the first channel layer 330 is a non-doped semiconductor material layer or a semiconductor material layer doped with a relatively low concentration, a large doping concentration difference of the doping element can be formed between the conductive layer 110 and the second channel layer 350. The concentration of carriers in the first channel layer 330 is much lower than that in the conductive layer 110 and the second channel layer 350, so that the mobility of carriers in the first channel layer 350 can be maintained at a high level, thereby improving the current conduction capability of the first channel layer.

[0154] refer to Fig.12 and Fig.13 As an option, in one embodiment of the present application, a portion of the initial channel filling layer 340' may be removed to form the channel filling layer 340. The removed portion of the initial channel filling layer 340' and the removed portion of the initial first channel layer 330' (such as Fig.11 shown) corresponds.

[0155] Optionally, the length of the channel filling layer 340 in the z direction is greater than the length of the first channel layer 330 in the z direction; optionally, the channel filling layer 340 and the first channel layer 330 have the same length in the z direction. In addition, the length of the channel filling layer 340 and the first channel layer 330 in the z direction is greater than or equal to the thickness of the conductive layer 110 (in the z direction).

[0156] Optionally, after removing part of the initial first channel layer 330' and part of the initial second channel layer 350', the conductive layer 110 and the initial first channel layer 330' and the initial second channel layer 350' remaining after the removal are planarized by, for example, a chemical mechanical polishing (CMP) process, so that the end faces of the first channel layer 330 and the second channel layer 350 are roughly coplanar with the surface of the conductive layer 110, so as to form other parts of the circuit loop for the operation of the memory cell in the semiconductor device on the flat coplanar surface. The coplanarity obtained after the planarization process is conducive to improving the stability of the finally formed semiconductor device.

[0157] Fig.14 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0158] like Fig.14 As shown, at least one embodiment of the present application further provides a storage system 30000. The storage system 30000 may include a controller 32200 and at least one semiconductor device 32100. The semiconductor device 32100 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it.

[0159] The controller 32200 may be coupled to the semiconductor device 32100 through a channel CH to control the semiconductor device 32100 to store data. The semiconductor device 32100 may receive a command CMD and an address ADDR from the controller 32200 through the channel CH and access an area selected from the memory cell array in response to the address. In other words, the semiconductor device 32100 may perform an internal operation corresponding to the command on the area selected by the address.

[0160] In some embodiments, the storage system 30000 may be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system and the method for preparing the semiconductor device provided in the present application have the same beneficial effects as the semiconductor device because the semiconductor device provided in the present application is provided, and are not described in detail here.

[0161] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A semiconductor device, characterized in that: include: Conductive layer; A stacked structure, located on one side of the conductive layer, the stacked structure comprising alternately stacked gate layers and dielectric layers; as well as a channel structure, which penetrates the stacked structure along the stacking direction and extends into the conductive layer, wherein the channel structure includes a first portion and a second portion connected to each other along the stacking direction, Wherein, the first portion penetrates the stacked structure along the stacking direction and includes a first channel layer and a functional layer from the inside to the outside; and The second portion extends into the conductive layer along the stacking direction and includes the first channel layer and the second channel layer from the inside to the outside.

2. The semiconductor device according to claim 1, wherein The second channel layer and the conductive layer have the same thickness in the stacking direction.

3. The semiconductor device according to claim 1, wherein In a direction perpendicular to the stacking direction, a thickness of the second channel layer is greater than a thickness of the first channel layer.

4. The semiconductor device according to claim 1, wherein: The semiconductor material layer included in the first channel layer and the semiconductor material layer included in the second channel layer both contain the same type of doping elements; or The semiconductor material layer included in the first channel layer, the semiconductor material layer included in the second channel layer, and the semiconductor material layer included in the conductive layer all contain the same type of doping elements.

5. The semiconductor device according to claim 4, wherein: A doping concentration of the doping element of the second channel layer is greater than a doping concentration of the doping element of the first channel layer.

6. The semiconductor device according to claim 1, wherein The semiconductor device further includes a substrate located on the other side of the conductive layer opposite to the one side; and The channel structure further includes a channel filling layer surrounded by the first channel layer, Wherein, the channel filling layer penetrates the stacked structure and the conductive layer along the stacking direction and extends into the substrate.

7. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a gate line gap structure having a spacing with the channel structure in a direction perpendicular to the stacking direction, wherein the gate line gap structure comprises a first sub-portion and a second sub-portion connected to each other along the stacking direction, Wherein, the first sub-portion penetrates the stacked structure along the stacking direction and includes a gap filling layer and a first sidewall isolation layer disposed between the stacked structure and the gap filling layer; and The second section at least penetrates the conductive layer along the stacking direction and includes the gap-filling layer and a second sidewall isolation layer disposed between the conductive layer and the gap-filling layer.

8. The semiconductor device according to claim 7, wherein: The first sidewall spacer layer and the second sidewall spacer layer include different materials.

9. The semiconductor device according to claim 7, wherein: The second sidewall isolation layer and the second channel layer include the same material.

10. The semiconductor device according to claim 1, wherein In a direction perpendicular to the stacking direction, the thickness of the second channel layer is greater than or equal to the thickness of the functional layer.

11. The semiconductor device according to claim 1, wherein The second portion penetrates the conductive layer along the stacking direction.

12. The semiconductor device according to claim 1, wherein Different second portions of the channel structures have different thicknesses along the stacking direction.

13. A method for preparing a semiconductor device, characterized in that: include: Forming a stacked structure and an initial channel structure on a first side of a substrate, wherein the substrate comprises a conductive layer, the stacked structure comprises alternately stacked gate layers and dielectric layers, and the initial channel structure penetrates the stacked structure along a stacking direction and at least extends into the conductive layer; From a second side opposite to the first side, removing a portion of the substrate to expose the conductive layer, and removing at least a portion of the initial functional layer of the initial channel structure located in the conductive layer to expose an initial first channel layer of the initial channel structure; forming an initial second channel layer, wherein the initial second channel layer at least covers the exposed initial first channel layer; as well as A portion of the initial first channel layer and a portion of the initial second channel layer are removed to form a first channel layer and a second channel layer.

14. The method according to claim 13, wherein: After removing a portion of the initial first channel layer and a portion of the initial second channel layer, the method further includes: The conductive layer and the initial first channel layer and the initial second channel layer remaining after the removal process are planarized.

15. The method according to claim 13, wherein: The initial channel structure further includes an initial channel filling layer surrounded by the initial first channel layer. After removing a portion of the initial first channel layer and a portion of the initial second channel layer, the method further includes: A portion of the initial channel filling layer is removed, wherein the removed portion of the initial channel filling layer corresponds to the removed portion of the initial first channel layer.

16. The method according to claim 13, wherein: After removing part of the initial first channel layer and part of the initial second channel layer, the method further includes: The initial first channel layer and the initial second channel layer remaining after the removal process are doped with the same type of doping elements.

17. The method according to claim 16, wherein: The method further comprises: The conductive layer is doped with the same type of doping elements.

18. The method according to claim 13, wherein: The stacked structure further includes an initial gate line gap structure having a spacing with the initial channel structure in a direction perpendicular to the stacking direction, the initial gate line gap structure penetrates the stacked structure along the stacking direction and extends to the substrate, and the method further includes: In the process of removing a portion of the substrate and a portion of the initial functional layer of the initial channel structure extending into the substrate, removing a portion of the initial first sidewall isolation layer of the initial gate line gap structure extending into the substrate to expose the gap filling layer of the initial gate line gap structure; covering the exposed gap-filling layer with the initial second channel layer; and removing a portion of the initial second channel layer covering the gap filling layer to form a second sidewall isolation layer, Wherein, the second sidewall isolation layer is located between the conductive layer and the gap filling layer.

19. The method according to claim 13, wherein: The method further comprises: forming a plurality of first openings in the conductive layer by removing at least a portion of the initial functional layer of the initial channel structure located in the conductive layer, before forming an initial second channel layer, wherein the initial second channel layer at least covers the exposed initial first channel layer; Enlarging the size of the first opening in a direction perpendicular to the stacking direction to form a second opening; Wherein, the initial second channel layer at least fills the second opening.

20. A storage system, characterized in that: include: Controller; as well as The semiconductor device according to any one of claims 1 to 12, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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