Semiconductor device and preparation method

Abstract

The invention discloses a semiconductor device and a preparation method, the semiconductor device is provided with a trench, and the trench comprises a gate trench and an emitter trench which are arranged perpendicular to each other; the axis of the gate trench and the axis of the emitter trench have at least one intersection point, the gate trench or the emitter trench is disconnected at the intersection point so that the gate trench is not in contact with the emitter trench, and the disconnected parts of the gate trench and the emitter trench are electrically connected through a conductive material outside the trench; a P well region and an N + doped region are arranged between the gate trench and the emitter trench, the N + doped region is located above the P well region, and one side of the front metal extends to the P well region in a punching mode to realize ohmic contact with the substrate. According to the invention, the extension directions of the gate trench and the emitter trench are set to be two different directions, so that the stress generated by polycrystalline silicon in the trench has two different extension directions, and the two directions can generate opposite stress at the same time, thereby enabling the stress generated in the trench to counteract each other, and improving the reliability of the device. Therefore, the warping degree of the wafer is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] In the semiconductor manufacturing process, the device grooves used in the semiconductor chips of semiconductor devices are mostly oriented in the same direction. When the chip area is large and the grooves reach a certain depth, a large stress will be generated between the filling material in the groove and the wafer substrate, which will bring stress concentrated in one direction to the wafer surface, causing wafer warping, which will directly affect the precise position of the device contact holes, thereby reducing chip performance and yield. Summary of the invention

[0003] Purpose of the invention: In view of the above shortcomings, the present invention provides a semiconductor device and a preparation method thereof.

[0004] Technical solution: To solve the above problems, the present invention adopts a semiconductor device, including a wafer substrate, on which a gate pad, a gate wiring and a groove are arranged, and the wafer substrate is covered with a front metal and an insulating oxide layer; the groove includes a gate groove and an emitter groove arranged perpendicular to each other, and the gate groove and the emitter groove are both filled with a groove conductive material, and the gate groove is connected to the gate wiring; the gate groove axis and the emitter groove axis have at least one intersection, the gate groove or the emitter groove is disconnected at the intersection so that the gate groove does not contact the emitter groove, and the disconnected part of the electrode groove is electrically connected through the conductive material outside the groove; a P-well region and an N+ doped region are provided between the gate groove and the emitter groove, and the N+ doped region is located above the P-well region, and one side of the front metal is extended to the P-well region by punching to achieve ohmic contact with the substrate.

[0005] Furthermore, the insulating oxide layer includes a first insulating oxide layer and a second insulating oxide layer, the first insulating oxide layer covers the through trench and the N+ doped regions on both sides of the trench, the second insulating oxide layer is attached to the front metal and is located below the front metal, and the conductive material outside the trench is located between the first insulating oxide layer and the second insulating oxide layer.

[0006] Furthermore, a contact hole is opened in the second insulating oxide layer, and the front metal passes through the contact hole and extends from the N+ doped region to the P well region.

[0007] Furthermore, the wafer substrate includes an active area and a terminal area arranged outside the active area, and the groove is arranged on the active area; the outer wiring of the gate wiring is surrounded by a rectangle, and the gate groove and the emitter groove form a 45° angle with any side of the rectangle.

[0008] Furthermore, the conductive material outside the trench covers the intersection of the axis of the gate trench and the axis of the emitter trench, and the conductive material outside the trench only connects the disconnected gate trenches or only connects the disconnected emitter trenches at the intersection.

[0009] Furthermore, it is characterized in that all gate grooves are arranged in rows and extend in the same direction, all emitter grooves are arranged in rows and extend in another direction, and the extension direction of the gate grooves is perpendicular to the extension direction of the emitter grooves; the emitter grooves through which each row of gate grooves is disconnected also form a disconnection of the emitter grooves at the intersection with the gate grooves of the adjacent row of gate grooves; the gate grooves through which each row of emitter grooves is disconnected also form a disconnection of the gate grooves at the intersection with the emitter grooves of the adjacent row of emitter grooves.

[0010] Furthermore, the wafer substrate is a silicon substrate, a silicon carbide substrate or a gallium nitride substrate; the conductive material is polycrystalline silicon, a gate oxide layer is provided on the inner wall of the groove, and the conductive material in the groove is filled on the gate oxide layer; the front metal is aluminum, copper or an aluminum-copper alloy, and the insulating oxide layer is borophosphosilicate glass.

[0011] The present invention also provides a method for preparing the semiconductor device, comprising the following steps:

[0012] Step 1, growing a layer of field oxide on the surface of the wafer substrate, and etching the field oxide to form a gate trench and an emitter trench;

[0013] Step 2, growing a gate oxide layer on the inner wall of the gate trench and the emitter trench, and filling the gate trench and the emitter trench with an inner trench conductive material;

[0014] Step 3, etching the surface of the wafer substrate to remove excess conductive material in the groove;

[0015] Step 4: forming a P well region and an N+ doped region between the gate trench and the emitter trench by ion implantation;

[0016] Step 5: Laying an insulating oxide layer on the surface of the wafer substrate;

[0017] Step 6, etching the insulating oxide layer to remove the excess insulating oxide layer, so that the insulating oxide layer only covers the through trench and the N+ doped regions on both sides of the trench, and laying a layer of conductive material outside the trench on the surface of the wafer substrate;

[0018] Step 7, etching the conductive material outside the trench, leaving only the conductive material outside the trench above the insulating oxide layer to achieve electrical connection at the disconnection point;

[0019] Step 8: Lay another insulating oxide layer on the surface of the wafer substrate;

[0020] Step 9, etching openings on the insulating oxide layer for the extension pins to pass through;

[0021] Step 10, covering the front metal on the insulating oxide layer, and extending the extension frame through the opening to the P-well region;

[0022] Step 11: Cover the front metal with a passivation layer and a PI layer, and etch to form a gate bonding area and an emitter bonding area.

[0023] Furthermore, the etching described in step 1 is specifically as follows: laying photoresist on the field oxygen, using a photomask for exposure and development to form a photolithography pattern with the field oxygen and the photoresist, and then performing dry etching using the photoresist as a mask, and the reaction gas passes through the pattern in the photolithography pattern and contacts the wafer substrate 1 to form a gate groove and an emitter groove.

[0024] Furthermore, the P-well region is formed by ion implantation at ≥1150°C for 100-300 minutes, and the N+ doped region is formed by ion implantation at 950°C for 30 minutes and then annealing.

[0025] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: (1) by setting the extension direction of the gate trench and the emitter trench to extend in two different directions, the stress generated by the polysilicon in the trench has two different extension directions, and the two directions can simultaneously generate opposite stresses, thereby making the stresses generated in the trench offset each other, thereby reducing the warping degree of the wafer; (2) by setting the active area trench disconnected, the stress concentration of the polysilicon deposited in the entire trench is reduced, so that in the subsequent process, the polysilicon brings less stress to the trench, thereby reducing the impact on the wafer warping, further improving the wafer warping, and improving the performance and yield of the chip; (3) the preparation method does not require increasing the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of the overall structure of the semiconductor device of the present invention after the insulating oxide layer and the front metal layer are removed;

[0027] Figure 2 for Figure 1 A schematic diagram of the enlarged structure in the middle;

[0028] Figure 3 for Figure 1 Schematic diagram of the structure for removing polysilicon outside the trench;

[0029] Figure 4 for Figure 3 Middle B is an enlarged schematic diagram of the structure;

[0030] Figure 5 It is an enlarged schematic diagram of the trench and polysilicon structure of the present invention;

[0031] Figure 6 for Figure 5 Schematic diagram of the aa section;

[0032] Figure 7 for Figure 5 Schematic diagram of the bb cross section;

[0033] Figure 8 is a schematic diagram of a second groove structure of the present invention;

[0034] Fig. 9 Schematic diagram of the third groove structure of the present invention. DETAILED DESCRIPTION

[0035] like Figure 1 As shown, a semiconductor device in this embodiment includes a wafer substrate 1, a gate pad 4 and a gate trace 5 arranged on the wafer substrate 1, the wafer substrate 1 includes an active area 3 and a terminal area 2 arranged outside the active area 3, a groove is arranged on the active area 3, and a front metal 10 and an insulating oxide layer 9 are also covered on the groove. Figure 1 The schematic diagram of removing the insulating oxide layer and the front metal layer is convenient for intuitively displaying the groove structure. The wafer substrate 1 is a silicon substrate, a silicon carbide substrate or a gallium nitride substrate. The gate wiring 5 includes a first gate wiring 5-1 perpendicular to the gate pad 4 and located above the gate pad 4, a second gate wiring 5-2 located on the left and right sides of the active area 3, a third gate wiring 5-3 located on the lower side of the active area 3, and a fourth gate wiring 5-4 located on the upper side of the active area 3; the second gate wiring 5-2, the third gate wiring 5-3, and the fourth gate wiring 5-4 are in contact with each other at the head and tail and surround the active area 3.

[0036] like Figure 2 As shown, the trenches include a gate trench 6-1 and an emitter trench 6-2 which are arranged perpendicular to each other. With the bottom edge of the active area 3 as the X-axis, the gate trench 6-1 forms an angle of 45° with the X-axis, and the emitter trench 6-2 forms an angle of 135° with the X-axis. Figure 3 and Figure 4As shown, multiple gate trenches 6-1 and emitter trenches 6-2 are symmetrically arranged on the left and right sides of the active area 3. All gate trenches 6-1 on the same side are arranged in a row and extend in the same direction, and all emitter trenches 6-2 are arranged in a row and extend in another direction, and the extension direction of the gate trench 6-1 is perpendicular to the extension direction of the emitter trench 6-2. The inner walls of the gate trench 6-1 and the emitter trench 6-2 are provided with a gate oxide layer, the thickness of the gate oxide layer is 0.05-0.1μm, and the trench is filled with intra-trench polysilicon 7-1. The gate trench 6-1 is connected to the gate wiring 5. The axis of the gate groove 6-1 and the axis of the emitter groove 6-2 have at least one intersection, and the gate groove 6-1 and the emitter groove 6-2 are alternately disconnected at the intersection so that the gate groove 6-1 does not contact the emitter groove 6-2, that is, the emitter groove 6-2 passing through each row of the gate groove 6-1 disconnection also forms the disconnection of the emitter groove 6-2 at the intersection with the gate groove 6-1 in the adjacent row of the gate groove 6-1; the gate groove 6-1 passing through each row of the emitter groove 6-2 disconnection also forms the disconnection of the gate groove 6-1 at the intersection with the emitter groove 6-2 in the adjacent row of the emitter groove 6-2, and the disconnection is shown in 6-11 and 6-21 in the figure. The depth and width of the gate groove 6-1 and the emitter groove 6-2 are the same, the depth is 4-8μm, the width is 1-4μm, the length is 34-40μm, and the disconnection distance is 8-14μm. In this embodiment, the gate trench 6-1 and the emitter trench 6-2 are each 48 μm long, the length of a single trench is 40 μm, the disconnection distance is 8 μm, and the spacing between parallel trenches is 24 μm. In this embodiment, the gate trench 6-1 or the emitter trench 6-2 is alternately disconnected at the intersection, and the intersections can also be all disconnected by the gate trench 6-1 or all disconnected by the emitter trench 6-2, such as Figure 8 and Fig. 9 As shown. The conductive material 7-2 outside the groove covers the intersection of the axis of the gate groove 6-1 and the axis of the emitter groove 6-2, and the conductive material 7-2 outside the groove only connects the disconnected gate groove 6-1 or only connects the disconnected emitter groove 6-2 at the intersection to achieve electrical connection of the disconnected groove. The polysilicon 7-2 outside the groove can be in a variety of shapes, such as rectangular, circular, polygonal, etc., with a thickness of 0.6-1μm, a length of at least 10μm, and must exceed the edge of the disconnection by at least 1μm. In this embodiment, the polysilicon 7-2 outside the groove is a square with a side length of 10μm, and the distance between adjacent polysilicon 7-2 outside the groove is 38μm.

[0037] like Figures 5 to 7As shown, a P-well region 8-2 and an N+ doped region 8-1 are provided between the gate trench 6-1 and the emitter trench 6-2, and the N+ doped region 8-1 is located above the P-well region 8-2. The insulating oxide layer 9 includes a first insulating oxide layer 9-1 and a second insulating oxide layer 9-2. The first insulating oxide layer 9-1 covers the through trench and the N+ doped region 8-1 on both sides of the trench. The second insulating oxide layer 9-2 is attached to the front metal 10 and is located below the front metal 10. The polysilicon 7-2 outside the trench is located between the first insulating oxide layer 9-1 and the second insulating oxide layer 9-2. A contact hole 11 is opened on the second insulating oxide layer 9-2. The front metal 10 passes through the contact hole 11 and the N+ doped region 8-1 and extends to the P-well region 8-2 to achieve ohmic contact with the substrate. The front metal 10 is aluminum, copper or aluminum-copper alloy, with a thickness of 4-6μm, and serves as the front emitter of the device. The insulating oxide layer 9 is borophosphosilicate glass (BPSG) with a thickness of 0.8-1.2 μm. Borophosphosilicate glass has excellent hole-filling ability and can improve the flatness of the entire silicon wafer surface, thereby providing a larger process range for device lithography and post-processing.

[0038] The present invention also provides a method for preparing the semiconductor device, comprising the following steps:

[0039] Step 1, provide a wafer substrate 1, divide the wafer substrate 1 into an active area 3 and a terminal area 2, and grow a layer of field oxide on the surface of the wafer substrate 1. Lay photoresist on the field oxide, use a photomask to expose and develop, so that the field oxide and the photoresist form a photolithography pattern, and then use the photoresist as a mask to perform dry etching, and the reaction gas passes through the pattern in the photolithography pattern and contacts the wafer substrate 1 to form a gate trench 6-1 and an emitter trench 6-2, and the gate trench 6-1 and the emitter trench 6-2 are both located in the active area 3.

[0040] Step 2: grow a layer of gate oxide on the inner wall of the gate trench 6-1 and the emitter trench 6-2, and fill the gate trench 6-1 and the emitter trench 6-2 with intra-trench polysilicon 7-1.

[0041] Step 3: Etch the surface of the wafer substrate 1 to remove the redundant polysilicon 7 - 1 in the groove.

[0042] Step 4: Form a P-well region 8-2 and an N+ doping region 8-1 between the gate trench 6-1 and the emitter trench 6-2 by ion implantation. The P-well region 8-2 is formed by ion implantation at ≥1150°C for 100-300 minutes, and the N+ doping region 8-1 is formed by ion implantation at 950°C for 30 minutes and annealing.

[0043] Step 5: Lay a first insulating oxide layer 9 - 1 on the surface of the wafer substrate 1 .

[0044] Step 6: Etch the insulating oxide layer 9 to remove the redundant first insulating oxide layer 9-1, so that it only covers the through trench and the N+ doped regions 8-1 on both sides of the trench, and lay a layer of polysilicon 7-2 outside the trench on the surface of the wafer substrate 1.

[0045] Step 7: Etch the conductive material 7-2 outside the trench, and only retain the polysilicon 7-2 outside the trench above the first insulating oxide layer 9-1 to achieve electrical connection at the disconnection point.

[0046] Step 8: Lay another second insulating oxide layer 9 - 2 on the surface of the wafer substrate 1 .

[0047] Step 9: Etch a contact hole 11 on the second insulating oxide layer 9-2 for the extended foot to pass through.

[0048] Step 10: Cover the second insulating oxide layer 9-2 with a front metal 10, and extend the extension frame through the contact hole 11 to the P-well region 8-2.

[0049] Step 11: Cover the front metal 10 with a passivation layer and a PI layer, and etch to form a gate bonding area and an emitter bonding area.

[0050] The present invention sets the extension direction of the gate trench 6-1 and the emitter trench 6-2 to extend in two different directions, so that the stress generated by the polysilicon in the trench has two different extension directions, and the two directions can simultaneously generate opposite stresses, thereby making the stresses generated in the trench offset each other, thereby reducing the degree of wafer warpage. In addition, by setting the active area trench disconnected, the stress concentration of polysilicon deposited in the entire trench is reduced, so that in the subsequent process, the polysilicon brings less stress to the trench, thereby reducing the impact on wafer warpage, further improving wafer warpage, and improving chip performance and yield. At the same time, the preparation method of the present invention does not need to increase process costs.

Claims

1. A semiconductor device, comprising a wafer substrate (1), on which a gate pad (4), a gate trace (5) and a groove are arranged, and the wafer substrate (1) is covered with a front metal (10) and an insulating oxide layer (9); characterized in that: The groove comprises a gate groove (6-1) and an emitter groove (6-2) which are arranged perpendicular to each other, the gate groove (6-1) and the emitter groove (6-2) are both filled with a groove conductive material (7-1), the gate groove (6-1) is connected to the gate wiring (5), the axis of the gate groove (6-1) and the axis of the emitter groove (6-2) have at least one intersection, the gate groove (6-1) or the emitter groove (6-2) is disconnected at the intersection so that the gate groove (6-1) is not in contact with the emitter trench (6-2), and the disconnected portion of the electrode trench is electrically connected through the conductive material (7-2) outside the trench; a P-well region (8-2) and an N+ doped region (8-1) are provided between the gate trench (6-1) and the emitter trench (6-2), and the N+ doped region (8-1) is located above the P-well region (8-2); one side of the front metal (10) is extended to the P-well region (8-2) by punching to achieve ohmic contact with the substrate.

2. The semiconductor device according to claim 1, wherein The insulating oxide layer (9) comprises a first insulating oxide layer (9-1) and a second insulating oxide layer (9-2); the first insulating oxide layer (9-1) covers a through trench and an N+ doped region (8-1) on both sides of the trench; the second insulating oxide layer (9-2) is attached to a front metal (10) and is located below the front metal (10); and the outer trench conductive material (7-2) is located between the first insulating oxide layer (9-1) and the second insulating oxide layer (9-2).

3. The semiconductor device according to claim 2, wherein: A contact hole (11) is formed on the second insulating oxide layer (9-2), and the front metal (10) passes through the contact hole (11) and the N+ doped region (8-1) and extends to the P well region (8-2).

4. The semiconductor device according to claim 1, wherein The wafer substrate (1) comprises an active area (3) and a terminal area (2) arranged outside the active area (3), and a groove is arranged on the active area (3); the outer wiring of the gate wiring (5) surrounds a rectangle, and the gate groove (6-1) and the emitter groove (6-2) form an angle of 45° with any side of the rectangle.

5. The semiconductor device according to claim 4, wherein: The outer groove conductive material (7-2) covers the intersection position of the axis of the gate groove (6-1) and the axis of the emitter groove (6-2), and the outer groove conductive material (7-2) only connects the disconnected gate groove (6-1) or only connects the disconnected emitter groove (6-2) at the intersection position.

6. The semiconductor device according to claim 1 or 4, characterized in that All gate grooves (6-1) are arranged in a row and extend in the same direction, and all emitter grooves (6-2) are arranged in a row and extend in another direction, and the extension direction of the gate grooves (6-1) is perpendicular to the extension direction of the emitter grooves (6-2); the emitter grooves (6-2) passing through the disconnected part of each row of gate grooves (6-1) also form a disconnection of the emitter grooves (6-2) at the intersection of the gate grooves (6-1) in the adjacent row of the gate grooves (6-1); the gate grooves (6-1) passing through the disconnected part of each row of emitter grooves (6-2) also form a disconnection of the gate grooves (6-1) at the intersection of the emitter grooves (6-2) in the adjacent row of the emitter grooves (6-2).

7. The semiconductor device according to claim 2, wherein: The wafer substrate (1) is a silicon substrate, a silicon carbide substrate or a gallium nitride substrate; the conductive material is polycrystalline silicon, a gate oxide layer is provided on the inner wall of the groove, and the conductive material (7-1) in the groove is filled on the gate oxide layer; the front metal (10) is aluminum, copper or an aluminum-copper alloy, and the insulating oxide layer (9) is borophosphosilicate glass.

8. A method for preparing a semiconductor device according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1, growing a layer of field oxide on the surface of a wafer substrate (1), and etching the field oxide to form a gate trench (6-1) and an emitter trench (6-2); Step 2, growing a gate oxide layer on the inner wall of the gate trench (6-1) and the emitter trench (6-2), and filling the gate trench (6-1) and the emitter trench (6-2) with an intra-trench conductive material (7-1); Step 3, etching the surface of the wafer substrate (1) to remove excess conductive material in the groove (7-1); Step 4: forming a P well region (8-2) and an N+ doped region (8-1) between the gate trench (6-1) and the emitter trench (6-2) by ion implantation; Step 5: Laying an insulating oxide layer (9) on the surface of the wafer substrate (1); Step 6, etching the insulating oxide layer (9) to remove the excess insulating oxide layer (9), so that the insulating oxide layer (9) only covers the through trench and the N+ doped regions (8-1) on both sides of the trench, and laying a layer of conductive material (7-2) outside the trench on the surface of the wafer substrate (1); Step 7, etching the conductive material (7-2) outside the trench, leaving only the conductive material (7-2) outside the trench above the insulating oxide layer (9) to achieve electrical connection at the disconnection point; Step 8, laying another insulating oxide layer (9) on the surface of the wafer substrate (1); Step 9, etching an opening on the insulating oxide layer (9) for the extension pin to pass through; Step 10, covering the front metal (10) on the insulating oxide layer (9), and extending the extension frame through the opening to the P-well region (8-2); Step 11: Cover the front metal (10) with a passivation layer and a PI layer, and etch to form a gate bonding area and an emitter bonding area.

9. The preparation method according to claim 8, characterized in that: The etching in step 1 is specifically as follows: laying photoresist on the field oxide, using a photomask for exposure and development to form a photolithography pattern with the field oxide and the photoresist, and then performing dry etching using the photoresist as a mask, and the reaction gas passes through the pattern in the photolithography pattern and contacts the wafer substrate 1 to form a gate trench (6-1) and an emitter trench (6-2).

10. The preparation method according to claim 9, characterized in that: The P well region (8-2) is formed by ion implantation at ≥1150°C for 100-300 minutes, and the N+ doped region (8-1) is formed by ion implantation at 950°C for 30 minutes and then annealing.

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